赛鸽项目CAN协议第一次提交,目前已实现串口和CAN数据收发,协议完成10个

main
masst 2 months ago
commit edd6abfb82

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out/
*.uvguix.*
JLinkLog.txt
JLinkSettings.ini
EventRecorderStub.scvd
settings/
*.dep
*.ewd
*.ewt
# Prerequisites
*.d
# Object files
*.o
*.ko
*.obj
*.elf
# Linker output
*.ilk
*.map
*.exp
# Precompiled Headers
*.gch
*.pch
# Libraries
*.lib
*.a
*.la
*.lo
# Shared objects (inc. Windows DLLs)
*.dll
*.so
*.so.*
*.dylib
# Executables
*.exe
*.out
*.app
*.i*86
*.x86_64
*.hex
# Debug files
*.dSYM/
*.su
*.idb
*.pdb
# Kernel Module Compile Results
*.mod*
*.cmd
.tmp_versions/
modules.order
Module.symvers
Mkfile.old
dkms.conf

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#include <stdint.h>
#include <string.h>
#define cb_item_t uint8_t // item type
#define CB_ITEM_N 1024 // item number实际可存入数据少一个留一个空位表示满以区别于空
typedef struct
{
cb_item_t buf[CB_ITEM_N];
int wrptr; // 写指针
int rdptr; // 读指针
} CircleBuffer_t;
/* Element Count in buffer */
static int CirBuf_Count(CircleBuffer_t *cirbuf)
{
return (cirbuf->wrptr - cirbuf->rdptr) & (CB_ITEM_N - 1);
}
/* Space available in buffer */
static int CirBuf_Space(CircleBuffer_t *cirbuf)
{
return (cirbuf->rdptr - cirbuf->wrptr - 1) & (CB_ITEM_N - 1);
}
static int CirBuf_Empty(CircleBuffer_t *cirbuf)
{
return CirBuf_Count(cirbuf) == 0;
}
static int CirBuf_Full(CircleBuffer_t *cirbuf)
{
return CirBuf_Space(cirbuf) == 0;
}
static void CirBuf_Clear(CircleBuffer_t *cirbuf)
{
cirbuf->rdptr = cirbuf->wrptr;
}
/**
* @brief
* @param cirbuf
* @param buf
* @param num
* @return int
*/
static int CirBuf_Write(CircleBuffer_t *cirbuf, cb_item_t *buf, int num) {
int n; // 临时变量,记录当前可写入的空间大小
// 情况1写指针(wrptr)在读指针(rdptr)之后或相等(未绕环)
if (cirbuf->wrptr >= cirbuf->rdptr) {
// 计算从写指针到缓冲区末尾的剩余空间CB_ITEM_N - wrptr
n = CB_ITEM_N - cirbuf->wrptr;
// 特殊情况如果读指针在0位置需保留一个空位以避免与读指针重合判断缓冲区满的条件
if (cirbuf->rdptr == 0)
n -= 1; // 减少一个可写入位置
// 取最小值:避免写入数量超过当前段剩余空间
n = (n >= num) ? num : n;
// 将数据从源缓冲区拷贝到环形缓冲区
memcpy(&cirbuf->buf[cirbuf->wrptr], buf, n * sizeof(cb_item_t));
// 更新写指针(考虑绕环)
cirbuf->wrptr = (cirbuf->wrptr + n) % CB_ITEM_N;
// 终止条件:已写入足够数量或缓冲区已满
if ((n == num) || CirBuf_Full(cirbuf)) {
return n;
}
// 递归写入剩余数据(从缓冲区头部开始)
else {
return n + CirBuf_Write(cirbuf, &buf[n], num - n);
}
}
// 情况2写指针(wrptr)在读指针(rdptr)之前(已绕环)
else {
// 计算剩余可写入空间rdptr - wrptr - 1
n = CirBuf_Space(cirbuf);
// 取最小值:避免写入数量超过剩余空间
n = (n >= num) ? num : n;
// 拷贝数据到环形缓冲区
memcpy(&cirbuf->buf[cirbuf->wrptr], buf, n * sizeof(cb_item_t));
// 更新写指针(线性增加,无需绕环)
cirbuf->wrptr += n;
return n; // 返回实际写入数量
}
}
/**
* @brief
* @param cirbuf
* @param buf
* @param num
* @return int
*/
static int CirBuf_Read(CircleBuffer_t *cirbuf, cb_item_t *buf, int num) {
int n; // 临时变量,记录当前可读取的数据量
// 情况1写指针(wrptr)在读指针(rdptr)之后或相等(未绕环)
if (cirbuf->wrptr >= cirbuf->rdptr) {
// 计算可读取的数据项数量wrptr - rdptr
n = CirBuf_Count(cirbuf);
// 取最小值:避免请求数量超过实际可读数量
n = (n >= num) ? num : n;
// 从环形缓冲区拷贝数据到目标缓冲区
memcpy(buf, &cirbuf->buf[cirbuf->rdptr], n * sizeof(cb_item_t));
// 更新读指针(线性增加)
cirbuf->rdptr += n;
return n; // 返回实际读取数量
}
// 情况2写指针(wrptr)在读指针(rdptr)之前(已绕环)
else {
// 计算从读指针到缓冲区末尾的数据项数量CB_ITEM_N - rdptr
n = CB_ITEM_N - cirbuf->rdptr;
// 取最小值:避免请求数量超过当前段可读数量
n = (n >= num) ? num : n;
// 拷贝当前段数据到目标缓冲区
memcpy(buf, &cirbuf->buf[cirbuf->rdptr], n * sizeof(cb_item_t));
// 更新读指针(考虑绕环)
cirbuf->rdptr = (cirbuf->rdptr + n) % CB_ITEM_N;
// 终止条件:已读取足够数量或缓冲区为空
if ((n == num) || CirBuf_Empty(cirbuf)) {
return n;
}
// 递归读取剩余数据(从缓冲区头部开始)
else {
return n + CirBuf_Read(cirbuf, &buf[n], num - n);
}
}
}

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#include "jw_bsp_init.h"
#include "SWM221.h"
/*
* SerialInit
* UART0
*
*
* PA.0UART0_RXPA.1UART0_TX
* 5760081
* FIFO3使
* 10使
*/
static void SerialInit(void)
{
UART_InitStructure UART_initStruct;
// 配置PA0引脚为UART0接收功能输入
PORT_Init(PORTA, PIN0, PORTA_PIN0_UART0_RX, 1);
// 配置PA1引脚为UART0发送功能输出
PORT_Init(PORTA, PIN1, PORTA_PIN1_UART0_TX, 0);
// 初始化UART配置结构体
UART_initStruct.Baudrate = 115200; // 波特率115200bps
UART_initStruct.DataBits = UART_DATA_8BIT; // 8位数据位
UART_initStruct.Parity = UART_PARITY_NONE; // 无校验
UART_initStruct.StopBits = UART_STOP_1BIT; // 1位停止位
UART_initStruct.RXThreshold = 3; // 接收FIFO阈值3字节
UART_initStruct.RXThresholdIEn = 1; // 接收阈值中断
UART_initStruct.TXThreshold = 3; // 发送FIFO阈值3字节
UART_initStruct.TXThresholdIEn = 0; // 禁用发送阈值中断
UART_initStruct.TimeoutTime = 10; // 接收超时时间单位依硬件而定10个字符时间内未接收到新的数据则触发超时中断
UART_initStruct.TimeoutIEn = 1; // 启用超时中断
// 应用配置并启用UART0
UART_Init(UART0, &UART_initStruct); // 初始化UART0参数
UART_Open(UART0); // 启动UART0通信
}
/* CAN端口初始化配置 */
static void CanInit(void)
{
CAN_InitStructure CAN_initStruct; // CAN初始化结构体
// 初始化PORTB引脚7和8为CAN0的RX/TX功能
// 参数:端口, 引脚号, 复用功能, 上拉/下拉使能1-使能0-禁用)
PORT_Init(PORTB, PIN7, PORTB_PIN7_CAN0_RX, 1); // CAN0接收引脚
PORT_Init(PORTB, PIN8, PORTB_PIN8_CAN0_TX, 0); // CAN0发送引脚
// 配置CAN初始化参数
CAN_initStruct.Mode = CAN_MODE_NORMAL; //常规模式 // 自测模式需短接TX和RXCAN_MODE_SELFTEST;//
CAN_initStruct.CAN_bs1 = CAN_BS1_5tq; // 位时间段1占5个时间单位
CAN_initStruct.CAN_bs2 = CAN_BS2_4tq; // 位时间段2占4个时间单位
CAN_initStruct.CAN_sjw = CAN_SJW_2tq; // 同步跳转宽度2个时间单位
CAN_initStruct.Baudrate = 500000; // 波特率500kbps
CAN_initStruct.RXNotEmptyIEn = 1; // 启用接收中断
CAN_initStruct.ArbitrLostIEn = 0; // 禁用仲裁丢失中断
CAN_initStruct.ErrPassiveIEn = 1; // 启用错误被动中断
CAN_Init(CAN0, &CAN_initStruct); // 应用配置初始化CAN0
/* CAN中断 */
CAN_INTEn(CAN0, CAN_IT_ERR_WARN | CAN_IT_RX_OVERFLOW);
// /* 过滤器16位ID模式 */
// CAN_SetFilter16b(CAN0, CAN_FILTER_1, 0x200, 0x7FE, 0x101, 0x7F8); //ID1:0x200,0x201; ID2:0x101~0x104
// CAN_SetFilter16b(CAN0, CAN_FILTER_2, 0x130, 0x7FF, 0x150, 0x7FF); //ID1:0x130; ID2:0x150
// CAN_SetFilter16b(CAN0, CAN_FILTER_3, 0x500, 0x7FC, 0x600, 0x7FC); //ID1:0x500~0x503; ID2:0x600~0x602
// CAN_SetFilter16b(CAN0, CAN_FILTER_4, 0x640, 0x7FF, 0x650, 0x7FF); //ID1:0x640; ID2:0x650
// CAN_SetFilter16b(CAN0, CAN_FILTER_5, 0x630, 0x7FF, 0x631, 0x7FE); //ID1:0x630; ID2:0x631~0x632
//
// /* 过滤器32位ID模式 */
// CAN_SetFilter32b(CAN0, CAN_FILTER_6, 0x1000FFA0, 0x1FF8FFFF); //接收扩展ID为0x1000FFAx~0x1004FFAx的帧
// CAN_SetFilter32b(CAN0, CAN_FILTER_7, 0x1011FFA7, 0x1FFEFFFF); //接收扩展ID为0x1011FFA7,0x1012FFA7的帧
// CAN_SetFilter32b(CAN0, CAN_FILTER_8, 0x1020FFA0, 0x1FF0FFFF); //接收扩展ID为0x1020FFAx~0x1028FFAx的帧
// CAN_SetFilter32b(CAN0, CAN_FILTER_9, 0x1030FFA0, 0x1FFCFFFF); //接收扩展ID为0x1030FFAx~0x1033FFAx的帧
CAN_Open(CAN0); // 启动CAN0控制器
}
/**
* @brief SysTick1ms
* @note
*/
static void SysTick_Configuration(void)
{
/* 调用SysTick_Config函数配置1ms中断
- SystemCoreClock/1000CPU1KHz
- 0 */
if (SysTick_Config(SystemCoreClock / 1000)) // 1ms tick
{
LOG("SysTick ERROR !!!\r\n");
/* 错误处理:初始化失败时卡死程序 */
while (1);
}
/* 设置SysTick中断优先级为最高0x00
- SysTick_IRQn */
NVIC_SetPriority(SysTick_IRQn, 0x00);
}
void SysTick_Handler(void)
{
//Timer_Task_1ms();
}
/********** 系统初始化 ********/
void bsp_init(void)
{
SystemInit();
GPIO_Init(GPIOA, PIN3, 1, 0, 1, 0); //输出MCU拉低使能
SerialInit(); //串口初始化
CanInit();
SysTick_Configuration(); // 配置SysTick系统定时器用于产生定时中断
}

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#ifndef _JW_BSP_INIT_H__
#define _JW_BSP_INIT_H__
#include "JW_RTT.h"
#define LOG(format,...) jw_log(format, ##__VA_ARGS__)
#define LOG_ORG(format,...) print_log(format, ##__VA_ARGS__)
extern void bsp_init(void);
#endif

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#include "jw_can.h"
#include "SWM221.h"

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/*********************************************************
*** 6CANgeneral_cmd,MC,BMS,VCU,HIMI,ABS, **********
*** V1.10 **********
**********************************************************/
#ifndef __JW_CAN_H__
#define __JW_CAN_H__
#include <stdint.h>
#include <stdbool.h>
/******************* 通用命令 general_cmd *******************/
typedef struct{
struct{
uint8_t main_sw_ver; //软件主版本号
uint8_t sub_sw_ver; //软件子版本号
uint8_t min_sw_ver; //软件小版本号
uint8_t main_hw_ver; //硬件主版本号
uint8_t sub_hw_ver; //硬件子版本号
uint8_t min_hw_ver; //硬件小版本号
uint16_t rsv;
}info_1_0x0101;
struct{
uint8_t sn_pack_num; //SN包序号(0SN数据0~5 1SN数据6~11 2SN数据12~17)
uint8_t sn_total_lenght;//SN总长度
uint8_t sn_data[6]; //SN数据
}info_2_0x0102;
}General_info_query; //通用信息查询
typedef struct{
uint8_t bus_control; //总线控制(0总线激活 1总线静默)
}General_set_0x0201; //通用设置
typedef struct{
struct{
uint32_t file_leng; //文件长度
uint32_t total_pack_num;//总包数
}ota_star_0x01; //OTA开始
struct{
uint32_t pack_number; //包序号
uint32_t pack_crc; //总CRC
}pack_info_0x02; //当前包信息
uint8_t data_0x03[8];
struct{
uint32_t pack_number; //包序号
uint16_t pack_crc; //总CRC
uint16_t rsv;
}verify_pack_0x04; //校验当前包
uint8_t ota_end_0x05[8]; //OTA结束
}OTA_cmd_0x10;
/******************* MC *******************/
//功能开关选项
typedef enum {
Off = 0x00, // 关闭功能
On = 0x01, // 开启功能
Invalid = 0x03 // 无效设置
}Fun_State;
/* 灯光颜色枚举(与协议对应) */
typedef enum {
COLOR_NO_REQUEST = 0x0,
COLOR_WHITE = 0x1,
COLOR_1 = 0x2,
COLOR_2 = 0x3,
COLOR_3 = 0x4,
COLOR_4 = 0x5,
COLOR_5 = 0x6,
COLOR_6 = 0x7,
COLOR_7 = 0x8,
COLOR_RANDOM = 0x9,
COLOR_RESERVED = 0xA // 0xA~0xF均为保留值
} color_set;
/* 功能开关状态 */
typedef enum {
FUNC_OFF = 0x00,
FUNC_ON = 0x01,
FUNC_INVALID= 0x03
}Rq_sta; //请求状态
typedef enum {
no_req = 0x0,
white_until = 0x1,
yellow_until = 0x2,
white_flash = 0x3,
yellow_flash = 0x4,
req_off = 0x5
}upper_set; //前照灯远光
// 功能开关设置0x20_0x01
typedef struct {
struct {
uint8_t voltage_select : 4; // 0:48V, 1:60V, 2:72V, 0xF:无效
uint8_t startup_mode : 4; // 0:节能, 1:标准, 2:运动, 0xF:无效
} byte0;
struct {
uint8_t gear_select : 4; //挡位选择, 0-5, 0xF:无效
uint8_t reserved : 4;
} byte1;
uint8_t OV_threshold; //过压阈值 byte2
uint8_t UV_threshold; //欠压阈值 byte3
uint8_t bus_current; //母线电流 byte4
uint8_t phase_current; //相线电流 byte5
struct {
uint8_t vehicle_type : 4; //车型 0:国标, 1:电轻摩, 2:电摩
uint8_t battery_mode : 1; // 0:铅酸, 1:锂电
uint8_t supported_voltages : 3; // bit5:48V, bit6:60V, bit7:72V
} byte6;
uint8_t reserved_byte7; // byte7
}MC_fun_swit_0x2001;
// 功能开关0x20_0x02
typedef struct {
struct {
uint8_t speed_limit : 2; // bit0-1 限速
uint8_t cruise_control : 2; // bit2-3 定速巡航
uint8_t rsv1 : 2; // bit4-5 倒车功能
uint8_t hill_holder : 2; // bit6-7 驻坡功能
} byte0;
struct {
uint8_t hdc : 2; // bit0-1 陡坡缓降功能
uint8_t tcs : 2; // bit2-3 TCS功能
uint8_t push_assist : 2; // bit4-5 辅助推车
uint8_t energy_recovery : 2; // bit6-7 能量回收
} byte1;
struct {
uint8_t soft_start : 2; // bit0-1 软硬启动
uint8_t seat_detect : 2; // bit2-3 坐垫检测
uint8_t stand_detect : 2; // bit4-5 边撑检测
uint8_t rsv2 : 2; // bit6-7
} byte2;
}MC_fun_swit_0x2002;
// 功能控制0x21_0x01
typedef struct {
uint8_t power_output; // 0:关闭, 1:开启 动力输出
}MC_Fun_Control_0x2101;
typedef struct {
struct {
uint8_t voltage_select : 4; // 0:48V, 1:60V, 2:72V, 0xF:无效
uint8_t startup_mode : 4; // 0:节能, 1:标准, 2:运动, 0xF:无效
} byte0;
struct {
uint8_t gear_select : 4; //挡位选择, 0-5, 0xF:无效
uint8_t reserved : 4;
} byte1;
uint8_t OV_threshold; //过压阈值 byte2
uint8_t UV_threshold; //欠压阈值 byte3
uint8_t bus_current; //母线电流 byte4
uint8_t phase_current; //相线电流 byte5
struct {
uint8_t vehicle_type : 4; //车型 0:国标, 1:电轻摩, 2:电摩
uint8_t battery_mode : 1; // 0:铅酸, 1:锂电
uint8_t supported_voltages : 3; // bit5:48V, bit6:60V, bit7:72V
} byte6;
uint8_t rsv_byte7; // byte7
}MC_Sys_Info_0x2201; //系统信息 200ms
typedef struct {
struct {
uint8_t speed_limit : 2; // bit0-1 限速
uint8_t cruise_control : 2; // bit2-3 定速巡航
uint8_t rsv1 : 2; // bit4-5 倒车功能
uint8_t hill_holder : 2; // bit6-7 驻坡功能
} byte0;
struct {
uint8_t hdc : 2; // bit0-1 陡坡缓降功能
uint8_t tcs : 2; // bit2-3 TCS功能
uint8_t push_assist : 2; // bit4-5 辅助推车
uint8_t energy_recovery : 2; // bit6-7 能量回收
} byte1;
struct {
uint8_t soft_start : 2; // bit0-1 软硬启动
uint8_t seat_detect : 2; // bit2-3 坐垫检测
uint8_t stand_detect : 2; // bit4-5 边撑检测
uint8_t rsv2 : 2; // bit6-7
} byte2;
}MC_Sys_Info_0x2202; //系统信息 200ms
typedef struct {
struct {
uint32_t MOSFET:1; //MOSFET故障
uint32_t Drive:1; //驱动故障
uint32_t OC:1; //过流故障
uint32_t OV:1; //过压故障
uint32_t OT:1; //过温故障
uint32_t UV:1; //欠压故障
uint32_t Motor_phase_loss:1; //电机缺相故障
uint32_t Motor_Hall:1; //电机霍尔故障
uint32_t Motor_OT:1; //电机过温故障
uint32_t Motor_block:1; //电机堵转故障
uint32_t Throttle:1; //转把故障
uint32_t Brake_failure:1; //刹车故障
uint32_t rsv:20;
}Fault;
struct {
uint32_t Gear:3; //档位
uint32_t Brake:1; //刹车状态
uint32_t Anti_theft:1; //防盗状态
uint32_t Speed_limit:1; //限速状态
uint32_t Cruising:1; //巡航状态
uint32_t Reverse:1; //倒车状态
uint32_t EBS:1; //EBS状态
uint32_t Hill_Holder:1; //驻坡状态
uint32_t HDC:1; //陡坡缓降状态
uint32_t Temple_prot:1; //单撑保护状态
uint32_t READY:1; //READY状态
uint32_t Charge_prot:1; //充电保护状态
uint32_t TCS_fun_enable:1; //TCS功能使能
uint32_t Pause_or_disable:1; //P档/禁用状态
uint32_t Gravity_detect:1; //重力检测
uint32_t stand_detect : 1; //边撑检测
uint32_t rsv:14;
}State;
}MC_RealTime_0x2301; //实时数据 200ms
typedef struct{
struct{
uint8_t speed_G:4; //0x0无三速控制器;0x1D1档低速;0x2D2档中速 ;0x3D3档高速
uint8_t P_G:1;
uint8_t R_G:1;
uint8_t T_G:1;
uint8_t rsv:1;
}Gear_position;
uint16_t Motor_speed; //电机转速
uint8_t Motor_temp; //电机温度
uint16_t speed; //速度
}MC_RealTime_0x2302; //实时数据 200ms
typedef struct{
uint16_t vol; //实时电压
uint16_t cur; //实时电流
uint8_t dump_energy; //剩余电量
uint8_t control_temp; //控制器温度
}MC_RealTime_0x2303; //实时数据 2000ms
typedef struct{
uint16_t Tyre_speed; //轮胎转速
uint16_t Tyre_C; //轮胎周长
uint8_t Throttle_value; //转把开度
uint8_t Brake_value; //刹车开度
}MC_RealTime_0x2304; //实时数据 500ms
typedef struct{
uint16_t total_miler; //总里程
uint16_t once_miler; //单次里程
uint16_t endurance_miler; //续航里程
}MC_RealTime_0x2305; //实时数据 2000ms
/******************* BMS *******************/
typedef struct{
struct{
uint16_t normal_dischg:1; //正常放电
uint16_t normal_chg:1; //正常充电
uint16_t chg_OV_prot:1; //充电过压保护
uint16_t bat_LV_prot:1; //电池低压保护
uint16_t chg_OC_prot:1; //充电过流保护
uint16_t dischg_OC_prot:1; //放电过流保护
uint16_t bat_dischg_OT_prot:1; //电池放电过热保护
uint16_t bat_dischg_LT_prot:1; //电池放电低温保护
uint16_t bat_open_circuit:1; //电池组开路
uint16_t dischg_SCP:1; //放电短路保护
uint16_t bat_chg_OT_prot:1; //电池充电过热保护
uint16_t bat_chg_UT_prot:1; //电池充电低温保护
uint16_t MOS_OT_prot:1; //线路板MOS过热保护
uint16_t temp_sensor_failure:1; //温度传感器故障(短/断路)
uint16_t chg_MOS_on:1; //充电MOS打开
uint16_t dischgg_MOS_on:1; //放电MOS打开
}failure;
uint16_t realtime_cur; //实时电流
uint16_t realtime_vol; //实时电压
uint8_t max_bat_temp; //电池最高温度
uint8_t min_bat_temp; //电池最低温度
}BMS_RealTime_status1_0x2301; //实时状态1 500ms
typedef struct{
uint8_t state_of_charge; //剩余电量SOC
uint8_t state_of_health; //电池健康度SOH
uint16_t max_dischg_cur; //允许最大放电电流
uint16_t max_chg_cur; //允许最大充电电流
uint16_t max_chg_vol; //最大充电电压
}BMS_RealTime_status2_0x2302; //实时状态2 1000ms
typedef struct{
uint16_t full_bat_capa; //电池满充容量
uint16_t remain_bat_capa; //电池剩余容量
uint16_t time_of_chg; //已充电次数
uint8_t External_signal_sta; //外部信号状态
uint8_t chg_time_remain; //充电剩余时间
}BMS_RealTime_status3_0x2303; //实时状态3 1000ms
//BMS扩展帧
typedef struct {
uint8_t main_hw_ver; // byte0: 主硬件版本 (0-99)
uint8_t sub_hw_ver; // byte1: 次硬件版本 (0-99)
uint8_t main_sw_ver; // byte2: 主软件版本 (0-99)
uint8_t sub_sw_ver; // byte3: 次软件版本 (0-99)
struct {
uint8_t boot1_main :4; // byte4低4位: BOOT1主版本 (0-15)
uint8_t boot1_sub :4; // byte4高4位: BOOT1次版本 (0-15)
} boot1;
struct {
uint8_t boot2_mai:4; // byte5低4位: BOOT2主版本 (0-15)
uint8_t boot2_sub :4; // byte5高4位: BOOT2次版本 (0-15)
} boot2;
uint8_t main_proto_ver; // byte6: 主通信协议版本 (0-99)
uint8_t sub_proto_ver; // byte7: 次通信协议版本 (0-99)
}BMS_ver_info_t; //版本信息 2000ms
typedef struct{
uint8_t product_model; // byte0: 产品型号 (0-99)
uint8_t hard_code; // byte1: 硬件厂商代码 (0-254)
uint16_t customer_code; // byte2-3: 客户代码 (大端存储)
uint16_t designer_code; // byte4-5: 设计厂家代码 (大端存储)
uint8_t reserved[2]; // byte6-7: 预留
}BMS_mf_info; //厂家信息 2000ms
typedef struct{
uint8_t year;
uint8_t month;
uint8_t day;
}BMS_product_date; //生产日期信息 2000ms
typedef struct{
uint8_t sn[4];
}BMS_sn_num; //BMS序列号 2000ms
typedef enum {
sanyuan = 0x00, //三元
LiFePO = 0x01, //磷酸铁锂
LMO, //锰酸锂
LFMP, //磷酸锰铁锂
sealed, //铅酸
NiH, //镍氢
LiCoO, //钴酸锂
LiTiO, //钛酸锂
Na, //钠离子
solid, //固态
Multic_dop //多元掺杂
}battery_type;
typedef struct{
uint16_t vol; //额定电压
uint8_t cap; //额定容量
uint8_t series_num; //串联数量
uint8_t parallel_num; //并联数量
battery_type bat_type; //电池类型
}BMS_Nominal_para; //额定参数 2000ms
typedef enum {
Not = 0x00, //无该包
Free, //空闲
Discharge, //放电
Charge, //充电
Feedback, //回馈
Off_line, //离线
Unincorporated, //未并入
Heat //加热
}work_state;
typedef enum {
Nott = 0x00, //无该包
One_chg, //单包充电
One_dischg, //单包放电
Two_chg, //双包充电
Two_dischg, //双包放电
three_chg, //三包充电
three_dischg, //三包放电
four_chg, //四包充电
four_dischg, //四包放电
}parallel_sta;//并机状态
typedef struct{
work_state sta0;
work_state sta1;
work_state sta2;
work_state sta3;
work_state sta4;
work_state sta5;
work_state sta6;
work_state sta7;
parallel_sta pll_sta; //并机状态
}BMS_work_state;//工作状态汇总 100ms
typedef struct{
uint16_t total_vol; //总电压
int16_t total_cur; //总电流
uint16_t total_soc; //总电池电量剩余充满时间
uint16_t average_soc; //平均总SOC
}BMS_vol_cur; //电压电流汇总 100ms
typedef struct{
int16_t Instant_DC; //总电池允许最大瞬时放电电流
int16_t ststain_DC; //总电池允许最大持续放电电流
int16_t ststain_chg;
//总电池允许最大持续充电电流
int16_t Feedback_cur;
//总电池允许最大允许回馈电流
}BMS_SOP; //SOP汇总 100ms
typedef enum {
mos_off = 0x00,
mos_on = 0x01,
rsv = 0x02,
Void = 0x03
}mos_sta;
typedef enum {
INvalid = 0x00,
valid = 0x01
}effecf; //有效、无效
typedef struct{
uint16_t vol;
int16_t cur;
struct{
mos_sta DMOS:2;
mos_sta CMOS:2;
mos_sta pre_dmos:2; //预放电MOS
mos_sta heat_mos:2; //加热MOS
}mos_state;
uint8_t rsv;
struct{
effecf ACC_signal:1; //ACC信号
effecf ON_signal:1; //ON信号
effecf CRG_signal:1; //CRG信号
}sign_info;
}BMS_VOL_MOS; //电池包电压及MOS信息 100ms
typedef struct{
uint16_t dischg; //最大允许放电
uint16_t chg; //最大允许充电
}BMS_instant_cur; //瞬时电流 100ms
typedef struct{
uint16_t plus; //正端绝缘电阻
uint16_t minus; //负端绝缘电阻
}BMS_insulate_test; //绝缘检测 500ms
typedef struct{
uint16_t SOC; //电量百分比
uint16_t SOH; //健康系数
uint16_t cycle; //循环次数
}BMS_SOX_info; //SOX估算信息 500ms
typedef struct{
uint16_t full_cap; //满充容量
uint16_t surplus_cap; //剩余容量
uint16_t SOE; //剩余能量
uint16_t full_tome; //剩余充满时间
}BMS_surplus_capa; //剩余容量信息 500ms
typedef struct{
uint16_t min;
uint16_t max;
}BMS_vol_vaule; //单体电压 500ms
typedef struct{
uint16_t chg; //充电
uint16_t Feedback; //回馈
uint16_t dischg; //放电
}BMS_cur_vaule; //最大电流 500ms
typedef struct{
uint8_t high; //最高电芯
uint8_t low; //最低电芯
uint8_t mos_high; //MOS最高
uint8_t envir; //环境
}BMS_temp_vaule; //温度值 500ms
#pragma pack(push, 1)
typedef struct {
struct {
// Byte 0
uint8_t single_OV :2; // B0.0-1 单体过压
uint8_t single_UV :2; // B0.2-3 单体欠压
uint8_t total_OV :2; // B0.4-5 总压过压
uint8_t total_UV :2; // B0.6-7 总压欠压
}b0;
struct {
// Byte 1
uint8_t DC_OT : 2; // B1.0-1,放电高温
uint8_t DC_LT : 2; // B1.2-3,放电低温
uint8_t C_OT : 2; // B1.4-5,充电高温
uint8_t C_LT : 2; // B1.6-7,充电低温
}b1;
struct {
// Byte 2
uint8_t temp_diff:2; // B2.0-1,温差大
uint8_t COC:2; // B2.2-3,充电过流
uint8_t feedback_OC:2; // B2.4-5,回馈过流
uint8_t DOC:2; // B2.6-7,放电过流
}b2;
struct {
// Byte 3
uint8_t D_inst_OC : 2; // B3.0-1,放电瞬时过流
uint8_t insulation_low : 2; // B3.2-3,绝缘过低
uint8_t soc_low : 2; // B3.4-5
uint8_t bat_id_conflict: 2; // B3.6-7,电池id冲突
}b3;
// Byte 4 (单比特标志位)
struct {
uint8_t AFE_comm_fault : 1; // B4.0,AFE通讯异常
uint8_t vol_collect_f:1; // B4.1,电池采集异常
uint8_t temp_collect_f:1; // B4.2,温度采集异常
uint8_t balance_OT:1; // B4.3,均衡过温
uint8_t MOS_OT:1; // B4.4,MOS过温
uint8_t preC_R_HT:1; // B4.5,预充电阻过温
uint8_t pre_timeout :1; // B4.6,预充超时
uint8_t pre_OC:1; // B4.7,预充过流
}b4;
// Byte 5 (单比特标志位)
struct {
uint8_t AFE_OV :1; // B5.0
uint8_t AFE_UV :1; // B5.1
uint8_t AFE_DOC:1; // B5.2
uint8_t AFE_COC :1; // B5.3
uint8_t AFE_SC:1; // B5.4,AFE短路
uint8_t AFE_COT :1; // B5.5
uint8_t AFE_CLT :1; // B5.6
uint8_t AFE_DOT:1; // B5.7
}b5;
// Byte 6 (单比特标志位)
struct {
uint8_t AFE_DLT:1; // B6.0
uint8_t float_chg:1; // B6.1,浮充
uint8_t OV_stop_chg:1; // B6.2,OV禁充
uint8_t precast_mos:1; // B6.3,预放MOS
uint8_t DMOS_stick:1; // B6.4,放电MOS粘连
uint8_t CMOS_stick :1; // B6.5,充电MOS粘连
uint8_t precast_mos_f:1;// B6.6,预放MOS驱动异常
uint8_t DMOS_drv_f:1; // B6.7,放电MOS驱动异常
}b6;
// Byte 7 (单比特标志位)
struct {
uint8_t CMOS_drv_f:1; // B7.0,充电MOS驱动异常
uint8_t EOL_state:1; // B7.1
uint8_t over_OV:1; // B7.2,电压严重过压
uint8_t rsv1:1; // B7.3
uint8_t rsv2:1; // B7.4
uint8_t rsv3:1; // B7.5
uint8_t C_P:1; // B7.6,充电保护
uint8_t DC_P:1; // B7.7,放电保护
}b7;
}BMS_fault_info; //故障信息 500ms
#pragma pack(pop)
typedef struct {
struct
{
uint8_t index : 5; //报文编号 (B0.0-B0.4)
uint8_t num : 3; //电压个数 (B0.5-B0.7)
}b0; // 整个B0字节
uint8_t vol[7];
}BMS_vol_info; //电池电压信息 500ms
typedef struct {
struct
{
uint8_t index : 5; //报文编号 (B0.0-B0.4)
uint8_t num : 3; // 温度个数 (B0.5-B0.7)
}b0; // 整个B0字节
int8_t temp[7]; // 温度值数组 (B1-B7)
} BMS_temp_info; //电池温度信息 500ms
typedef struct{
uint8_t one_year; //电池实时时间-年
uint8_t month;
uint8_t day;
uint8_t hour;
uint8_t min;
uint8_t sec;
uint16_t rsv;
}BMS_time_info; //实时时间信息 500ms
typedef struct{
uint8_t index;
uint8_t SN_num[7];
}BMS_PACK_SN; //电池包Pack SN码 100ms
/******************* VCU *******************/
typedef struct{
struct{
uint32_t ACC_enable:1; //0:ACC OFF1:ACC ON
uint32_t garrison:1; //0:撤防1:设防
uint32_t network_connect:1; //1:网络连接成功
uint32_t GPS:1; //1:北斗定位成功
uint32_t ble_connect:1; //1:蓝牙已链接
uint32_t temple:1; //1:边撑在位状态
uint32_t Cushion_detecte:1; //1:坐垫/重力在位状态
uint32_t PKE:1; //1:PKE感应状态
uint32_t rotor_heat:1; //1:转把加热
uint32_t cushion_heat:1; //1:坐垫加热
uint32_t faucet_lock:1; //1:龙头锁状态
uint32_t rsv1:5;
uint32_t shake_alarm:1; //1:震动报警
uint32_t rotation_alarm:1; //1:轮动报警
uint32_t Vehicle_dump:1; //1:车辆倾倒
uint32_t rsv2:13;
}state;
struct{
uint32_t SIM_card:1; //1:SIM卡故障
uint32_t abnor_network_reg:1; //1:网络注册异常
uint32_t ble_abnormal:1; //1:蓝牙异常
uint32_t gps_abnormal:1; //1:北斗定位异常
uint32_t rsv1:4;
uint32_t control_comm:1; //1:控制器通信故障
uint32_t instrument_comm:1; //1:仪表通信故障
uint32_t BMS_comm:1; //1:BMS通信故障
uint32_t ABS_comm:1; //1:ABS通信故障
uint32_t charging_comm:1; //1:充电器通信故障
uint32_t LED_comm:1; //1:灯控盒通信故障
uint32_t radar_comm:1; //1:雷达通信故障
uint32_t rsv2:17;
}fault;
}VCU_realtime_status_0x2301; //500ms
typedef struct{
uint32_t total_miler; //总里程
uint16_t once_miler; //单次里程
uint16_t endurance_miler; //续航里程
}VCU_miler_0x2302;
typedef struct{
uint8_t hour; //小时
uint8_t min; //分钟
}VCU_time_0x2303;
/******************* HIMI ******************/
typedef struct{
uint16_t speed_factor_set; //速度系数设置
}HIMI_fct_switch_set_0X2001; //功能开关设置
typedef struct{
uint32_t Total_distance; //总里程
uint16_t Single_distance; //单次里程
uint8_t mode; //0白天模式; 1夜间模式
uint8_t speed; //车速
}HIMI_realtime_status1_0X2301; //实时状态1
/******************* ABS *******************/
typedef struct{
Fun_State fun_switch1;
}ABS_fun_swit_set_0x2001; //功能开关设置
typedef struct{
Fun_State fun_switch2;
}ABS_sys_info_0x2201; //系统信息 1000ms
// 实时状态标志位结构体(内存对齐优化)
#pragma pack(push, 1)
typedef struct {
uint32_t fault_flag : 1; // bit0: ABS故障0正常/1故障
uint32_t reserved : 31; // 保留位
uint32_t work_status : 1; // bit32: ABS工作状态0待机/1运行
}ABS_RealTime_Status1_0x2301; //实时状态1 200ms
#pragma pack(pop)
/******************* 灯控盒 *******************/
typedef struct{
struct {
uint8_t system_enable : 2; // bit0-1
uint8_t reserved : 6;
} switch_status; // 灯控系统开关
color_set front_corridor:4; // 前照灯示廓灯 (bit0-3)
color_set front_LOGO:4; // 前照灯LOGO灯 (bit4-7)
color_set front_thick_wall:4; // 前照灯厚壁灯 (bit0-3)
color_set back_corridor:4; // 尾灯示廓灯 (bit4-7)
color_set back_LOGO:4; // 尾灯LOGO灯 (bit0-3)
}LED_fun_swit_set_0x2001;
/* 灯光配置结构体 */
typedef struct{
struct{
Rq_sta low_beam:4; //近光灯(bit0-3)
upper_set upper_beam:4; //远光(bit4-7)
}front_t1; //byte0 前照灯
struct{
Rq_sta left_beam:2; //前照灯左转向灯(bit0-1)
Rq_sta left_side:2; //前照灯左侧指示灯(bit2-3)
Rq_sta left_fill:2; //前照灯左侧补光灯(bit4-5)
Rq_sta right_beam:2; //前照灯右转向灯(bit6-7)
}front_t2; //byte1
struct{
Rq_sta right_side:2; //前照灯右侧指示灯(bit0-1)
Rq_sta right_fill:2; //前照灯右侧补光灯(bit2-3)
Rq_sta both_side:2; //前照灯两侧示廓灯(bit4-5)
Rq_sta LOGO_beam:2; //前照灯LOGO灯(bit6-7)
}front_t3; //byte2
struct{
Rq_sta thick_wall:2; //前照灯厚壁灯(bit0-1)
Rq_sta drive_lamp:2; //尾灯行车灯(bit2-3)
Rq_sta stop_lamp:2; //尾灯制动灯(bit4-5)
Rq_sta left_t:2; //尾灯左转(bit6-7)
}back_t1;
struct{
Rq_sta right_t:2; //尾灯右转(bit0-1)
Rq_sta corridor_t:2; //尾灯示廓灯(bit2-3)
Rq_sta logo_t:2; //尾灯LOGO灯(bit4-5)
}back_t2;
}LED_fun_cotrol_0x2101;
typedef struct{
Fun_State light_ctrl_box;//灯控盒
}LED_sys_info_t; //系统信息 1000ms
typedef struct{
struct{
uint16_t light_t:1; //灯光总开关/尾灯开关
uint16_t high_beam:1; //远光灯开关
uint16_t left_turn:1; //左转开关
uint16_t right_turn:1; //右转开关
uint16_t warn_light:1; //警示灯开关
uint16_t overtake_light:1; //超车灯开关
uint16_t rsv:10;
}switch_input;
struct{
uint16_t tail_on:1; //尾灯开启
uint16_t high_beam_on:1; //远光灯开启
uint16_t left_turn_on:1; //左转开启
uint16_t right_turn_on:1; //右转开启
uint16_t low_beam_on:1; //近光灯开启
uint16_t rsv:11;
}output_state;
}LED_realtime_status1_0x2301; //50ms
/******************* 雷达rado *******************/
typedef struct{
struct{
Fun_State radar_sys:2; //雷达系统开关
Fun_State warn_light:2; //预警灯开关
Fun_State buzzer:2; //蜂鸣器开关
Fun_State video:2; //录像开关
}switch1;
struct{
Fun_State behind_vehicle:2; //后方来车预警开关
Fun_State left_vehicle:2; //左侧方来车预警开关
Fun_State right_vehicle:2; //右侧方来车预警开关
}switch2;
}RADO_fun_switch_set_0x2001; //功能开关设置
typedef struct{
struct{
Fun_State radar_sys:2; //雷达系统开关
Fun_State warn_light:2; //预警灯开关
Fun_State buzzer:2; //蜂鸣器开关
Fun_State video:2; //录像开关
}switch1;
struct{
Fun_State behind_vehicle:2; //后方来车预警开关
Fun_State left_vehicle:2; //左侧方来车预警开关
Fun_State right_vehicle:2; //右侧方来车预警开关
}switch2;
}RADO_sys_info_0x2201; //系统信息 1000ms
typedef struct {
uint32_t faile;
struct{
uint32_t left_level_1:1; //左侧方来车一级预警
uint32_t left_level_2:1; //左侧方来车二级预警
uint32_t right_level_1:1; //右侧方来车一级预警
uint32_t right_level_2:1; //右侧方来车二级预警
uint32_t behind_level_1:1; //后方来车一级预警
uint32_t behind_level_2:1; //后方来车二级预警
}state;
}RADO_RealTime_status1_0x2301; //实时状态1 100ms
/******************* charger扩展 *******************/
typedef struct{
uint8_t main_ver; //充电流程协议主版本
uint8_t sub_ver; //充电流程协议次版本
uint32_t roll_code; //滚动码
uint16_t crc;
}charger_hs_ver_info; //充电器握手版本信息 200ms
typedef struct{
uint16_t low_vol; //最低输出电压
uint16_t high_vol; //最高输出电压
uint16_t low_cur; //最低输出电流
uint16_t high_cur; //最高输出电流
}charger_output; //充电器输出能力配置 200ms
typedef struct{
uint16_t rsv;
uint16_t vol;
uint16_t cur;
}charger_realtime_status;//充电器实时充电状态 200ms
typedef enum{
Idle = 0,
precharge = 1,
charging = 2,
fail = 3,
full_of = 4
}chg_sta;
typedef struct{
chg_sta state; //充电器状态
chg_sta comm_fail; //通讯故障
chg_sta chg_overtime; //充电超时
}charger_state;
/***************************************************************/
#define CAN_SIZE_MAX 100U //根据CAN的id数设置大小41
#define QUEUE_BUFF_SIZE 36U
//定义can包
typedef struct
{
uint32_t can_id;
uint8_t data[8];
}can_data_t;
/****************************** 外部申明函数 ***********************************/
#endif

@ -0,0 +1,124 @@
#include "jw_sys_timer.h"
#include "SWM221.h"
#include "jw_bsp_init.h"
// 全局变量用于记录系统运行的tick数毫秒级
uint32_t m_getTick;
extern void Timer_TASK_50msFunc(void);
extern void Timer_TASK_100msFunc(void);
extern void Timer_TASK_200msFunc(void);
extern void Timer_TASK_500msFunc(void);
extern void Timer_TASK_1000msFunc(void);
extern void Timer_TASK_2000msFunc(void);
/* 定义任务函数指针类型,指向无参数无返回值的函数 */
typedef void (*TaskFunType)(void);
/* 任务函数指针数组,存储所有任务函数的地址 */
static TaskFunType TaskFunPtr[TASKFUNNUMBER] =
{
&Timer_TASK_50msFunc, /* 索引1: 50ms任务 */
&Timer_TASK_100msFunc, /* 索引2: 100ms任务 */
&Timer_TASK_200msFunc, /* 索引3: 200ms任务 */
&Timer_TASK_500msFunc, /* 索引4: 500ms任务 */
&Timer_TASK_1000msFunc, /* 索引5: 1000ms任务 */
&Timer_TASK_2000msFunc /* 索引6: 2000ms任务 */
};
/**
* @brief 1ms
* @note 1ms
*/
void Timer_Task_1ms(void)
{
// 静态变量,记录从系统启动开始的毫秒数
static uint16_t Counterms = 0;
uint8_t i = 0;
// 更新全局tick计数器处理32位溢出情况
// 当达到32位最大值时归零否则自增
if (m_getTick == 0xFFFFFFFF)
{
m_getTick = 0;
}
else
{
m_getTick++;
}
// 检查计数器是否超过最大值
if(Counterms > TASKMAXCOUNTER)
{
Counterms = 0; // 超过最大值则归零
}
else
{
Counterms++; // 否则自增
// 遍历所有任务,检查是否需要触发
for(i = 0; i < TASKFUNNUMBER; i++)
{
// 检查当前计数器值是否符合任务的触发条件
if((Counterms % TimeArr[i].Period) == TimeArr[i].Remainder)
{
TaskFlag[i] = TRUE; // 设置任务触发标志
}
}
}
}
/* 定时任务主调度函数 */
void Timer_MainFun(void)
{
uint8_t i = 0;
/* 遍历所有任务 */
for(i = 0; i < TASKFUNNUMBER; i++)
{
/* 检查任务标志是否为TRUE需要执行 */
if(TaskFlag[i] == TRUE)
{
/* 检查任务函数指针是否有效 */
if(TaskFunPtr[i] != NULL)
{
/* 执行对应的任务函数 */
TaskFunPtr[i]();
/* 任务执行完成后,清除任务标志 */
TaskFlag[i] = FALSE;
}
}
}
}
void Timer_TASK_50msFunc(void)
{
}
void Timer_TASK_100msFunc(void)
{
}
void Timer_TASK_200msFunc(void)
{
}
void Timer_TASK_500msFunc(void)
{
}
void Timer_TASK_1000msFunc(void)
{
// LOG("tiimer 1000ms...\r\n");
}
void Timer_TASK_2000msFunc(void)
{
}

@ -0,0 +1,52 @@
#ifndef __JW_SYS_TIMER_H__
#define __JW_SYS_TIMER_H__
#include "SWM221.h"
/* 定义布尔值常量 */
#define TRUE 1
#define FALSE 0
/* 定义任务函数数量为6个 */
#define TASKFUNNUMBER 6
// 定义最大计数器值为6000无符号整型
#define TASKMAXCOUNTER (6000U)
typedef struct
{
uint16_t Period; // 任务执行周期ms
uint16_t Remainder; // 触发任务的计数器余数值
}TaskTimeType;
/* 任务标志数组,用于标记各任务是否需要执行 */
/* 初始化为全0FALSE表示初始状态下所有任务都不需要执行 */
static uint8_t TaskFlag[TASKFUNNUMBER] = {0, 0, 0, 0, 0,0};
// 每个任务配置了周期和余数,用于决定何时触发任务
static TaskTimeType TimeArr[TASKFUNNUMBER] =
{
{50,49}, // 任务1每50ms执行当Counterms%50==49时触发
{100, 97}, // 任务2每100ms执行当Counterms%100==97时触发
{200, 197}, // 任务3每200ms执行当Counterms%200==197时触发
{500, 497}, // 任务4每500ms执行当Counterms%500==497时触发
{1000, 999},// 任务5每1000ms执行当Counterms%1000==999时触发
{2000, 1999}// 任务6每2000ms执行当Counterms%2000==1999时触发
};
void Timer_MainFun(void);
#endif

@ -0,0 +1,368 @@
#include "SWM221.h"
#include "CircleBuffer.h"
#include "jw_can.h"
#include "jw_bsp_init.h"
#include "jw_sys_timer.h"
/* 测试条件SWM221 <==CAN_RX/TX==> CAN 收发器(如 TJA1050<==CAN_H/L==> CAN 分析仪
*
* 1 CAN CAN ACK CAN->TXERR 0 128
* 2 SWM221 CAN CAN->TXERR 255 Bus OffCAN->CR.RST 1CAN
* 3ISR Bus Off CAN_Open(CAN0) 使 CAN 退CAN->TXERR 0CAN
*/
static can_data_t can_buff[CAN_SIZE_MAX] = {
/* MCU ID值, cnt-->11 */
{.can_id = 0x101,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //参数设置
{.can_id = 0x102,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //功能开关设置
{.can_id = 0x103,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //功能控制
{.can_id = 0x104,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //信息获取
{.can_id = 0x500,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //版本信息
{.can_id = 0x501,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //序列号
{.can_id = 0x502,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //系统信息1 /*周期1000ms*/
{.can_id = 0x503,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //系统信息2 /*周期1000ms*/
{.can_id = 0x600,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //故障状态 /*周期500ms*/
{.can_id = 0x601,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //运行信息1 /*周期200ms*/
{.can_id = 0x602,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //功率输出状态 /*周期500ms*/
/* BMS ID值, cnt-->21 */
{.can_id = 0x1000FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //版本信息 /*周期2000ms*/
{.can_id = 0x1001FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //厂商信息 /*周期2000ms*/
{.can_id = 0x1002FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包生产日期 /*周期2000ms*/
{.can_id = 0x1003FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包BMS序列号 /*周期2000ms*/
{.can_id = 0x1004FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包额定参数 /*周期2000ms*/
{.can_id = 0x1010FFA7,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包工作状态--汇总信息 /*周期100ms*/
{.can_id = 0x1011FFA7,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包电压电流--汇总信息 /*周期100ms*/
{.can_id = 0x1012FFA7,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包SOP--汇总信息 /*周期100ms*/
{.can_id = 0x1020FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包电压及MOS信息 /*周期100ms*/
{.can_id = 0x1021FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包瞬时充放电电流 /*周期100ms*/
{.can_id = 0x1022FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包绝缘检测信息 /*周期500ms*/
{.can_id = 0x1023FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包SOX估算信息 /*周期500ms*/
{.can_id = 0x1024FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包剩余容量信息 /*周期500ms*/
{.can_id = 0x1025FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包单体电压信息 /*周期500ms*/
{.can_id = 0x1026FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包持续电流信息 /*周期500ms*/
{.can_id = 0x1027FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包温度信息 /*周期500ms*/
{.can_id = 0x1028FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包故障信息 /*周期500ms*/
{.can_id = 0x1030FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包单体电压信息 /*周期500ms*/
{.can_id = 0x1031FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包温度信息 /*周期500ms*/
{.can_id = 0x1032FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包实时时间信息 /*周期500ms*/
{.can_id = 0x1033FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包Pack SN码 /*周期100ms*/
/* VCU ID值, cnt-->4 */
{.can_id = 0x630,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //系统状态 /*周期200ms*/
{.can_id = 0x631,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //辅助功能状态 /*周期500ms*/
{.can_id = 0x632,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //防盗 /*周期500ms*/
{.can_id = 0x130,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //控制指令
/* HIMI ID值, cnt-->2 */
{.can_id = 0x650,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //状态信息 /*周期500ms*/
{.can_id = 0x150,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //参数设置
/* TBOX ID值, cnt-->1 */
{.can_id = 0x640,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //状态信息 /*周期500ms*/
/* LED ID值, cnt-->2 */
{.can_id = 0x200,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //beam_control /*周期100ms*/
{.can_id = 0x201,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} } //beam_set /*周期100ms*/
};
volatile bool msg_rcvd = false;
CircleBuffer_t CirBuf;
CircleBuffer_t TX_CirBuf;
void SerialInit(void);
void UART_send(void);
void CAN_send_id(int id,uint8_t *pdat);
//#define LOG printf
static uint8_t m_buf[1024];
/**
* @brief CANID
* @param id : CANID
* @retval NULL
*/
static __inline uint8_t *find_can_db(int id)
{
int i = 0, idx = 0; // 循环计数器i匹配索引idx
can_data_t *p_arry = can_buff; // 获取CAN数据库首地址
// 遍历整个CAN数据库
for (; i < CAN_SIZE_MAX; i++)
{
// 比对当前项的CAN ID
if (p_arry[i].can_id == id) {
idx = i; // 记录匹配项的索引
break; // 找到后立即退出循环
}
}
// 返回结果如果遍历完未找到返回NULL否则返回对应数据的地址
return (i == CAN_SIZE_MAX) ? NULL : p_arry[idx].data;
}
int main(void)
{
int len=0,i;
uint8_t *pcan_dat = NULL; // 定义指向CAN数据的指针
can_data_t can_dat = {0}; // 定义CAN数据结构体并初始化为0
bsp_init();
segger_rtt_init(" [JW LOG]:---->>>> SG01 app start ! <<<----\r\n"); // 初始化SEGGER RTT调试日志
while(1) // 嵌入式系统典型的主循环Super Loop结构
{
// //原CAN发送代码已注释保留供调试参考
// uint8_t tx_data[8] = {1, 2, 3, 4, 5, 6, 7, 8},i;
// CAN_Transmit(CAN0, CAN_FRAME_STD, 0x104, tx_data, 8, 1);
// while(CAN_TXComplete(CAN0) == 0) __NOP(); // 阻塞等待CAN发送完成
// printf("\r\nCAN->TXERR: %d\r\n", CAN0->TXERR); // 调试用打印CAN发送错误计数
// for(i=0;i<9;i++)
// {
// UART_WriteByte(UART0, tx_data[i]); // 写入UART发送寄存器
// LOG(">>>>>>send data :%d <<<<<<\r\n",tx_data[i]);
// }
/* 核心逻辑UART消息处理与转发 */
if(msg_rcvd) // 检测UART接收完成标志由UART中断置位
{
msg_rcvd = false; // 立即清除标志,避免重复处理
// 检查环形缓冲区数据有效性
if(!CirBuf_Empty(&CirBuf))
{
len = CirBuf_Count(&CirBuf); // 获取缓冲区数据长度
// 数据长度校验12~1023字节为合法范围
if( (len < 12) || (len > (1024-1)) )
{
CirBuf_Clear(&CirBuf); // 非法数据清空缓冲区
LOG(">>>>>>CAN data len:%d ERR! <<<<<<\r\n",len); // 记录错误日志
}
else
{
/*错:此处串口发送的数据不对,需要修改*/
// 有效数据处理流程:
CirBuf_Read(&CirBuf, (uint8_t *)m_buf, len); // 读取数据到m_buf
CAN_send_id((int)m_buf, &m_buf[4]); // 解析并发送CAN帧假设前4字节为ID后续为数据
}
}
// 启用UART发送中断准备后续数据发送
UART_INTEn(UART0, UART_IT_TX_THR);
}
// /*--- CAN数据处理部分 ---*/
// for(i = 0; i < CAN_SIZE_MAX; i++) // 遍历CAN数据库
// {
// /*--- 常规CAN数据处理 ---*/
// pcan_dat = find_can_db(can_dat.can_id); // 在CAN数据库查找对应ID
// if( pcan_dat == NULL )
// {
// //LOG(">>>>>>>>>>>>> Not Find CAN id %08X <<<<<<<<<<<<<\n",can_dat.can_id);
// break;
// }
// memcpy(pcan_dat,can_dat.data,sizeof(can_dat.data)); // 拷贝数据到数据库
// }
// 主动触发UART发送非中断驱动部分
UART_send();
/*--- 定时任务处理 ---*/
//Timer_MainFun();
// 延时控制(基于系统时钟的精确空操作延时)
for(int i = 0; i < SystemCoreClock / 16; i++) __NOP(); // 约62.5ms延时SystemCoreClock=8MHz
}
}
void CAN0_Handler(void)
{
uint32_t can_if = CAN_INTStat(CAN0);
uint32_t id_p = 0; //id位置互换
// 处理接收数据可用中断
if(can_if & CAN_IF_RXDA_Msk)
{
CAN_RXMessage msg;
CAN_Receive(CAN0, &msg);
if(msg.size > 0)
{
LOG_ORG(" Receive %s: %08X", msg.format == CAN_FRAME_STD ? "STD" : "EXT", msg.id);
for(int i = 0; i < msg.size; i++)
LOG_ORG(" %02X", msg.data[i]);
LOG("\n");
if(msg.format == CAN_FRAME_STD)
{
id_p = (msg.id <<24)&0xff000000;
id_p |= (msg.id <<8)&0x00ff0000;
CirBuf_Write(&TX_CirBuf, (uint8_t *)&id_p, 4);
CirBuf_Write(&TX_CirBuf, (uint8_t *)msg.data, 8);
}
else
{
id_p = (msg.id <<24)&0xff000000;
id_p |= (msg.id <<8)&0x00ff0000;
id_p |= (msg.id >>24)&0x000000ff;
id_p |= (msg.id >>8)&0x0000ff00;
CirBuf_Write(&TX_CirBuf, (uint8_t *)&id_p, 4);
CirBuf_Write(&TX_CirBuf, (uint8_t *)msg.data, 8);
}
}
else if(msg.remote == 1) //远程帧
{
LOG_ORG(" Receive %s Remote Request\r\n", msg.format == CAN_FRAME_STD ? "STD" : "EXT");
}
}
// 处理接收溢出中断
if(can_if & CAN_IF_RXOV_Msk)
{
LOG_ORG(" CAN RX Overflow\r\n");
// 关闭CAN0模块以清除溢出状态
CAN_Close(CAN0);
//延时确保CAN完全关闭
for(int i = 0; i < CyclesPerUs; i++) __NOP();
// 重新打开CAN0模块以恢复通信
CAN_Open(CAN0);
}
// 处理错误警告中断
if(can_if & CAN_IF_ERRWARN_Msk)
{
// 检查是否发生总线关闭错误
if(CAN0->SR & CAN_SR_BUSOFF_Msk)
{
LOG(" CAN Bus Off\r\n");
LOG_ORG(" CAN->CR.RST = %d\r\n", CAN0->CR & CAN_CR_RST_Msk ? 1 : 0);
// 尝试恢复总线连接
CAN_Open(CAN0); //Bus Off recovery
}
else if(CAN0->SR & CAN_SR_ERRWARN_Msk)
{
LOG(" CAN Error Warning\r\n");
}
}
// 处理错误被动中断
if(can_if & CAN_IF_ERRPASS_Msk)
{
LOG(" CAN Error Passive\r\n");
}
}
void CAN_send_id(int id,uint8_t *pdat)
{
int can_id = id;
uint8_t data[8] = {0};
memcpy(data,pdat,8);
CAN_Transmit(CAN0, CAN_FRAME_STD, can_id, data, 8, 1);
while(CAN_TXComplete(CAN0) == 0) __NOP();
if( CAN0->TXERR )
{
LOG(">>>>>>>>>>>>>>>>>>CAN Error CAN->TXERR: %d<<<<<<<<<<<<<<<<<<<<<\r\n", CAN0->TXERR);
}
}
/**
* @brief UART0
* UART0
*/
void UART0_Handler(void)
{
uint32_t chr; // 临时存储读取/发送的字符
/* 接收中断处理RX FIFO阈值中断或接收超时中断*/
if(UART_INTStat(UART0, UART_IT_RX_THR | UART_IT_RX_TOUT))
{
// 循环读取RX FIFO直到为空
while(UART_IsRXFIFOEmpty(UART0) == 0)
{
// 成功读取字节时写入环形缓冲区
if(UART_ReadByte(UART0, &chr) == 0)
{
CirBuf_Write(&CirBuf, (uint8_t *)&chr, 1); // 写入接收缓冲区
LOG(" uart RX... \r");
}
}
/* 特殊处理接收超时中断(数据流间隔触发)*/
if(UART_INTStat(UART0, UART_IT_RX_TOUT))
{
UART_INTClr(UART0, UART_IT_RX_TOUT); // 清除中断标志
msg_rcvd = true; // 设置消息接收完成标志(可能用于主程序轮询)
LOG(" uart RX TOUT... \r");
}
}
/* 发送中断处理TX FIFO阈值中断*/
if(UART_INTStat(UART0, UART_IT_TX_THR))
{
// 当TX FIFO未满时持续发送数据
while(!UART_IsTXFIFOFull(UART0))
{
// 如果发送缓冲区有数据则取出并发送
if(!CirBuf_Empty(&TX_CirBuf))
{
CirBuf_Read(&TX_CirBuf, (uint8_t *)&chr, 1); // 从发送缓冲区读取
UART_WriteByte(UART0, chr); // 写入UART发送寄存器
LOG(" uart TX... \r");
}
else
{
// 发送缓冲区为空时禁用TX中断避免空转
UART_INTDis(UART0, UART_IT_TX_THR);
LOG(" uart ERR... \r");
break; // 退出发送循环
}
}
}
}
void UART_send(void)
{
uint32_t chr = 0;
// if(UART_INTStat(UART1, UART_IT_TX_THR))//not chk TX_THR
{
while(!UART_IsTXFIFOFull(UART0))
{
if(!CirBuf_Empty(&TX_CirBuf))
{
CirBuf_Read(&TX_CirBuf, (uint8_t *)&chr, 1);
UART_WriteByte(UART0, chr);
while(UART_IsTXBusy(UART0)); //发送空闲跳出
// while(UART_IsTXBusy(UART1))__NOP();
// LOG("[ UART_send ] TX ->: %02X\n", chr&0xFF);
//LOG("handle TX msg_rcvd->: %d cnt:%d \r\n", msg_rcvd,CirBuf_Count(&CirBuf));
}
else
{
UART_INTDis(UART0, UART_IT_TX_THR);
//LOG("~~~~~~~~Cycle TX buffer Empty~~~~~~~\n");
break;
}
}
}
}
/*********************************************************************************************
* : fputc()
* : printf()使
* : int ch
* FILE *f
* :
* :
**********************************************************************************************/
int fputc(int ch, FILE *f)
{
#if 0
UART_WriteByte(UART0, ch);
while(UART_IsTXBusy(UART0));
#endif
return ch;
}

@ -0,0 +1,17 @@
howto:
JW invok
//#include "JW_RTT.h"
//segger_rtt_init("JW_RTT DBG start !");
//print_log("print a log\n");
for orignal invok
//#include "SEGGER_RTT.h"
//SEGGER_RTT_Init();
//SEGGER_RTT_printf(0, "Hi, World!\r\n");

@ -0,0 +1,50 @@
/* SEGGER RTT 相关头文件 */
#include <stdlib.h>
#include <stdarg.h>
#include "SEGGER_RTT.h"
#include "SEGGER_RTT_Conf.h"
#include "JW_RTT.h"
#define BUFFER_INDEX 0 // 默认使用RTT缓冲区索引0
extern int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList);
/**
* @brief
* @param sFormat:
* @param ...:
* @retval
*/
void print_log(const char * sFormat, ...)
{
va_list ParamList; // 定义可变参数列表
va_start(ParamList, sFormat); // 初始化可变参数
SEGGER_RTT_vprintf(BUFFER_INDEX, sFormat, &ParamList); // 调用RTT打印函数
va_end(ParamList); // 结束可变参数
}
/**
* @brief SEGGER RTT
* @param string:
* @retval
*/
void segger_rtt_init(char * string)
{
SEGGER_RTT_Init(); // 初始化RTT模块
print_log(string); // 打印初始化信息
}
/**
* @brief (JW)
* @param sFormat:
* @param ...:
* @retval
*/
void jw_rtt_print_log(const char * sFormat, ...)
{
va_list ParamList;
print_log("[JW_LOG]: --------->"); // 打印固定前缀
va_start(ParamList, sFormat); // 初始化可变参数
SEGGER_RTT_vprintf(BUFFER_INDEX, sFormat, &ParamList); // 打印实际日志内容
va_end(ParamList); // 结束可变参数
}

@ -0,0 +1,10 @@
#ifndef __JW_RTT_H__
#define __JW_RTT_H__
#define jw_log(format,...) print_log("[JW_LOG]: ---->");print_log(format, ##__VA_ARGS__)
#define jw_dbg(format,...) print_log("[JW_DBG]: ---->");print_log(format, ##__VA_ARGS__)
void print_log(const char * sFormat, ...);
void segger_rtt_init(char * str);
void jw_rtt_print_log(const char * sFormat, ...);
#endif //JW_RTT_H

File diff suppressed because it is too large Load Diff

@ -0,0 +1,227 @@
/*********************************************************************
* SEGGER MICROCONTROLLER GmbH & Co. KG *
* Solutions for real time microcontroller applications *
**********************************************************************
* *
* (c) 2014 - 2015 SEGGER Microcontroller GmbH & Co. KG *
* *
* www.segger.com Support: support@segger.com *
* *
**********************************************************************
* *
* SEGGER RTT * Real Time Transfer for embedded targets *
* *
**********************************************************************
* *
* All rights reserved. *
* *
* * This software may in its unmodified form be freely redistributed *
* in source form. *
* * The source code may be modified, provided the source code *
* retains the above copyright notice, this list of conditions and *
* the following disclaimer. *
* * Modified versions of this software in source or linkable form *
* may not be distributed without prior consent of SEGGER. *
* * This software may only be used for communication with SEGGER *
* J-Link debug probes. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
* DAMAGE. *
* *
**********************************************************************
* *
* RTT version: 5.02k *
* *
**********************************************************************
---------------------------END-OF-HEADER------------------------------
File : SEGGER_RTT.h
Purpose : Implementation of SEGGER real-time transfer which allows
real-time communication on targets which support debugger
memory accesses while the CPU is running.
----------------------------------------------------------------------
*/
#ifndef SEGGER_RTT_H
#define SEGGER_RTT_H
#include "SEGGER_RTT_Conf.h"
/*********************************************************************
*
* Defines, fixed
*
**********************************************************************
*/
/*********************************************************************
*
* Types
*
**********************************************************************
*/
//
// Description for a circular buffer (also called "ring buffer")
// which is used as up-buffer (T->H)
//
typedef struct {
const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4"
char* pBuffer; // Pointer to start of buffer
unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty.
unsigned WrOff; // Position of next item to be written by either target.
volatile unsigned RdOff; // Position of next item to be read by host. Must be volatile since it may be modified by host.
unsigned Flags; // Contains configuration flags
} SEGGER_RTT_BUFFER_UP;
//
// Description for a circular buffer (also called "ring buffer")
// which is used as down-buffer (H->T)
//
typedef struct {
const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4"
char* pBuffer; // Pointer to start of buffer
unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty.
volatile unsigned WrOff; // Position of next item to be written by host. Must be volatile since it may be modified by host.
unsigned RdOff; // Position of next item to be read by target (down-buffer).
unsigned Flags; // Contains configuration flags
} SEGGER_RTT_BUFFER_DOWN;
//
// RTT control block which describes the number of buffers available
// as well as the configuration for each buffer
//
//
typedef struct {
char acID[16]; // Initialized to "SEGGER RTT"
int MaxNumUpBuffers; // Initialized to SEGGER_RTT_MAX_NUM_UP_BUFFERS (type. 2)
int MaxNumDownBuffers; // Initialized to SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (type. 2)
SEGGER_RTT_BUFFER_UP aUp[SEGGER_RTT_MAX_NUM_UP_BUFFERS]; // Up buffers, transferring information up from target via debug probe to host
SEGGER_RTT_BUFFER_DOWN aDown[SEGGER_RTT_MAX_NUM_DOWN_BUFFERS]; // Down buffers, transferring information down from host via debug probe to target
} SEGGER_RTT_CB;
/*********************************************************************
*
* Global data
*
**********************************************************************
*/
extern SEGGER_RTT_CB _SEGGER_RTT;
/*********************************************************************
*
* RTT API functions
*
**********************************************************************
*/
int SEGGER_RTT_AllocDownBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags);
int SEGGER_RTT_AllocUpBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags);
int SEGGER_RTT_ConfigUpBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags);
int SEGGER_RTT_ConfigDownBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags);
int SEGGER_RTT_GetKey (void);
unsigned SEGGER_RTT_HasData (unsigned BufferIndex);
int SEGGER_RTT_HasKey (void);
void SEGGER_RTT_Init (void);
unsigned SEGGER_RTT_Read (unsigned BufferIndex, void* pBuffer, unsigned BufferSize);
unsigned SEGGER_RTT_ReadNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize);
int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName);
int SEGGER_RTT_SetNameUpBuffer (unsigned BufferIndex, const char* sName);
int SEGGER_RTT_WaitKey (void);
unsigned SEGGER_RTT_Write (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
unsigned SEGGER_RTT_WriteNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
unsigned SEGGER_RTT_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes);
unsigned SEGGER_RTT_WriteString (unsigned BufferIndex, const char* s);
//
// Function macro for performance optimization
//
#define SEGGER_RTT_HASDATA(n) (_SEGGER_RTT.aDown[n].WrOff - _SEGGER_RTT.aDown[n].RdOff)
/*********************************************************************
*
* RTT "Terminal" API functions
*
**********************************************************************
*/
int SEGGER_RTT_SetTerminal (char TerminalId);
int SEGGER_RTT_TerminalOut (char TerminalId, const char* s);
/*********************************************************************
*
* RTT printf functions (require SEGGER_RTT_printf.c)
*
**********************************************************************
*/
int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...);
/*********************************************************************
*
* Defines
*
**********************************************************************
*/
//
// Operating modes. Define behavior if buffer is full (not enough space for entire message)
//
#define SEGGER_RTT_MODE_NO_BLOCK_SKIP (0U) // Skip. Do not block, output nothing. (Default)
#define SEGGER_RTT_MODE_NO_BLOCK_TRIM (1U) // Trim: Do not block, output as much as fits.
#define SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL (2U) // Block: Wait until there is space in the buffer.
#define SEGGER_RTT_MODE_MASK (3U)
//
// Control sequences, based on ANSI.
// Can be used to control color, and clear the screen
//
#define RTT_CTRL_RESET "\e[0m" // Reset to default colors
#define RTT_CTRL_CLEAR "\e[2J" // Clear screen, reposition cursor to top left
#define RTT_CTRL_TEXT_BLACK "\e[2;30m"
#define RTT_CTRL_TEXT_RED "\e[2;31m"
#define RTT_CTRL_TEXT_GREEN "\e[2;32m"
#define RTT_CTRL_TEXT_YELLOW "\e[2;33m"
#define RTT_CTRL_TEXT_BLUE "\e[2;34m"
#define RTT_CTRL_TEXT_MAGENTA "\e[2;35m"
#define RTT_CTRL_TEXT_CYAN "\e[2;36m"
#define RTT_CTRL_TEXT_WHITE "\e[2;37m"
#define RTT_CTRL_TEXT_BRIGHT_BLACK "\e[1;30m"
#define RTT_CTRL_TEXT_BRIGHT_RED "\e[1;31m"
#define RTT_CTRL_TEXT_BRIGHT_GREEN "\e[1;32m"
#define RTT_CTRL_TEXT_BRIGHT_YELLOW "\e[1;33m"
#define RTT_CTRL_TEXT_BRIGHT_BLUE "\e[1;34m"
#define RTT_CTRL_TEXT_BRIGHT_MAGENTA "\e[1;35m"
#define RTT_CTRL_TEXT_BRIGHT_CYAN "\e[1;36m"
#define RTT_CTRL_TEXT_BRIGHT_WHITE "\e[1;37m"
#define RTT_CTRL_BG_BLACK "\e[24;40m"
#define RTT_CTRL_BG_RED "\e[24;41m"
#define RTT_CTRL_BG_GREEN "\e[24;42m"
#define RTT_CTRL_BG_YELLOW "\e[24;43m"
#define RTT_CTRL_BG_BLUE "\e[24;44m"
#define RTT_CTRL_BG_MAGENTA "\e[24;45m"
#define RTT_CTRL_BG_CYAN "\e[24;46m"
#define RTT_CTRL_BG_WHITE "\e[24;47m"
#define RTT_CTRL_BG_BRIGHT_BLACK "\e[4;40m"
#define RTT_CTRL_BG_BRIGHT_RED "\e[4;41m"
#define RTT_CTRL_BG_BRIGHT_GREEN "\e[4;42m"
#define RTT_CTRL_BG_BRIGHT_YELLOW "\e[4;43m"
#define RTT_CTRL_BG_BRIGHT_BLUE "\e[4;44m"
#define RTT_CTRL_BG_BRIGHT_MAGENTA "\e[4;45m"
#define RTT_CTRL_BG_BRIGHT_CYAN "\e[4;46m"
#define RTT_CTRL_BG_BRIGHT_WHITE "\e[4;47m"
#endif
/*************************** End of file ****************************/

@ -0,0 +1,171 @@
/*********************************************************************
* SEGGER MICROCONTROLLER GmbH & Co. KG *
* Solutions for real time microcontroller applications *
**********************************************************************
* *
* (c) 2014 - 2015 SEGGER Microcontroller GmbH & Co. KG *
* *
* www.segger.com Support: support@segger.com *
* *
**********************************************************************
* *
* SEGGER RTT * Real Time Transfer for embedded targets *
* *
**********************************************************************
* *
* All rights reserved. *
* *
* * This software may in its unmodified form be freely redistributed *
* in source form. *
* * The source code may be modified, provided the source code *
* retains the above copyright notice, this list of conditions and *
* the following disclaimer. *
* * Modified versions of this software in source or linkable form *
* may not be distributed without prior consent of SEGGER. *
* * This software may only be used for communication with SEGGER *
* J-Link debug probes. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
* DAMAGE. *
* *
**********************************************************************
* *
* RTT version: 5.02k *
* *
**********************************************************************
----------------------------------------------------------------------
File : SEGGER_RTT_Conf.h
Purpose : Implementation of SEGGER real-time transfer (RTT) which
allows real-time communication on targets which support
debugger memory accesses while the CPU is running.
---------------------------END-OF-HEADER------------------------------
*/
#ifndef SEGGER_RTT_CONF_H
#define SEGGER_RTT_CONF_H
#ifdef __ICCARM__
#include <intrinsics.h>
#endif
/*********************************************************************
*
* Defines, configurable
*
**********************************************************************
*/
#define SEGGER_RTT_MAX_NUM_UP_BUFFERS (2) // Max. number of up-buffers (T->H) available on this target (Default: 2)
#define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (2) // Max. number of down-buffers (H->T) available on this target (Default: 2)
#define BUFFER_SIZE_UP (128) //1024--->512--->384 256 Size of the buffer for terminal output of target, up to host (Default: 1k)
#define BUFFER_SIZE_DOWN (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16)
#define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64)
#define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0)
//
// Target is not allowed to perform other RTT operations while string still has not been stored completely.
// Otherwise we would probably end up with a mixed string in the buffer.
// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here.
//
/*********************************************************************
*
* RTT lock configuration for SEGGER Embedded Studio,
* Rowley CrossStudio and GCC
*/
#if (defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)
#ifdef __ARM_ARCH_6M__
#define SEGGER_RTT_LOCK(SavedState) { \
asm volatile ("mrs %0, primask \n\t" \
"mov r1, $1 \n\t" \
"msr primask, r1 \n\t" \
: "=r" (SavedState) \
: \
: "r1" \
); \
}
#define SEGGER_RTT_UNLOCK(SavedState) { \
asm volatile ("msr primask, %0 \n\t" \
: \
: "r" (SavedState) \
: \
); \
}
#elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__))
#define SEGGER_RTT_LOCK(SavedState) { \
asm volatile ("mrs %0, basepri \n\t" \
"mov r1, $128 \n\t" \
"msr basepri, r1 \n\t" \
: "=r" (SavedState) \
: \
: "r1" \
); \
}
#define SEGGER_RTT_UNLOCK(SavedState) { \
asm volatile ("msr basepri, %0 \n\t" \
: \
: "r" (SavedState) \
: \
); \
}
#else
#define SEGGER_RTT_LOCK(SavedState) (void)(SavedState)
#define SEGGER_RTT_UNLOCK(SavedState) (void)(SavedState)
#endif
#endif
/*********************************************************************
*
* RTT lock configuration for IAR EWARM
*/
#ifdef __ICCARM__
#if (defined (__ARM7M__) && (__CORE__ == __ARM7M__))
#define SEGGER_RTT_LOCK(SavedState) { \
SavedState = __get_PRIMASK(); \
__set_PRIMASK(1); \
}
#define SEGGER_RTT_UNLOCK(SavedState) { \
__set_PRIMASK(SavedState); \
}
#elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__))
#define SEGGER_RTT_LOCK(SavedState) { \
SavedState = __get_BASEPRI(); \
__set_BASEPRI(128); \
}
#define SEGGER_RTT_UNLOCK(SavedState) { \
__set_BASEPRI(SavedState); \
}
#endif
#endif
/*********************************************************************
*
* RTT lock configuration fallback
*/
#ifndef SEGGER_RTT_LOCK
#define SEGGER_RTT_LOCK(SavedState) (void)(SavedState)
#endif
#ifndef SEGGER_RTT_UNLOCK
#define SEGGER_RTT_UNLOCK(SavedState) (void)(SavedState)
#endif
#endif
/*************************** End of file ****************************/

@ -0,0 +1,500 @@
/*********************************************************************
* SEGGER MICROCONTROLLER GmbH & Co. KG *
* Solutions for real time microcontroller applications *
**********************************************************************
* *
* (c) 2014 - 2015 SEGGER Microcontroller GmbH & Co. KG *
* *
* www.segger.com Support: support@segger.com *
* *
**********************************************************************
* *
* SEGGER RTT * Real Time Transfer for embedded targets *
* *
**********************************************************************
* *
* All rights reserved. *
* *
* * This software may in its unmodified form be freely redistributed *
* in source form. *
* * The source code may be modified, provided the source code *
* retains the above copyright notice, this list of conditions and *
* the following disclaimer. *
* * Modified versions of this software in source or linkable form *
* may not be distributed without prior consent of SEGGER. *
* * This software may only be used for communication with SEGGER *
* J-Link debug probes. *
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND *
* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, *
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE *
* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT *
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE *
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH *
* DAMAGE. *
* *
**********************************************************************
* *
* RTT version: 5.02k *
* *
**********************************************************************
---------------------------END-OF-HEADER------------------------------
File : SEGGER_RTT_printf.c
Purpose : Replacement for printf to write formatted data via RTT
----------------------------------------------------------------------
*/
#include "SEGGER_RTT.h"
#include "SEGGER_RTT_Conf.h"
/*********************************************************************
*
* Defines, configurable
*
**********************************************************************
*/
#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE
#define SEGGER_RTT_PRINTF_BUFFER_SIZE (64)
#endif
#include <stdlib.h>
#include <stdarg.h>
#define FORMAT_FLAG_LEFT_JUSTIFY (1u << 0)
#define FORMAT_FLAG_PAD_ZERO (1u << 1)
#define FORMAT_FLAG_PRINT_SIGN (1u << 2)
#define FORMAT_FLAG_ALTERNATE (1u << 3)
/*********************************************************************
*
* Types
*
**********************************************************************
*/
typedef struct {
char* pBuffer;
unsigned BufferSize;
unsigned Cnt;
int ReturnValue;
unsigned RTTBufferIndex;
} SEGGER_RTT_PRINTF_DESC;
/*********************************************************************
*
* Function prototypes
*
**********************************************************************
*/
int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList);
/*********************************************************************
*
* Static code
*
**********************************************************************
*/
/*********************************************************************
*
* _StoreChar
*/
static void _StoreChar(SEGGER_RTT_PRINTF_DESC * p, char c) {
unsigned Cnt;
Cnt = p->Cnt;
if ((Cnt + 1u) <= p->BufferSize) {
*(p->pBuffer + Cnt) = c;
p->Cnt = Cnt + 1u;
p->ReturnValue++;
}
//
// Write part of string, when the buffer is full
//
if (p->Cnt == p->BufferSize) {
if (SEGGER_RTT_Write(p->RTTBufferIndex, p->pBuffer, p->Cnt) != p->Cnt) {
p->ReturnValue = -1;
} else {
p->Cnt = 0u;
}
}
}
/*********************************************************************
*
* _PrintUnsigned
*/
static void _PrintUnsigned(SEGGER_RTT_PRINTF_DESC * pBufferDesc, unsigned v, unsigned Base, unsigned NumDigits, unsigned FieldWidth, unsigned FormatFlags) {
static const char _aV2C[16] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' };
unsigned Div;
unsigned Digit;
unsigned Number;
unsigned Width;
char c;
Number = v;
Digit = 1u;
//
// Get actual field width
//
Width = 1u;
while (Number >= Base) {
Number = (Number / Base);
Width++;
}
if (NumDigits > Width) {
Width = NumDigits;
}
//
// Print leading chars if necessary
//
if ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u) {
if (FieldWidth != 0u) {
if (((FormatFlags & FORMAT_FLAG_PAD_ZERO) == FORMAT_FLAG_PAD_ZERO) && (NumDigits == 0u)) {
c = '0';
} else {
c = ' ';
}
while ((FieldWidth != 0u) && (Width < FieldWidth)) {
FieldWidth--;
_StoreChar(pBufferDesc, c);
if (pBufferDesc->ReturnValue < 0) {
break;
}
}
}
}
if (pBufferDesc->ReturnValue >= 0) {
//
// Compute Digit.
// Loop until Digit has the value of the highest digit required.
// Example: If the output is 345 (Base 10), loop 2 times until Digit is 100.
//
while (1) {
if (NumDigits > 1u) { // User specified a min number of digits to print? => Make sure we loop at least that often, before checking anything else (> 1 check avoids problems with NumDigits being signed / unsigned)
NumDigits--;
} else {
Div = v / Digit;
if (Div < Base) { // Is our divider big enough to extract the highest digit from value? => Done
break;
}
}
Digit *= Base;
}
//
// Output digits
//
do {
Div = v / Digit;
v -= Div * Digit;
_StoreChar(pBufferDesc, _aV2C[Div]);
if (pBufferDesc->ReturnValue < 0) {
break;
}
Digit /= Base;
} while (Digit);
//
// Print trailing spaces if necessary
//
if ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == FORMAT_FLAG_LEFT_JUSTIFY) {
if (FieldWidth != 0u) {
while ((FieldWidth != 0u) && (Width < FieldWidth)) {
FieldWidth--;
_StoreChar(pBufferDesc, ' ');
if (pBufferDesc->ReturnValue < 0) {
break;
}
}
}
}
}
}
/*********************************************************************
*
* _PrintInt
*/
static void _PrintInt(SEGGER_RTT_PRINTF_DESC * pBufferDesc, int v, unsigned Base, unsigned NumDigits, unsigned FieldWidth, unsigned FormatFlags) {
unsigned Width;
int Number;
Number = (v < 0) ? -v : v;
//
// Get actual field width
//
Width = 1u;
while (Number >= (int)Base) {
Number = (Number / (int)Base);
Width++;
}
if (NumDigits > Width) {
Width = NumDigits;
}
if ((FieldWidth > 0u) && ((v < 0) || ((FormatFlags & FORMAT_FLAG_PRINT_SIGN) == FORMAT_FLAG_PRINT_SIGN))) {
FieldWidth--;
}
//
// Print leading spaces if necessary
//
if ((((FormatFlags & FORMAT_FLAG_PAD_ZERO) == 0u) || (NumDigits != 0u)) && ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u)) {
if (FieldWidth != 0u) {
while ((FieldWidth != 0u) && (Width < FieldWidth)) {
FieldWidth--;
_StoreChar(pBufferDesc, ' ');
if (pBufferDesc->ReturnValue < 0) {
break;
}
}
}
}
//
// Print sign if necessary
//
if (pBufferDesc->ReturnValue >= 0) {
if (v < 0) {
v = -v;
_StoreChar(pBufferDesc, '-');
} else if ((FormatFlags & FORMAT_FLAG_PRINT_SIGN) == FORMAT_FLAG_PRINT_SIGN) {
_StoreChar(pBufferDesc, '+');
} else {
}
if (pBufferDesc->ReturnValue >= 0) {
//
// Print leading zeros if necessary
//
if (((FormatFlags & FORMAT_FLAG_PAD_ZERO) == FORMAT_FLAG_PAD_ZERO) && ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u) && (NumDigits == 0u)) {
if (FieldWidth != 0u) {
while ((FieldWidth != 0u) && (Width < FieldWidth)) {
FieldWidth--;
_StoreChar(pBufferDesc, '0');
if (pBufferDesc->ReturnValue < 0) {
break;
}
}
}
}
if (pBufferDesc->ReturnValue >= 0) {
//
// Print number without sign
//
_PrintUnsigned(pBufferDesc, (unsigned)v, Base, NumDigits, FieldWidth, FormatFlags);
}
}
}
}
/*********************************************************************
*
* Public code
*
**********************************************************************
*/
/*********************************************************************
*
* SEGGER_RTT_vprintf
*
* Function description
* Stores a formatted string in SEGGER RTT control block.
* This data is read by the host.
*
* Parameters
* BufferIndex Index of "Up"-buffer to be used. (e.g. 0 for "Terminal")
* sFormat Pointer to format string
* pParamList Pointer to the list of arguments for the format string
*
* Return values
* >= 0: Number of bytes which have been stored in the "Up"-buffer.
* < 0: Error
*/
int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList) {
char c;
SEGGER_RTT_PRINTF_DESC BufferDesc;
int v;
unsigned NumDigits;
unsigned FormatFlags;
unsigned FieldWidth;
char acBuffer[SEGGER_RTT_PRINTF_BUFFER_SIZE];
BufferDesc.pBuffer = acBuffer;
BufferDesc.BufferSize = SEGGER_RTT_PRINTF_BUFFER_SIZE;
BufferDesc.Cnt = 0u;
BufferDesc.RTTBufferIndex = BufferIndex;
BufferDesc.ReturnValue = 0;
do {
c = *sFormat;
sFormat++;
if (c == 0u) {
break;
}
if (c == '%') {
//
// Filter out flags
//
FormatFlags = 0u;
v = 1;
do {
c = *sFormat;
switch (c) {
case '-': FormatFlags |= FORMAT_FLAG_LEFT_JUSTIFY; sFormat++; break;
case '0': FormatFlags |= FORMAT_FLAG_PAD_ZERO; sFormat++; break;
case '+': FormatFlags |= FORMAT_FLAG_PRINT_SIGN; sFormat++; break;
case '#': FormatFlags |= FORMAT_FLAG_ALTERNATE; sFormat++; break;
default: v = 0; break;
}
} while (v);
//
// filter out field with
//
FieldWidth = 0u;
do {
c = *sFormat;
if ((c < '0') || (c > '9')) {
break;
}
sFormat++;
FieldWidth = (FieldWidth * 10u) + ((unsigned)c - '0');
} while (1);
//
// Filter out precision (number of digits to display)
//
NumDigits = 0u;
c = *sFormat;
if (c == '.') {
sFormat++;
do {
c = *sFormat;
if ((c < '0') || (c > '9')) {
break;
}
sFormat++;
NumDigits = NumDigits * 10u + ((unsigned)c - '0');
} while (1);
}
//
// Filter out length modifier
//
c = *sFormat;
do {
if ((c == 'l') || (c == 'h')) {
c = *sFormat;
sFormat++;
} else {
break;
}
} while (1);
//
// Handle specifiers
//
switch (c) {
case 'c': {
char c0;
v = va_arg(*pParamList, int);
c0 = (char)v;
_StoreChar(&BufferDesc, c0);
break;
}
case 'd':
v = va_arg(*pParamList, int);
_PrintInt(&BufferDesc, v, 10u, NumDigits, FieldWidth, FormatFlags);
break;
case 'u':
v = va_arg(*pParamList, int);
_PrintUnsigned(&BufferDesc, (unsigned)v, 10u, NumDigits, FieldWidth, FormatFlags);
break;
case 'x':
case 'X':
v = va_arg(*pParamList, int);
_PrintUnsigned(&BufferDesc, (unsigned)v, 16u, NumDigits, FieldWidth, FormatFlags);
break;
case 's':
{
const char * s = va_arg(*pParamList, const char *);
do {
c = *s;
s++;
if (c == '\0') {
break;
}
_StoreChar(&BufferDesc, c);
} while (BufferDesc.ReturnValue >= 0);
}
break;
case 'p':
v = va_arg(*pParamList, int);
_PrintUnsigned(&BufferDesc, (unsigned)v, 16u, 8u, 8u, 0u);
break;
case '%':
_StoreChar(&BufferDesc, '%');
break;
default:
break;
}
sFormat++;
} else {
_StoreChar(&BufferDesc, c);
}
} while (BufferDesc.ReturnValue >= 0);
if (BufferDesc.ReturnValue > 0) {
//
// Write remaining data, if any
//
if (BufferDesc.Cnt != 0u) {
SEGGER_RTT_Write(BufferIndex, acBuffer, BufferDesc.Cnt);
}
BufferDesc.ReturnValue += (int)BufferDesc.Cnt;
}
return BufferDesc.ReturnValue;
}
/*********************************************************************
*
* SEGGER_RTT_printf
*
* Function description
* Stores a formatted string in SEGGER RTT control block.
* This data is read by the host.
*
* Parameters
* BufferIndex Index of "Up"-buffer to be used. (e.g. 0 for "Terminal")
* sFormat Pointer to format string, followed by the arguments for conversion
*
* Return values
* >= 0: Number of bytes which have been stored in the "Up"-buffer.
* < 0: Error
*
* Notes
* (1) Conversion specifications have following syntax:
* %[flags][FieldWidth][.Precision]ConversionSpecifier
* (2) Supported flags:
* -: Left justify within the field width
* +: Always print sign extension for signed conversions
* 0: Pad with 0 instead of spaces. Ignored when using '-'-flag or precision
* Supported conversion specifiers:
* c: Print the argument as one char
* d: Print the argument as a signed integer
* u: Print the argument as an unsigned integer
* x: Print the argument as an hexadecimal integer
* s: Print the string pointed to by the argument
* p: Print the argument as an 8-digit hexadecimal integer. (Argument shall be a pointer to void.)
*/
int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...) {
va_list ParamList;
va_start(ParamList, sFormat);
return SEGGER_RTT_vprintf(BufferIndex, sFormat, &ParamList);
}
/*************************** End of file ****************************/

File diff suppressed because it is too large Load Diff

@ -0,0 +1,8 @@
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<batchBuild/>
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@ -0,0 +1,560 @@
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<Number>0</Number>
<Key>DLGUARM</Key>
<Name>?1w桴~</Name>
</SetRegEntry>
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<WinNumber>1</WinNumber>
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</WatchWindow1>
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<periodic>0</periodic>
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</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
</RTE>
<LayerInfo>
<Layers>
<Layer>
<LayName>SimplCAN_RX_Int</LayName>
<LayPrjMark>1</LayPrjMark>
</Layer>
</Layers>
</LayerInfo>
</Project>

@ -0,0 +1 @@
功能说明CAN接收例程使用中断

@ -0,0 +1,201 @@
Apache License
Version 2.0, January 2004
http://www.apache.org/licenses/
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
1. Definitions.
"License" shall mean the terms and conditions for use, reproduction,
and distribution as defined by Sections 1 through 9 of this document.
"Licensor" shall mean the copyright owner or entity authorized by
the copyright owner that is granting the License.
"Legal Entity" shall mean the union of the acting entity and all
other entities that control, are controlled by, or are under common
control with that entity. For the purposes of this definition,
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@ -0,0 +1,2 @@
# SWM221_Lib
SWM221 Chip Support Library and Sample Code

@ -0,0 +1,63 @@
#include "SWM221.h"
void SerialInit(void);
int main(void)
{
SystemInit();
SerialInit();
GPIO_Init(GPIOA, PIN5, 1, 0, 0, 0); //GPIOA.5接LED
GPIO_INIT(GPIOA, PIN5, GPIO_OUTPUT); //同上,另一种可读性更好的写法
while(1==1)
{
GPIO_InvBit(GPIOA, PIN5);
printf("Hi, World!\r\n");
for(int i=0; i<SystemCoreClock/4; i++) __NOP();
}
}
void SerialInit(void)
{
UART_InitStructure UART_initStruct;
PORT_Init(PORTA, PIN0, PORTA_PIN0_UART0_RX, 1); //GPIOA.0配置为UART0 RXD
PORT_Init(PORTA, PIN1, PORTA_PIN1_UART0_TX, 0); //GPIOA.1配置为UART0 TXD
UART_initStruct.Baudrate = 57600;
UART_initStruct.DataBits = UART_DATA_8BIT;
UART_initStruct.Parity = UART_PARITY_NONE;
UART_initStruct.StopBits = UART_STOP_1BIT;
UART_initStruct.RXThreshold = 3;
UART_initStruct.RXThresholdIEn = 0;
UART_initStruct.TXThreshold = 3;
UART_initStruct.TXThresholdIEn = 0;
UART_initStruct.TimeoutTime = 10;
UART_initStruct.TimeoutIEn = 0;
UART_Init(UART0, &UART_initStruct);
UART_Open(UART0);
}
/******************************************************************************************************************************************
* : fputc()
* : printf()使
* : int ch
* FILE *f
* :
* :
******************************************************************************************************************************************/
int fputc(int ch, FILE *f)
{
UART_WriteByte(UART0, ch);
while(UART_IsTXBusy(UART0));
return ch;
}

@ -0,0 +1,136 @@
/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 31. July 2014
* $Revision: V1.4.4
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
//extern const q31_t realCoefAQ31[1024];
//extern const q31_t realCoefBQ31[1024];
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* ARM_COMMON_TABLES_H */

@ -0,0 +1,79 @@
/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 31. July 2014
* $Revision: V1.4.4
*
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
*
* Description: This file has constant structs that are initialized for
* user convenience. For example, some can be given as
* arguments to the arm_cfft_f32() function.
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif

@ -0,0 +1,711 @@
/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V4.00
* @date 22. August 2014
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#ifdef __cplusplus
extern "C" {
#endif
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup Cortex_M0
@{
*/
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI__VFP_SUPPORT____
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ ) /* Cosmic */
#if ( __CSMC__ & 0x400) // FPU present for parser
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

@ -0,0 +1,822 @@
/**************************************************************************//**
* @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
* @version V4.00
* @date 22. August 2014
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifndef __CORE_CM0PLUS_H_GENERIC
#define __CORE_CM0PLUS_H_GENERIC
#ifdef __cplusplus
extern "C" {
#endif
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup Cortex-M0+
@{
*/
/* CMSIS CM0P definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
__CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI__VFP_SUPPORT____
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ ) /* Cosmic */
#if ( __CSMC__ & 0x400) // FPU present for parser
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0PLUS_H_DEPENDANT
#define __CORE_CM0PLUS_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0PLUS_REV
#define __CM0PLUS_REV 0x0000
#warning "__CM0PLUS_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex-M0+ */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if (__VTOR_PRESENT == 1)
__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
#endif
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
#if (__VTOR_PRESENT == 1)
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1)
/** \ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/** \brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register */
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0+ Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

@ -0,0 +1,637 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.00
* @date 28. August 2014
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
/* Cosmic specific functions */
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

@ -0,0 +1,880 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.00
* @date 28. August 2014
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
/** \brief Rotate Right with Extend (32 bit)
This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/** \brief LDRT Unprivileged (8 bit)
This function executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/** \brief LDRT Unprivileged (16 bit)
This function executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/** \brief LDRT Unprivileged (32 bit)
This function executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/** \brief STRT Unprivileged (8 bit)
This function executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/** \brief STRT Unprivileged (16 bit)
This function executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/** \brief STRT Unprivileged (32 bit)
This function executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint8_t) result); /* Add explicit type cast here */
}
/** \brief LDR Exclusive (16 bit)
This function executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint16_t) result); /* Add explicit type cast here */
}
/** \brief LDR Exclusive (32 bit)
This function executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return ((uint8_t) result); /* Add explicit type cast here */
}
/** \brief Rotate Right with Extend (32 bit)
This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief LDRT Unprivileged (8 bit)
This function executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint8_t) result); /* Add explicit type cast here */
}
/** \brief LDRT Unprivileged (16 bit)
This function executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint16_t) result); /* Add explicit type cast here */
}
/** \brief LDRT Unprivileged (32 bit)
This function executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STRT Unprivileged (8 bit)
This function executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
}
/** \brief STRT Unprivileged (16 bit)
This function executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
}
/** \brief STRT Unprivileged (32 bit)
This function executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
}
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
/* Cosmic specific functions */
#include <cmsis_csm.h>
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

@ -0,0 +1,697 @@
/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.00
* @date 22. August 2014
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32) ) >> 32))
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SSAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
#define __USAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else // Big endian
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else // Big endian
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else // Big endian
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
{
union llreg_u{
uint32_t w32[2];
uint64_t w64;
} llr;
llr.w64 = acc;
#ifndef __ARMEB__ // Little endian
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
#else // Big endian
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
#endif
return(llr.w64);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
#define __PKHBT(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#define __PKHTB(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
else \
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/* not yet supported */
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
/* Cosmic specific functions */
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */

@ -0,0 +1,331 @@
;******************************************************************************************************************************************
; 文件名称: startup_SWM221.s
; 功能说明: SWM221单片机的启动文件
; 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1
; 注意事项:
; 版本日期: V1.0.0 2016年1月30日
; 升级记录:
;
;
;******************************************************************************************************************************************
; @attention
;
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
; REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
; FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
; OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
; -ECTION WITH THEIR PRODUCTS.
;
; COPYRIGHT 2012 Synwit Technology
;******************************************************************************************************************************************
; Amount of memory (in bytes) allocated for Stack
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; Amount of memory (in bytes) allocated for Heap
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, CODE, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UART0_Handler
DCD TIMR0_Handler
DCD CAN0_Handler
DCD UART1_Handler
DCD PWM1_Handler
DCD TIMR1_Handler
DCD HALL_Handler
DCD PWM0_Handler
DCD QSPI0_Handler
DCD PWMBRK_Handler
DCD USART0_Handler
DCD WDT_Handler
DCD I2C0_Handler
DCD XTALSTOP_Handler
DCD ADC_Handler
DCD ACMP_Handler
DCD BTIMR0_Handler
DCD BTIMR1_Handler
DCD BTIMR2_Handler
DCD BTIMR3_Handler
DCD GPIOA_Handler
DCD GPIOB_Handler
DCD GPIOC_Handler
DCD GPIOA0_GPIOC0_Handler
DCD GPIOA1_GPIOC1_Handler
DCD GPIOA2_GPIOC2_MPU_Handler
DCD GPIOA3_GPIOC3_PVD_Handler
DCD GPIOB0_GPIOA8_TIMR2_Handler
DCD GPIOB1_GPIOA9_DMA_Handler
DCD GPIOB2_GPIOA10_DIV_Handler
DCD GPIOB3_GPIOA11_SPI0_Handler
DCD GPIOB4_GPIOB10_QEI_Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
;AREA |.text|, CODE, READONLY
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
UART0_Handler PROC
EXPORT UART0_Handler [WEAK]
B .
ENDP
TIMR0_Handler PROC
EXPORT TIMR0_Handler [WEAK]
B .
ENDP
CAN0_Handler PROC
EXPORT CAN0_Handler [WEAK]
B .
ENDP
UART1_Handler PROC
EXPORT UART1_Handler [WEAK]
B .
ENDP
PWM1_Handler PROC
EXPORT PWM1_Handler [WEAK]
B .
ENDP
TIMR1_Handler PROC
EXPORT TIMR1_Handler [WEAK]
B .
ENDP
HALL_Handler PROC
EXPORT HALL_Handler [WEAK]
B .
ENDP
PWM0_Handler PROC
EXPORT PWM0_Handler [WEAK]
B .
ENDP
QSPI0_Handler PROC
EXPORT QSPI0_Handler [WEAK]
B .
ENDP
PWMBRK_Handler PROC
EXPORT PWMBRK_Handler [WEAK]
B .
ENDP
USART0_Handler PROC
EXPORT USART0_Handler [WEAK]
B .
ENDP
WDT_Handler PROC
EXPORT WDT_Handler [WEAK]
B .
ENDP
I2C0_Handler PROC
EXPORT I2C0_Handler [WEAK]
B .
ENDP
XTALSTOP_Handler PROC
EXPORT XTALSTOP_Handler [WEAK]
B .
ENDP
ADC_Handler PROC
EXPORT ADC_Handler [WEAK]
B .
ENDP
ACMP_Handler PROC
EXPORT ACMP_Handler [WEAK]
B .
ENDP
BTIMR0_Handler PROC
EXPORT BTIMR0_Handler [WEAK]
B .
ENDP
BTIMR1_Handler PROC
EXPORT BTIMR1_Handler [WEAK]
B .
ENDP
BTIMR2_Handler PROC
EXPORT BTIMR2_Handler [WEAK]
B .
ENDP
BTIMR3_Handler PROC
EXPORT BTIMR3_Handler [WEAK]
B .
ENDP
GPIOA_Handler PROC
EXPORT GPIOA_Handler [WEAK]
B .
ENDP
GPIOB_Handler PROC
EXPORT GPIOB_Handler [WEAK]
B .
ENDP
GPIOC_Handler PROC
EXPORT GPIOC_Handler [WEAK]
B .
ENDP
GPIOA0_GPIOC0_Handler PROC
EXPORT GPIOA0_GPIOC0_Handler [WEAK]
B .
ENDP
GPIOA1_GPIOC1_Handler PROC
EXPORT GPIOA1_GPIOC1_Handler [WEAK]
B .
ENDP
GPIOA2_GPIOC2_MPU_Handler PROC
EXPORT GPIOA2_GPIOC2_MPU_Handler [WEAK]
B .
ENDP
GPIOA3_GPIOC3_PVD_Handler PROC
EXPORT GPIOA3_GPIOC3_PVD_Handler [WEAK]
B .
ENDP
GPIOB0_GPIOA8_TIMR2_Handler PROC
EXPORT GPIOB0_GPIOA8_TIMR2_Handler [WEAK]
B .
ENDP
GPIOB1_GPIOA9_DMA_Handler PROC
EXPORT GPIOB1_GPIOA9_DMA_Handler [WEAK]
B .
ENDP
GPIOB2_GPIOA10_DIV_Handler PROC
EXPORT GPIOB2_GPIOA10_DIV_Handler [WEAK]
B .
ENDP
GPIOB3_GPIOA11_SPI0_Handler PROC
EXPORT GPIOB3_GPIOA11_SPI0_Handler [WEAK]
B .
ENDP
GPIOB4_GPIOB10_QEI_Handler PROC
EXPORT GPIOB4_GPIOB10_QEI_Handler [WEAK]
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

@ -0,0 +1,175 @@
.syntax unified
.arch armv6-m
/* Memory Model
The HEAP starts at the end of the DATA section and grows upward.
The STACK starts at the end of the RAM and grows downward */
.section .stack
.align 3
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space 0x800
__StackTop:
.section .heap
.align 3
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.space 0x000
__HeapLimit:
.section .isr_vector
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop
.long Reset_Handler
.long NMI_Handler
.long HardFault_Handler
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long SVC_Handler
.long 0
.long 0
.long PendSV_Handler
.long SysTick_Handler
/* External interrupts */
.long UART0_Handler
.long TIMR0_Handler
.long CAN0_Handler
.long UART1_Handler
.long PWM1_Handler
.long TIMR1_Handler
.long HALL_Handler
.long PWM0_Handler
.long QSPI0_Handler
.long PWMBRK_Handler
.long USART0_Handler
.long WDT_Handler
.long I2C0_Handler
.long XTALSTOP_Handler
.long ADC_Handler
.long ACMP_Handler
.long BTIMR0_Handler
.long BTIMR1_Handler
.long BTIMR2_Handler
.long BTIMR3_Handler
.long GPIOA_Handler
.long GPIOB_Handler
.long GPIOC_Handler
.long GPIOA0_GPIOC0_Handler
.long GPIOA1_GPIOC1_Handler
.long GPIOA2_GPIOC2_MPU_Handler
.long GPIOA3_GPIOC3_PVD_Handler
.long GPIOB0_GPIOA8_TIMR2_Handler
.long GPIOB1_GPIOA9_DMA_Handler
.long GPIOB2_GPIOA10_DIV_Handler
.long GPIOB3_GPIOA11_SPI0_Handler
.long GPIOB4_GPIOB10_QEI_Handler
.section .text.Reset_Handler
.align 2
.thumb
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by symbols evaluated in linker script. */
ldr r1, =__data_load__
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .Lflash_to_ram_done
.Lflash_to_ram_loop:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .Lflash_to_ram_loop
.Lflash_to_ram_done:
ldr r2, =__bss_start__
ldr r3, =__bss_end__
subs r3, r2
ble .Lbss_to_ram_done
movs r0, 0
.Lbss_to_ram_loop:
subs r3, #4
str r0, [r2, r3]
bgt .Lbss_to_ram_loop
.Lbss_to_ram_done:
ldr r0, =main
bx r0
.pool
.text
/* Macro to define default handlers.
Default handler will be weak symbol and just dead loops. */
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler SVC_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler UART0_Handler
def_default_handler TIMR0_Handler
def_default_handler CAN0_Handler
def_default_handler UART1_Handler
def_default_handler PWM1_Handler
def_default_handler TIMR1_Handler
def_default_handler HALL_Handler
def_default_handler PWM0_Handler
def_default_handler QSPI0_Handler
def_default_handler PWMBRK_Handler
def_default_handler USART0_Handler
def_default_handler WDT_Handler
def_default_handler I2C0_Handler
def_default_handler XTALSTOP_Handler
def_default_handler ADC_Handler
def_default_handler ACMP_Handler
def_default_handler BTIMR0_Handler
def_default_handler BTIMR1_Handler
def_default_handler BTIMR2_Handler
def_default_handler BTIMR3_Handler
def_default_handler GPIOA_Handler
def_default_handler GPIOB_Handler
def_default_handler GPIOC_Handler
def_default_handler GPIOA0_GPIOC0_Handler
def_default_handler GPIOA1_GPIOC1_Handler
def_default_handler GPIOA2_GPIOC2_MPU_Handler
def_default_handler GPIOA3_GPIOC3_PVD_Handler
def_default_handler GPIOB0_GPIOA8_TIMR2_Handler
def_default_handler GPIOB1_GPIOA9_DMA_Handler
def_default_handler GPIOB2_GPIOA10_DIV_Handler
def_default_handler GPIOB3_GPIOA11_SPI0_Handler
def_default_handler GPIOB4_GPIOB10_QEI_Handler
def_default_handler Default_Handler
.end

@ -0,0 +1,280 @@
;******************************************************************************************************************************************
; 文件名称: startup_SWM221.s
; 功能说明: SWM221单片机的启动文件
; 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1
; 注意事项:
; 版本日期: V1.0.0 2016年1月30日
; 升级记录:
;
;
;******************************************************************************************************************************************
; @attention
;
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
; REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
; FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
; OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
; -ECTION WITH THEIR PRODUCTS.
;
; COPYRIGHT 2012 Synwit Technology
;******************************************************************************************************************************************
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UART0_Handler
DCD TIMR0_Handler
DCD CAN0_Handler
DCD UART1_Handler
DCD PWM1_Handler
DCD TIMR1_Handler
DCD HALL_Handler
DCD PWM0_Handler
DCD QSPI0_Handler
DCD PWMBRK_Handler
DCD USART0_Handler
DCD WDT_Handler
DCD I2C0_Handler
DCD XTALSTOP_Handler
DCD ADC_Handler
DCD ACMP_Handler
DCD BTIMR0_Handler
DCD BTIMR1_Handler
DCD BTIMR2_Handler
DCD BTIMR3_Handler
DCD GPIOA_Handler
DCD GPIOB_Handler
DCD GPIOC_Handler
DCD GPIOA0_GPIOC0_Handler
DCD GPIOA1_GPIOC1_Handler
DCD GPIOA2_GPIOC2_MPU_Handler
DCD GPIOA3_GPIOC3_PVD_Handler
DCD GPIOB0_GPIOA8_TIMR2_Handler
DCD GPIOB1_GPIOA9_DMA_Handler
DCD GPIOB2_GPIOA10_DIV_Handler
DCD GPIOB3_GPIOA11_SPI0_Handler
DCD GPIOB4_GPIOB10_QEI_Handler
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK UART0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UART0_Handler
B UART0_Handler
PUBWEAK TIMR0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMR0_Handler
B TIMR0_Handler
PUBWEAK CAN0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
CAN0_Handler
B CAN0_Handler
PUBWEAK UART1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UART1_Handler
B UART1_Handler
PUBWEAK PWM1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM1_Handler
B PWM1_Handler
PUBWEAK TIMR1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMR1_Handler
B TIMR1_Handler
PUBWEAK HALL_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HALL_Handler
B HALL_Handler
PUBWEAK PWM0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWM0_Handler
B PWM0_Handler
PUBWEAK QSPI0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
QSPI0_Handler
B QSPI0_Handler
PUBWEAK PWMBRK_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PWMBRK_Handler
B PWMBRK_Handler
PUBWEAK USART0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
USART0_Handler
B USART0_Handler
PUBWEAK WDT_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
WDT_Handler
B WDT_Handler
PUBWEAK I2C0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
I2C0_Handler
B I2C0_Handler
PUBWEAK XTALSTOP_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
XTALSTOP_Handler
B XTALSTOP_Handler
PUBWEAK ADC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
ADC_Handler
B ADC_Handler
PUBWEAK ACMP_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
ACMP_Handler
B ACMP_Handler
PUBWEAK BTIMR0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BTIMR0_Handler
B BTIMR0_Handler
PUBWEAK BTIMR1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BTIMR1_Handler
B BTIMR1_Handler
PUBWEAK BTIMR2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BTIMR2_Handler
B BTIMR2_Handler
PUBWEAK BTIMR3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BTIMR3_Handler
B BTIMR3_Handler
PUBWEAK GPIOA_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOA_Handler
B GPIOA_Handler
PUBWEAK GPIOB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOB_Handler
B GPIOB_Handler
PUBWEAK GPIOC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOC_Handler
B GPIOC_Handler
PUBWEAK GPIOA0_GPIOC0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOA0_GPIOC0_Handler
B GPIOA0_GPIOC0_Handler
PUBWEAK GPIOA1_GPIOC1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOA1_GPIOC1_Handler
B GPIOA1_GPIOC1_Handler
PUBWEAK GPIOA2_GPIOC2_MPU_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOA2_GPIOC2_MPU_Handler
B GPIOA2_GPIOC2_MPU_Handler
PUBWEAK GPIOA3_GPIOC3_PVD_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOA3_GPIOC3_PVD_Handler
B GPIOA3_GPIOC3_PVD_Handler
PUBWEAK GPIOB0_GPIOA8_TIMR2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOB0_GPIOA8_TIMR2_Handler
B GPIOB0_GPIOA8_TIMR2_Handler
PUBWEAK GPIOB1_GPIOA9_DMA_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOB1_GPIOA9_DMA_Handler
B GPIOB1_GPIOA9_DMA_Handler
PUBWEAK GPIOB2_GPIOA10_DIV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOB2_GPIOA10_DIV_Handler
B GPIOB2_GPIOA10_DIV_Handler
PUBWEAK GPIOB3_GPIOA11_SPI0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOB3_GPIOA11_SPI0_Handler
B GPIOB3_GPIOA11_SPI0_Handler
PUBWEAK GPIOB4_GPIOB10_QEI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOB4_GPIOB10_QEI_Handler
B GPIOB4_GPIOB10_QEI_Handler
END

@ -0,0 +1,224 @@
/******************************************************************************************************************************************
* : system_SWM221.c
* : SWM221
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.0.0 2016130
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include <stdint.h>
#include "SWM221.h"
/******************************************************************************************************************************************
*
*****************************************************************************************************************************************/
#define SYS_CLK_8MHz 3 //内部高频8MHz RC振荡器
#define SYS_CLK_XTAL 2 //外部晶体振荡器4-24MHz
#define SYS_CLK_PLL 1 //锁相环输出
#define SYS_CLK_32KHz 0 //内部低频32KHz RC振荡器
#define SYS_CLK SYS_CLK_PLL
#define SYS_CLK_DIV SYS_CLK_DIV_1 //SYS_CLK 选择的时钟,经过 SYS_CLK_DIV 分频后用作系统时钟
#define __HSI ( 8000000UL) //高速内部时钟
#define __LSI ( 32000UL) //低速内部时钟
#define __HSE (12000000UL) //高速外部时钟
#define __LSE ( 32768UL) //低速外部时钟
/********************************** PLL 设定 **********************************************
* PLL = PLL / INDIV * FBDIV
*****************************************************************************************/
#define SYS_PLL_SRC SYS_CLK_XTAL //可取值SYS_CLK_8MHz、SYS_CLK_XTAL
#define PLL_IN_DIV 3
#define PLL_FB_DIV 15
uint32_t SystemCoreClock = __HSI; //System Clock Frequency (Core Clock)
uint32_t CyclesPerUs = (__HSI / 1000000); //Cycles per micro second
/******************************************************************************************************************************************
* : SystemCoreClockUpdate()
* : This function is used to update the variable SystemCoreClock and must be called whenever the core clock is changed
* :
* :
* :
******************************************************************************************************************************************/
void SystemCoreClockUpdate(void)
{
if(SYS->CLKSEL & SYS_CLKSEL_SYS_Msk) //SYS <= HRC
{
SystemCoreClock = __HSI;
}
else //SYS <= CLK
{
switch((SYS->CLKSEL & SYS_CLKSEL_CLK_Msk) >> SYS_CLKSEL_CLK_Pos)
{
case SYS_CLK_8MHz:
SystemCoreClock = __HSI;
break;
case SYS_CLK_XTAL:
SystemCoreClock = __HSE;
break;
case SYS_CLK_PLL:
{
uint32_t indiv = (SYS->PLLCR & SYS_PLLCR_INDIV_Msk) >> SYS_PLLCR_INDIV_Pos;
uint32_t fbdiv = (SYS->PLLCR & SYS_PLLCR_FBDIV_Msk) >> SYS_PLLCR_FBDIV_Pos;
if(SYS->PLLCR & SYS_PLLCR_INSEL_Msk)
{
SystemCoreClock = __HSE * fbdiv / indiv;
}
else
{
SystemCoreClock = __HSI * fbdiv / indiv;
}
break;
}
case SYS_CLK_32KHz:
SystemCoreClock = __LSI;
break;
}
SystemCoreClock /= (1 << ((SYS->CLKSEL & SYS_CLKSEL_CLK_DIVx_Msk) >> SYS_CLKSEL_CLK_DIVx_Pos));
}
CyclesPerUs = SystemCoreClock / 1000000;
}
/******************************************************************************************************************************************
* :
* : The necessary initializaiton of systerm
* :
* :
* :
******************************************************************************************************************************************/
void SystemInit(void)
{
SYS->CLKEN0 |= (1 << SYS_CLKEN0_ANAC_Pos);
Flash_Param_at_xMHz(72);
switchToHRC();
switch(SYS_CLK)
{
case SYS_CLK_8MHz:
switchOnHRC();
break;
case SYS_CLK_XTAL:
switchOnXTAL();
break;
case SYS_CLK_PLL:
switchOnPLL(SYS_PLL_SRC, PLL_IN_DIV, PLL_FB_DIV);
break;
case SYS_CLK_32KHz:
switchOn32KHz();
break;
}
switchToDIV(SYS_CLK, SYS_CLK_DIV);
Flash_Param_at_xMHz(CyclesPerUs);
Cache_Clear(); // Cache Clear
FMC->CACHE |= FMC_CACHE_CEN_Msk; // Cache Enable
PORTB->PULLD &= ~((1 << PIN10) | (1 << PIN11));
PORTB->PULLU &= ~((1 << PIN12) | (1 << PIN15));
}
void switchToHRC(void)
{
SYS->RCCR |= (1 << SYS_RCCR_HON_Pos);
for(int i = 0; i < CyclesPerUs; i++) {}
SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS <= HRC
SystemCoreClockUpdate();
}
void switchToDIV(uint32_t src, uint32_t div)
{
SYS->CLKSEL &=~(SYS_CLKSEL_CLK_Msk | SYS_CLKSEL_CLK_DIVx_Msk);
SYS->CLKSEL |= (src << SYS_CLKSEL_CLK_Pos) |
(div << SYS_CLKSEL_CLK_DIVx_Pos);
SYS->CLKDIVx_ON = 1;
for(int i = 0; i < CyclesPerUs; i++) {}
SYS->CLKSEL &=~(1 << SYS_CLKSEL_SYS_Pos); //SYS <= CLK_DIVx
SystemCoreClockUpdate();
}
void switchOnHRC(void)
{
SYS->RCCR |= (1 << SYS_RCCR_HON_Pos);
}
void switchOnXTAL(void)
{
PORTB->PULLU &= ~((1 << PIN11) | (1 << PIN12));
PORTB->PULLD &= ~((1 << PIN11) | (1 << PIN12));
PORT_Init(PORTB, PIN11, PORTB_PIN11_XTAL_IN, 0);
PORT_Init(PORTB, PIN12, PORTB_PIN12_XTAL_OUT, 0);
SYS->XTALCR |= (1 << SYS_XTALCR_ON_Pos) | (1 << SYS_XTALCR_DET_Pos);
}
void switchOnPLL(uint32_t src, uint32_t indiv, uint32_t fbdiv)
{
if(src == SYS_CLK_XTAL)
switchOnXTAL();
else
switchOnHRC();
SYS->PLLCR = (0 << SYS_PLLCR_PWRDN_Pos) |
(1 << SYS_PLLCR_OUTEN_Pos) |
((src == SYS_CLK_XTAL) << SYS_PLLCR_INSEL_Pos) |
(0 << SYS_PLLCR_BYPASS_Pos) |
(indiv << SYS_PLLCR_INDIV_Pos) |
(fbdiv << SYS_PLLCR_FBDIV_Pos);
while((SYS->PLLSR & SYS_PLLSR_LOCK_Msk) == 0) __NOP(); //等待PLL锁定
SYS->PLLSR |= SYS_PLLSR_ENA_Msk;
}
void switchOn32KHz(void)
{
SYS->RCCR |= (1 << SYS_RCCR_LON_Pos);
}

@ -0,0 +1,43 @@
#ifndef __SYSTEM_SWM221_H__
#define __SYSTEM_SWM221_H__
#ifdef __cplusplus
extern "C" {
#endif
#define SYS_CLK_8MHz 3 //内部高频8MHz RC振荡器
#define SYS_CLK_XTAL 2 //外部晶体振荡器4-24MHz
#define SYS_CLK_PLL 1 //锁相环输出
#define SYS_CLK_32KHz 0 //内部低频32KHz RC振荡器
#define SYS_CLK_DIV_1 0
#define SYS_CLK_DIV_2 1
#define SYS_CLK_DIV_4 2
#define SYS_CLK_DIV_8 3
extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock)
extern uint32_t CyclesPerUs; // Cycles per micro second
extern void SystemInit(void);
extern void SystemCoreClockUpdate (void);
extern void switchToHRC(void);
extern void switchToDIV(uint32_t src, uint32_t div);
extern void switchOnHRC(void);
extern void switchOnXTAL(void);
extern void switchOnPLL(uint32_t src, uint32_t indiv, uint32_t fbdiv);
extern void switchOn32KHz(void);
#ifdef __cplusplus
}
#endif
#endif //__SYSTEM_SWM221_H__

@ -0,0 +1,311 @@
/******************************************************************************************************************************************
* : SWM341_adc.c
* : SWM341ADC
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.0.0 2016130
* :
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM221.h"
#include "SWM221_adc.h"
/******************************************************************************************************************************************
* : ADC_Init()
* : ADC
* : ADC_TypeDef * ADCx ADCADC0ADC1
* ADC_InitStructure * initStruct ADC
* :
* :
******************************************************************************************************************************************/
void ADC_Init(ADC_TypeDef * ADCx, ADC_InitStructure * initStruct)
{
switch((uint32_t)ADCx)
{
case ((uint32_t)ADC0):
case ((uint32_t)ADC1):
SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_ADC0_Pos);
break;
}
ADC_Close(ADCx); //一些关键寄存器只能在ADC关闭时设置
ADCx->CR &= ~(ADC_CR_CLKDIV_Msk | ADC_CR_AVG_Msk | ADC_CR_BITS_Pos);
ADCx->CR |= ((initStruct->clkdiv - 1) << ADC_CR_CLKDIV_Pos) |
(initStruct->samplAvg << ADC_CR_AVG_Pos) |
(0 << ADC_CR_BITS_Pos);
if(initStruct->refsrc & (1 << 0))
{
PORT_Init(PORTA, PIN11, PORTA_PIN11_ADC_REFP, 0);
if(initStruct->refsrc & (1 << 1))
{
SYS->VRFCR &=~SYS_VRFCR_LVL_Msk;
SYS->VRFCR |= (initStruct->refsrc >> 2) << SYS_VRFCR_LVL_Pos;
SYS->VRFCR |= SYS_VRFCR_EN_Msk;
}
else
{
SYS->VRFCR &=~SYS_VRFCR_EN_Msk;
}
SYS->ADCREF |= SYS_ADCREF_REFSEL_Msk;
}
else
{
SYS->ADCREF &=~SYS_ADCREF_REFSEL_Msk;
}
}
static uint32_t ADC_seq2pos(uint32_t seq)
{
uint32_t pos = 0;
switch(seq)
{
case ADC_SEQ0: pos = 0; break;
case ADC_SEQ1: pos = 8; break;
}
return pos;
}
/******************************************************************************************************************************************
* : ADC_SEQ_Init()
* : ADC
* : ADC_TypeDef * ADCx ADCADC0ADC1
* uint32_t seq ADC_SEQ0ADC_SEQ1
* ADC_SEQ_InitStructure * initStruct ADC
* :
* :
******************************************************************************************************************************************/
void ADC_SEQ_Init(ADC_TypeDef * ADCx, uint32_t seq, ADC_SEQ_InitStructure * initStruct)
{
uint32_t pos = ADC_seq2pos(seq);
ADCx->SEQTRG &= ~(0xFFu << pos);
ADCx->SEQTRG |= (initStruct->trig_src << pos);
ADCx->SMPTIM &= ~(0xFFu << pos);
ADCx->SMPTIM |= ((initStruct->samp_tim - 4) << pos);
ADCx->SMPNUM &= ~(0xFFu << pos);
ADCx->SMPNUM |= ((initStruct->conv_cnt - 1) << pos);
ADCx->IE |= (initStruct->EOCIntEn << pos);
if(initStruct->EOCIntEn)
NVIC_EnableIRQ(ADC_IRQn);
__IO uint32_t * SEQxCHN = (seq == ADC_SEQ0) ? &ADCx->SEQ0CHN : &ADCx->SEQ1CHN;
*SEQxCHN = 0;
for(int i = 0; i < 8; i++)
{
*SEQxCHN |= initStruct->channels[i] << (i * 4);
if(initStruct->channels[i] == 0xF)
break;
}
}
/******************************************************************************************************************************************
* : ADC_CMP_Init()
* : ADC
* : ADC_TypeDef * ADCx ADCADC0ADC1
* uint32_t seq ADC_SEQ0ADC_SEQ1
* ADC_CMP_InitStructure * initStruct ADC
* :
* :
******************************************************************************************************************************************/
void ADC_CMP_Init(ADC_TypeDef * ADCx, uint32_t seq, ADC_CMP_InitStructure * initStruct)
{
if(seq == ADC_SEQ0)
ADCx->SEQ0CHK = (initStruct->UpperLimit << ADC_SEQ0CHK_MAX_Pos) |
(initStruct->LowerLimit << ADC_SEQ0CHK_MIN_Pos);
else
ADCx->SEQ1CHK = (initStruct->UpperLimit << ADC_SEQ1CHK_MAX_Pos) |
(initStruct->LowerLimit << ADC_SEQ1CHK_MIN_Pos);
if(initStruct->UpperLimitIEn)
ADC_INTEn(ADCx, seq, ADC_IT_CMP_MAX);
if(initStruct->LowerLimitIEn)
ADC_INTEn(ADCx, seq, ADC_IT_CMP_MIN);
if(initStruct->UpperLimitIEn || initStruct->LowerLimitIEn)
NVIC_EnableIRQ(ADC_IRQn);
}
/******************************************************************************************************************************************
* : ADC_Open()
* : ADCADC
* : ADC_TypeDef * ADCx ADCADC0ADC1
* :
* :
******************************************************************************************************************************************/
void ADC_Open(ADC_TypeDef * ADCx)
{
ADCx->CR &= ~ADC_CR_PWDN_Msk;
int clkdiv = ((ADCx->CR & ADC_CR_CLKDIV_Msk) >> ADC_CR_CLKDIV_Pos) + 1;
for(int i = 0; i < clkdiv * 32; i++) {} // 退出 Powerdown 32 个采样时钟周期后才能工作
}
/******************************************************************************************************************************************
* : ADC_Close()
* : ADCADC
* : ADC_TypeDef * ADCx ADCADC0ADC1
* :
* :
******************************************************************************************************************************************/
void ADC_Close(ADC_TypeDef * ADCx)
{
ADCx->CR |= ADC_CR_PWDN_Msk;
}
/******************************************************************************************************************************************
* : ADC_Start()
* : ADC
* : uint32_t ADC0_seq ADC0ADC_SEQ0ADC_SEQ1
* uint32_t ADC1_seq ADC1ADC_SEQ0ADC_SEQ1
* :
* :
******************************************************************************************************************************************/
void ADC_Start(uint32_t ADC0_seq, uint32_t ADC1_seq)
{
ADC0->START |= (ADC0_seq << ADC_START_ADC0SEQ0_Pos) |
(ADC1_seq << ADC_START_ADC1SEQ0_Pos);
}
/******************************************************************************************************************************************
* : ADC_Stop()
* : ADC
* : uint32_t ADC0_seq ADC0ADC_SEQ0ADC_SEQ1
* uint32_t ADC1_seq ADC1ADC_SEQ0ADC_SEQ1
* :
* :
******************************************************************************************************************************************/
void ADC_Stop(uint32_t ADC0_seq, uint32_t ADC1_seq)
{
ADC0->START &= ~((ADC0_seq << ADC_START_ADC0SEQ0_Pos) |
(ADC1_seq << ADC_START_ADC1SEQ0_Pos));
}
/******************************************************************************************************************************************
* : ADC_Busy()
* : ADC
* : ADC_TypeDef * ADCx ADCADC0ADC1
* : bool true false
* :
******************************************************************************************************************************************/
bool ADC_Busy(ADC_TypeDef * ADCx)
{
if(ADCx == ADC0)
return ADC0->START & ADC_START_ADC0BUSY_Msk;
else
return ADC0->START & ADC_START_ADC1BUSY_Msk;
}
/******************************************************************************************************************************************
* : ADC_Read()
* :
* : ADC_TypeDef * ADCx ADCADC0ADC1
* uint32_t chn ADC_CH0ADC_CH1... ...ADC_CH10ADC_CH11
* : uint32_t
* :
******************************************************************************************************************************************/
uint32_t ADC_Read(ADC_TypeDef * ADCx, uint32_t chn)
{
return ADCx->DATA[chn] & ADC_DATA_DATA_Msk;
}
/******************************************************************************************************************************************
* : ADC_DataAvailable()
* :
* : ADC_TypeDef * ADCx ADCADC0ADC1
* uint32_t chn ADC_CH0ADC_CH1... ...ADC_CH10ADC_CH11
* : uint32_t 1 0
* : ADC ADCx->DATA.FLAG
******************************************************************************************************************************************/
uint32_t ADC_DataAvailable(ADC_TypeDef * ADCx, uint32_t chn)
{
return (ADCx->DATA[chn] & ADC_DATA_FLAG_Msk) != 0;
}
/******************************************************************************************************************************************
* : ADC_INTEn()
* : 使
* : ADC_TypeDef * ADCx ADCADC0ADC1
* uint32_t seq ADCADC_SEQ0ADC_SEQ1
* uint32_t it interrupt typeADC_IT_EOCADC_IT_CMP_MAXADC_IT_CMP_MIN
* :
* :
******************************************************************************************************************************************/
void ADC_INTEn(ADC_TypeDef * ADCx, uint32_t seq, uint32_t it)
{
uint32_t pos = ADC_seq2pos(seq);
ADCx->IE |= (it << pos);
}
/******************************************************************************************************************************************
* : ADC_INTDis()
* :
* : ADC_TypeDef * ADCx ADCADC0ADC1
* uint32_t seq ADCADC_SEQ0ADC_SEQ1
* uint32_t it interrupt typeADC_IT_EOCADC_IT_CMP_MAXADC_IT_CMP_MIN
* :
* :
******************************************************************************************************************************************/
void ADC_INTDis(ADC_TypeDef * ADCx, uint32_t seq, uint32_t it)
{
uint32_t pos = ADC_seq2pos(seq);
ADCx->IE &= ~(it << pos);
}
/******************************************************************************************************************************************
* : ADC_INTClr()
* :
* : ADC_TypeDef * ADCx ADCADC0ADC1
* uint32_t seq ADCADC_SEQ0ADC_SEQ1
* uint32_t it interrupt typeADC_IT_EOCADC_IT_CMP_MAXADC_IT_CMP_MIN
* :
* :
******************************************************************************************************************************************/
void ADC_INTClr(ADC_TypeDef * ADCx, uint32_t seq, uint32_t it)
{
uint32_t pos = ADC_seq2pos(seq);
ADCx->IF = (it << pos);
}
/******************************************************************************************************************************************
* : ADC_INTStat()
* :
* : ADC_TypeDef * ADCx ADCADC0ADC1
* uint32_t seq ADCADC_SEQ0ADC_SEQ1
* uint32_t it interrupt typeADC_IT_EOCADC_IT_CMP_MAXADC_IT_CMP_MIN
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t ADC_INTStat(ADC_TypeDef * ADCx, uint32_t seq, uint32_t it)
{
uint32_t pos = ADC_seq2pos(seq);
return (ADCx->IF & (it << pos)) ? 1 : 0;
}

@ -0,0 +1,88 @@
#ifndef __SWM221_ADC_H__
#define __SWM221_ADC_H__
typedef struct {
uint8_t clkdiv; //1-32
uint8_t refsrc; //ADC_REF_VDD、ADC_REF_REFP、ADC_REF_2V4、ADC_REF_3V6、ADC_REF_4V5
uint8_t samplAvg; //ADC_AVG_SAMPLE1、ADC_AVG_SAMPLE2、ADC_AVG_SAMPLE4、ADC_AVG_SAMPLE8
} ADC_InitStructure;
typedef struct {
uint8_t trig_src; //ADC序列触发方式ADC_TRIGGER_SW、ADC_TRIGGER_TIMER0、ADC_TRIGGER_TIMER1、... ...
uint8_t samp_tim; //ADC序列采样时间可取值4--259
uint8_t conv_cnt; //ADC序列转换次数可取值1--256
uint8_t EOCIntEn; //转换完成中断使能可取值0、1
uint8_t *channels; //序列转换通道选择,元素为 ADC_CH0、ADC_CH1、...、ADC_CH11 的数组,最多 8 个通道,以 0xF 结束,通道可重复
} ADC_SEQ_InitStructure;
typedef struct {
uint16_t UpperLimit; //比较上限值
uint16_t UpperLimitIEn; //ADC转换结果大于UpperLimit中断使能
uint16_t LowerLimit; //比较下限值
uint16_t LowerLimitIEn; //ADC转换结果小于LowerLimit中断使能
} ADC_CMP_InitStructure;
#define ADC_SEQ0 0x1
#define ADC_SEQ1 0x2
#define ADC_CH0 0
#define ADC_CH1 1
#define ADC_CH2 2
#define ADC_CH3 3
#define ADC_CH4 4
#define ADC_CH5 5
#define ADC_CH6 6
#define ADC_CH7 7
#define ADC_CH8 8
#define ADC_CH9 9
#define ADC_REF_VDD (0)
#define ADC_REF_REFP (1 | (0 << 1))
#define ADC_REF_2V4 (1 | (1 << 1) | (0 << 2))
#define ADC_REF_3V6 (1 | (1 << 1) | (1 << 2))
#define ADC_REF_4V5 (1 | (1 << 1) | (2 << 2))
#define ADC_AVG_SAMPLE1 0
#define ADC_AVG_SAMPLE2 1 //一次启动连续采样、转换2次并计算两次结果的平均值作为转换结果
#define ADC_AVG_SAMPLE4 2
#define ADC_AVG_SAMPLE8 3
#define ADC_TRIGGER_NO 0
#define ADC_TRIGGER_SW 1 //软件启动
#define ADC_TRIGGER_TIMER0 2
#define ADC_TRIGGER_TIMER1 3
#define ADC_TRIGGER_TIMER2 4
#define ADC_TRIGGER_PWM0 16
#define ADC_TRIGGER_PWM1 17
/* Interrupt Type */
#define ADC_IT_EOC (1 << 0) //End Of Conversion
#define ADC_IT_CMP_MAX (1 << 1) //转换结果大于COMP.MAX
#define ADC_IT_CMP_MIN (1 << 2) //转换结果小于COMP.MIN
void ADC_Init(ADC_TypeDef * ADCx, ADC_InitStructure * initStruct); //ADC模数转换器初始化
void ADC_SEQ_Init(ADC_TypeDef * ADCx, uint32_t seq, ADC_SEQ_InitStructure * initStruct); //ADC序列初始化
void ADC_CMP_Init(ADC_TypeDef * ADCx, uint32_t seq, ADC_CMP_InitStructure * initStruct); //ADC比较功能初始化
void ADC_Open(ADC_TypeDef * ADCx); //ADC开启可以软件启动、或硬件触发ADC转换
void ADC_Close(ADC_TypeDef * ADCx); //ADC关闭无法软件启动、或硬件触发ADC转换
void ADC_Start(uint32_t ADC0_seq, uint32_t ADC1_seq); //启动指定ADC开始模数转换
void ADC_Stop(uint32_t ADC0_seq, uint32_t ADC1_seq); //关闭指定ADC停止模数转换
bool ADC_Busy(ADC_TypeDef * ADCx);
uint32_t ADC_Read(ADC_TypeDef * ADCx, uint32_t chn); //从指定通道读取转换结果
uint32_t ADC_DataAvailable(ADC_TypeDef * ADCx, uint32_t chn); //指定通道是否有数据可读取
void ADC_INTEn(ADC_TypeDef * ADCx, uint32_t seq, uint32_t it);
void ADC_INTEn(ADC_TypeDef * ADCx, uint32_t seq, uint32_t it);
void ADC_INTClr(ADC_TypeDef * ADCx, uint32_t seq, uint32_t it);
uint32_t ADC_INTStat(ADC_TypeDef * ADCx, uint32_t seq, uint32_t it);
#endif //__SWM221_ADC_H__

@ -0,0 +1,427 @@
/******************************************************************************************************************************************
* : SWM221_can.c
* : SWM221CAN
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM221.h"
#include "SWM221_can.h"
/******************************************************************************************************************************************
* : CAN_Init()
* : CAN
* : CAN_TypeDef * CANx CANCAN0
* CAN_InitStructure * initStruct CAN
* :
* :
******************************************************************************************************************************************/
void CAN_Init(CAN_TypeDef * CANx, CAN_InitStructure * initStruct)
{
uint32_t brp = SystemCoreClock/2/initStruct->Baudrate/(1 + (initStruct->CAN_bs1 + 1) + (initStruct->CAN_bs2 + 1)) - 1;
switch((uint32_t)CANx)
{
case ((uint32_t)CAN0):
SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_CAN0_Pos);
break;
}
CAN_Close(CANx); //一些关键寄存器只能在CAN关闭时设置
CANx->CR &= ~(CAN_CR_LOM_Msk | CAN_CR_STM_Msk);
CANx->CR |= (initStruct->Mode << CAN_CR_LOM_Pos);
CANx->BT1 = (0 << CAN_BT1_SAM_Pos) |
(initStruct->CAN_bs1 << CAN_BT1_TSEG1_Pos) |
(initStruct->CAN_bs2 << CAN_BT1_TSEG2_Pos);
CANx->BT0 = (initStruct->CAN_sjw << CAN_BT0_SJW_Pos) |
((brp & 0x3F) << CAN_BT0_BRP_Pos);
CANx->BT2 = ((brp >> 6) << CAN_BT2_BRP_Pos);
CANx->RXERR = 0; //只能在复位模式下清除
CANx->TXERR = 0;
CANx->IE = (initStruct->RXNotEmptyIEn << CAN_IE_RXDA_Pos) |
(initStruct->ArbitrLostIEn << CAN_IE_ARBLOST_Pos) |
(initStruct->ErrPassiveIEn << CAN_IE_ERRPASS_Pos);
switch((uint32_t)CANx)
{
case ((uint32_t)CAN0):
if(initStruct->RXNotEmptyIEn | initStruct->ArbitrLostIEn | initStruct->ErrPassiveIEn)
{
NVIC_EnableIRQ(CAN0_IRQn);
}
else
{
NVIC_DisableIRQ(CAN0_IRQn);
}
break;
}
}
/******************************************************************************************************************************************
* : CAN_Open()
* : CAN
* : CAN_TypeDef * CANx CANCAN0
* :
* :
******************************************************************************************************************************************/
void CAN_Open(CAN_TypeDef * CANx)
{
CANx->CR &= ~(0x01 << CAN_CR_RST_Pos); //退出复位模式,进入工作模式
}
/******************************************************************************************************************************************
* : CAN_Close()
* : CAN
* : CAN_TypeDef * CANx CANCAN0
* :
* :
******************************************************************************************************************************************/
void CAN_Close(CAN_TypeDef * CANx)
{
CANx->CR |= (0x01 << CAN_CR_RST_Pos); //进入复位模式,不能发送和接收数据
}
/******************************************************************************************************************************************
* : CAN_Transmit()
* : CAN
* : CAN_TypeDef * CANx CANCAN0
* uint32_t format CAN_FRAME_STD CAN_FRAME_EXT
* uint32_t id ID
* uint8_t data[]
* uint32_t size
* uint32_t once 使NAK
* :
* :
******************************************************************************************************************************************/
void CAN_Transmit(CAN_TypeDef * CANx, uint32_t format, uint32_t id, uint8_t data[], uint32_t size, uint32_t once)
{
uint32_t i;
if(format == CAN_FRAME_STD)
{
CANx->FRAME.INFO = (0 << CAN_INFO_FF_Pos) |
(0 << CAN_INFO_RTR_Pos) |
(size << CAN_INFO_DLC_Pos);
CANx->FRAME.DATA[0] = id >> 3;
CANx->FRAME.DATA[1] = id << 5;
for(i = 0; i < size; i++)
{
CANx->FRAME.DATA[i+2] = data[i];
}
}
else //if(format == CAN_FRAME_EXT)
{
CANx->FRAME.INFO = (1 << CAN_INFO_FF_Pos) |
(0 << CAN_INFO_RTR_Pos) |
(size << CAN_INFO_DLC_Pos);
CANx->FRAME.DATA[0] = id >> 21;
CANx->FRAME.DATA[1] = id >> 13;
CANx->FRAME.DATA[2] = id >> 5;
CANx->FRAME.DATA[3] = id << 3;
for(i = 0; i < size; i++)
{
CANx->FRAME.DATA[i+4] = data[i];
}
}
if(CANx->CR & CAN_CR_STM_Msk)
{
CANx->CMD = (1 << CAN_CMD_SRR_Pos);
}
else
{
if(once == 0)
{
CANx->CMD = (1 << CAN_CMD_TXREQ_Pos);
}
else
{
CANx->CMD = (1 << CAN_CMD_TXREQ_Pos) | (1 << CAN_CMD_ABTTX_Pos);
}
}
}
/******************************************************************************************************************************************
* : CAN_TransmitRequest()
* : CAN
* : CAN_TypeDef * CANx CANCAN0
* uint32_t format CAN_FRAME_STD CAN_FRAME_EXT
* uint32_t id ID
* uint32_t once 使NAK
* :
* :
******************************************************************************************************************************************/
void CAN_TransmitRequest(CAN_TypeDef * CANx, uint32_t format, uint32_t id, uint32_t once)
{
if(format == CAN_FRAME_STD)
{
CANx->FRAME.INFO = (0 << CAN_INFO_FF_Pos) |
(1 << CAN_INFO_RTR_Pos) |
(0 << CAN_INFO_DLC_Pos);
CANx->FRAME.DATA[0] = id >> 3;
CANx->FRAME.DATA[1] = id << 5;
}
else //if(format == CAN_FRAME_EXT)
{
CANx->FRAME.INFO = (1 << CAN_INFO_FF_Pos) |
(1 << CAN_INFO_RTR_Pos) |
(0 << CAN_INFO_DLC_Pos);
CANx->FRAME.DATA[0] = id >> 21;
CANx->FRAME.DATA[1] = id >> 13;
CANx->FRAME.DATA[2] = id >> 5;
CANx->FRAME.DATA[3] = id << 3;
}
if(once == 0)
{
CANx->CMD = (1 << CAN_CMD_TXREQ_Pos);
}
else
{
CANx->CMD = (1 << CAN_CMD_TXREQ_Pos) | (1 << CAN_CMD_ABTTX_Pos);
}
}
/******************************************************************************************************************************************
* : CAN_Receive()
* : CAN
* : CAN_TypeDef * CANx CANCAN0
* CAN_RXMessage *msg
* :
* :
******************************************************************************************************************************************/
void CAN_Receive(CAN_TypeDef * CANx, CAN_RXMessage *msg)
{
uint32_t i;
msg->format = (CANx->FRAME.INFO & CAN_INFO_FF_Msk) >> CAN_INFO_FF_Pos;
msg->remote = (CANx->FRAME.INFO & CAN_INFO_RTR_Msk) >> CAN_INFO_RTR_Pos;
msg->size = (CANx->FRAME.INFO & CAN_INFO_DLC_Msk) >> CAN_INFO_DLC_Pos;
if(msg->format == CAN_FRAME_STD)
{
msg->id = (CANx->FRAME.DATA[0] << 3) | (CANx->FRAME.DATA[1] >> 5);
for(i = 0; i < msg->size; i++)
{
msg->data[i] = CANx->FRAME.DATA[i+2];
}
}
else //if(msg->format == CAN_FRAME_EXT)
{
msg->id = (CANx->FRAME.DATA[0] << 21) | (CANx->FRAME.DATA[1] << 13) | (CANx->FRAME.DATA[2] << 5) | (CANx->FRAME.DATA[3] >> 3);
for(i = 0; i < msg->size; i++)
{
msg->data[i] = CANx->FRAME.DATA[i+4];
}
}
CANx->CMD = (1 << CAN_CMD_RRB_Pos);
}
/******************************************************************************************************************************************
* : CAN_TXComplete()
* :
* : CAN_TypeDef * CANx CANCAN0
* : uint32_t 1 0
* : Abort
******************************************************************************************************************************************/
uint32_t CAN_TXComplete(CAN_TypeDef * CANx)
{
return (CANx->SR & CAN_SR_TXBR_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : CAN_TXSuccess()
* :
* : CAN_TypeDef * CANx CANCAN0
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t CAN_TXSuccess(CAN_TypeDef * CANx)
{
return (CANx->SR & CAN_SR_TXOK_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : CAN_AbortTransmit()
* :
* : CAN_TypeDef * CANx CANCAN0
* :
* :
******************************************************************************************************************************************/
void CAN_AbortTransmit(CAN_TypeDef * CANx)
{
CANx->CMD = (1 << CAN_CMD_ABTTX_Pos);
}
/******************************************************************************************************************************************
* : CAN_TXBufferReady()
* : TX Buffer
* : CAN_TypeDef * CANx CANCAN0
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t CAN_TXBufferReady(CAN_TypeDef * CANx)
{
return (CANx->SR & CAN_SR_TXBR_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : CAN_RXDataAvailable()
* : RX FIFO
* : CAN_TypeDef * CANx CANCAN0
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t CAN_RXDataAvailable(CAN_TypeDef * CANx)
{
return (CANx->SR & CAN_SR_RXDA_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : CAN_SetBaudrate()
* :
* : CAN_TypeDef * CANx CANCAN0
* uint32_t baudrate
* uint32_t CAN_bs1 CAN_BS1_1tqCAN_BS1_2tq... ... CAN_BS1_16tq
* uint32_t CAN_bs2 CAN_BS2_1tqCAN_BS2_2tq... ... CAN_BS2_8tq
* uint32_t CAN_sjw CAN_SJW_1tqCAN_SJW_2tqCAN_SJW_3tqCAN_SJW_4tq
* :
* : CAN_Close()CAN
******************************************************************************************************************************************/
void CAN_SetBaudrate(CAN_TypeDef * CANx, uint32_t baudrate, uint32_t CAN_bs1, uint32_t CAN_bs2, uint32_t CAN_sjw)
{
uint32_t brp = SystemCoreClock/2/baudrate/(1 + (CAN_bs1 + 1) + (CAN_bs2 + 1)) - 1;
CANx->BT1 = (0 << CAN_BT1_SAM_Pos) |
(CAN_bs1 << CAN_BT1_TSEG1_Pos) |
(CAN_bs2 << CAN_BT1_TSEG2_Pos);
CANx->BT0 = (CAN_sjw << CAN_BT0_SJW_Pos) |
((brp & 0x3F) << CAN_BT0_BRP_Pos);
CANx->BT2 = ((brp >> 6) << CAN_BT2_BRP_Pos);
}
/******************************************************************************************************************************************
* : CAN_SetFilter32b()
* : 132
* : CAN_TypeDef * CANx CANCAN0
* uint32_t filter CAN_FILTER_1CAN_FILTER_2...CAN_FILTER_16
* uint32_t check maskMessagecheck & mask == ID & maskMessage
* uint32_t mask
* :
* :
******************************************************************************************************************************************/
void CAN_SetFilter32b(CAN_TypeDef * CANx, uint32_t filter, uint32_t check, uint32_t mask)
{
CANx->AFM |= (1 << filter);
CANx->ACR[filter] = __REV(check << 3); // 高29位
CANx->AMR[filter] = __REV(~(mask << 3));
CANx->AFE |= (1 << filter);
}
/******************************************************************************************************************************************
* : CAN_SetFilter16b()
* : 216
* : CAN_TypeDef * CANx CANCAN0
* uint32_t filter CAN_FILTER_1CAN_FILTER_2...CAN_FILTER_16
* uint16_t check1 maskMessagecheck & mask == ID & maskMessage
* uint16_t mask1
* uint16_t check2
* uint16_t mask2
* :
* :
******************************************************************************************************************************************/
void CAN_SetFilter16b(CAN_TypeDef * CANx, uint32_t filter, uint16_t check1, uint16_t mask1, uint16_t check2, uint16_t mask2)
{
CANx->AFM &= ~(1 << filter);
CANx->ACR[filter] = __REV((check1 << 5) | (check2 << 21)); // 高11位
CANx->AMR[filter] = __REV(~((mask1 << 5) | (mask2 << 21)));
CANx->AFE |= (1 << filter);
}
/******************************************************************************************************************************************
* : CAN_INTEn()
* : 使
* : CAN_TypeDef * CANx CANCAN0
* uint32_t it interrupt type CAN_IT_RX_NOTEMPTYCAN_IT_RX_OVERFLOWCAN_IT_TX_EMPTYCAN_IT_ARBLOST
* CAN_IT_ERRCAN_IT_ERR_WARNCAN_IT_ERR_PASSCAN_IT_WAKEUP
* :
* :
******************************************************************************************************************************************/
void CAN_INTEn(CAN_TypeDef * CANx, uint32_t it)
{
CANx->IE |= it;
}
/******************************************************************************************************************************************
* : CAN_INTDis()
* :
* : CAN_TypeDef * CANx CANCAN0
* uint32_t it interrupt type CAN_IT_RX_NOTEMPTYCAN_IT_RX_OVERFLOWCAN_IT_TX_EMPTYCAN_IT_ARBLOST
* CAN_IT_ERRCAN_IT_ERR_WARNCAN_IT_ERR_PASSCAN_IT_WAKEUP
* :
* :
******************************************************************************************************************************************/
void CAN_INTDis(CAN_TypeDef * CANx, uint32_t it)
{
CANx->IE &= ~it;
}
/******************************************************************************************************************************************
* : CAN_INTClr()
* :
* : CAN_TypeDef * CANx CANCAN0
* uint32_t it interrupt type CAN_IT_RX_OVERFLOW
* :
* :
******************************************************************************************************************************************/
void CAN_INTClr(CAN_TypeDef * CANx, uint32_t it)
{
CANx->CMD = (1 << CAN_CMD_CLROV_Pos);
}
/******************************************************************************************************************************************
* : CAN_INTStat()
* :
* : CAN_TypeDef * CANx CANCAN0
* : uint32_t
* : CANx->IFISR
******************************************************************************************************************************************/
uint32_t CAN_INTStat(CAN_TypeDef * CANx)
{
return CANx->IF;
}

@ -0,0 +1,121 @@
#ifndef __SWM221_CAN_H__
#define __SWM221_CAN_H__
typedef struct {
uint8_t Mode; //CAN_MODE_NORMAL、CAN_MODE_LISTEN、CAN_MODE_SELFTEST
uint8_t CAN_bs1; //CAN_BS1_1tq、CAN_BS1_2tq、... ... 、CAN_BS1_16tq
uint8_t CAN_bs2; //CAN_BS2_1tq、CAN_BS2_2tq、... ... 、CAN_BS2_8tq
uint8_t CAN_sjw; //CAN_SJW_1tq、CAN_SJW_2tq、CAN_SJW_3tq、CAN_SJW_4tq
uint32_t Baudrate; //波特率即位传输速率取值1--1000000
uint8_t RXNotEmptyIEn; //接收FIFO非空有数据可读
uint8_t ArbitrLostIEn; //控制器丢失仲裁变成接收方
uint8_t ErrPassiveIEn; //接收/发送错误计数值达到127
} CAN_InitStructure;
#define CAN_MODE_NORMAL 0 //常规模式
#define CAN_MODE_LISTEN 1 //监听模式
#define CAN_MODE_SELFTEST 2 //自测模式
#define CAN_BS1_1tq 0
#define CAN_BS1_2tq 1
#define CAN_BS1_3tq 2
#define CAN_BS1_4tq 3
#define CAN_BS1_5tq 4
#define CAN_BS1_6tq 5
#define CAN_BS1_7tq 6
#define CAN_BS1_8tq 7
#define CAN_BS1_9tq 8
#define CAN_BS1_10tq 9
#define CAN_BS1_11tq 10
#define CAN_BS1_12tq 11
#define CAN_BS1_13tq 12
#define CAN_BS1_14tq 13
#define CAN_BS1_15tq 14
#define CAN_BS1_16tq 15
#define CAN_BS2_1tq 0
#define CAN_BS2_2tq 1
#define CAN_BS2_3tq 2
#define CAN_BS2_4tq 3
#define CAN_BS2_5tq 4
#define CAN_BS2_6tq 5
#define CAN_BS2_7tq 6
#define CAN_BS2_8tq 7
#define CAN_SJW_1tq 0
#define CAN_SJW_2tq 1
#define CAN_SJW_3tq 2
#define CAN_SJW_4tq 3
#define CAN_FRAME_STD 0
#define CAN_FRAME_EXT 1
#define CAN_FILTER_1 0
#define CAN_FILTER_2 1
#define CAN_FILTER_3 2
#define CAN_FILTER_4 3
#define CAN_FILTER_5 4
#define CAN_FILTER_6 5
#define CAN_FILTER_7 6
#define CAN_FILTER_8 7
#define CAN_FILTER_9 8
#define CAN_FILTER_10 9
#define CAN_FILTER_11 10
#define CAN_FILTER_12 11
#define CAN_FILTER_13 12
#define CAN_FILTER_14 13
#define CAN_FILTER_15 14
#define CAN_FILTER_16 15
/* Interrupt Type */
#define CAN_IT_RX_NOTEMPTY (0x01 << 0) //RX Buffer Not Empty
#define CAN_IT_RX_OVERFLOW (0x01 << 3) //RX Buffer Overflow
#define CAN_IT_TX_EMPTY (0x01 << 1) //TX Buffer Empty
#define CAN_IT_ARBLOST (0x01 << 6) //Arbitration lost
#define CAN_IT_ERR (0x01 << 7)
#define CAN_IT_ERR_WARN (0x01 << 2) //TXERR/RXERR计数值达到Error Warning Limit
#define CAN_IT_ERR_PASS (0x01 << 5) //TXERR/RXERR计数值达到127
#define CAN_IT_WAKEUP (0x01 << 4)
typedef struct {
uint32_t id; //消息ID
uint8_t format; //帧格式CAN_FRAME_STD(11bit ID)、CAN_FRAME_EXT(29bit ID)
uint8_t remote; //消息是否为远程帧
uint8_t size; //接收到的数据个数
uint8_t data[8]; //接收到的数据
} CAN_RXMessage;
void CAN_Init(CAN_TypeDef * CANx, CAN_InitStructure * initStruct);
void CAN_Open(CAN_TypeDef * CANx);
void CAN_Close(CAN_TypeDef * CANx);
void CAN_Transmit(CAN_TypeDef * CANx, uint32_t format, uint32_t id, uint8_t data[], uint32_t size, uint32_t once);
void CAN_TransmitRequest(CAN_TypeDef * CANx, uint32_t format, uint32_t id, uint32_t once);
void CAN_Receive(CAN_TypeDef * CANx, CAN_RXMessage *msg);
uint32_t CAN_TXComplete(CAN_TypeDef * CANx);
uint32_t CAN_TXSuccess(CAN_TypeDef * CANx);
void CAN_AbortTransmit(CAN_TypeDef * CANx);
uint32_t CAN_TXBufferReady(CAN_TypeDef * CANx);
uint32_t CAN_RXDataAvailable(CAN_TypeDef * CANx);
void CAN_SetBaudrate(CAN_TypeDef * CANx, uint32_t baudrate, uint32_t CAN_bs1, uint32_t CAN_bs2, uint32_t CAN_sjw);
void CAN_SetFilter32b(CAN_TypeDef * CANx, uint32_t filter, uint32_t check, uint32_t mask);
void CAN_SetFilter16b(CAN_TypeDef * CANx, uint32_t filter, uint16_t check1, uint16_t mask1, uint16_t check2, uint16_t mask2);
void CAN_INTEn(CAN_TypeDef * CANx, uint32_t it);
void CAN_INTDis(CAN_TypeDef * CANx, uint32_t it);
void CAN_INTClr(CAN_TypeDef * CANx, uint32_t it);
uint32_t CAN_INTStat(CAN_TypeDef * CANx);
#endif //__SWM221_CAN_H__

@ -0,0 +1,67 @@
/******************************************************************************************************************************************
* : SWM341_crc.c
* : SWM341CRC
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM221.h"
#include "SWM221_crc.h"
/******************************************************************************************************************************************
* : CRC_Init()
* : CRC
* : CRC_TypeDef * CRCx CRCCRC
* CRC_InitStructure * initStruct CRC
* :
* :
******************************************************************************************************************************************/
void CRC_Init(CRC_TypeDef * CRCx, CRC_InitStructure * initStruct)
{
switch((uint32_t)CRCx)
{
case ((uint32_t)CRC):
SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_CRC_Pos);
break;
}
CRCx->INIVAL = initStruct->init_crc;
CRCx->CR = (1 << CRC_CR_EN_Pos) |
(initStruct->Poly << CRC_CR_POLY_Pos) |
(initStruct->in_width << CRC_CR_IBIT_Pos) |
(initStruct->in_rev << CRC_CR_IREV_Pos) |
(initStruct->in_not << CRC_CR_INOT_Pos) |
(initStruct->out_rev << CRC_CR_OREV_Pos) |
(initStruct->out_not << CRC_CR_ONOT_Pos);
}
/******************************************************************************************************************************************
* : CRC_SetInitVal()
* : CRC
* : CRC_TypeDef * CRCx CRCCRC
* uint32_t init_crc CRC
* :
* :
******************************************************************************************************************************************/
void CRC_SetInitVal(CRC_TypeDef * CRCx, uint32_t init_crc)
{
CRCx->INIVAL = init_crc;
CRCx->CR |= (1 << CRC_CR_EN_Pos);
}

@ -0,0 +1,59 @@
#ifndef __SWM221_CRC_H__
#define __SWM221_CRC_H__
typedef struct {
uint32_t init_crc; // 初始值
uint8_t Poly; // CRC多项式可取值CRC_POLY_11021、CRC_POLY_107、CRC_POLY_18005、CRC_POLY_104C11DB7
uint8_t in_width; // 输入数据宽度可取值CRC_WIDTH_32、CRC_WIDTH_16、CRC_WIDTH_8
uint8_t in_rev; // 输入数据翻转可取值CRC_REV_NOT、CRC_REV_ALL、CRC_REV_IN_BYTE、CRC_REV_BYTE
bool in_not; // 输入数据取反
uint8_t out_rev; // 输出结果翻转可取值CRC_REV_NOT、CRC_REV_ALL、CRC_REV_IN_BYTE、CRC_REV_BYTE
bool out_not; // 输出结果取反
} CRC_InitStructure;
#define CRC_POLY_11021 0 // x^16+x^12+x^5+1
#define CRC_POLY_107 1 // x^8+x^2+x+1
#define CRC_POLY_18005 2 // x^16+x^15+x^2+1
#define CRC_POLY_104C11DB7 3 // x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1
#define CRC_WIDTH_32 0
#define CRC_WIDTH_16 1
#define CRC_WIDTH_8 2
#define CRC_REV_NOT 0 // bit顺序不变
#define CRC_REV_ALL 1 // bit顺序完全翻转
#define CRC_REV_IN_BYTE 2 // bit顺序字节内翻转
#define CRC_REV_BYTE 3 // 仅字节顺序翻转
void CRC_Init(CRC_TypeDef * CRCx, CRC_InitStructure * initStruct);
void CRC_SetInitVal(CRC_TypeDef * CRCx, uint32_t init_crc);
/******************************************************************************************************************************************
* : CRC_Write()
* : CRC
* : uint32_t data
* :
* :
******************************************************************************************************************************************/
static __INLINE void CRC_Write(uint32_t data)
{
CRC->DATAIN = data;
}
/******************************************************************************************************************************************
* : CRC_Result()
* : CRC
* :
* : uint32_t CRC
* :
******************************************************************************************************************************************/
static __INLINE uint32_t CRC_Result(void)
{
return CRC->RESULT;
}
#endif //__SWM221_CRC_H__

@ -0,0 +1,40 @@
/******************************************************************************************************************************************
* : SWM221_div.c
* : SWM221DIV
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.0.0 2016130
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM221.h"
#include "SWM221_div.h"
/******************************************************************************************************************************************
* : DIV_Init()
* :
* : DIV_TypeDef * DIVx DIV
* :
* :
******************************************************************************************************************************************/
void DIV_Init(DIV_TypeDef * DIVx)
{
switch((uint32_t)DIVx)
{
case ((uint32_t)DIV):
SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_DIV_Pos);
break;
}
}

@ -0,0 +1,129 @@
#ifndef __SWM221_DIV_H__
#define __SWM221_DIV_H__
void DIV_Init(DIV_TypeDef * DIVx);
/******************************************************************************************************************************************
* : DIV_UDiv()
* : 使
* : uint32_t dividend
* uint32_t divisor
* :
* :
******************************************************************************************************************************************/
static __INLINE void DIV_UDiv(uint32_t dividend, uint32_t divisor)
{
DIV->DIVIDEND = dividend;
DIV->DIVISOR = divisor;
DIV->CR = (1 << DIV_CR_DIVSIGN_Pos) | (1 << DIV_CR_DIVGO_Pos);
}
/******************************************************************************************************************************************
* : DIV_SDiv()
* : 使
* : int32_t dividend
* int32_t divisor
* :
* :
******************************************************************************************************************************************/
static __INLINE void DIV_SDiv(int32_t dividend, int32_t divisor)
{
DIV->DIVIDEND = dividend;
DIV->DIVISOR = divisor;
DIV->CR = (0 << DIV_CR_DIVSIGN_Pos) | (1 << DIV_CR_DIVGO_Pos);
}
/******************************************************************************************************************************************
* : DIV_Div_IsBusy()
* :
* :
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
static __INLINE uint32_t DIV_Div_IsBusy(void)
{
return (DIV->SR & DIV_SR_DIVBUSY_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : DIV_UDiv_Result()
* :
* :
* : uint32_t *quotient
* uint32_t *remainder
* :
******************************************************************************************************************************************/
static __INLINE void DIV_UDiv_Result(uint32_t *quotient, uint32_t *remainder)
{
*quotient = DIV->QUO;
*remainder = DIV->REMAIN;
}
/******************************************************************************************************************************************
* : DIV_SDiv_Result()
* :
* :
* : int32_t *quotient
* int32_t *remainder
* :
******************************************************************************************************************************************/
static __INLINE void DIV_SDiv_Result(int32_t *quotient, int32_t *remainder)
{
*quotient = DIV->QUO & 0x7FFFFFFF;
if(DIV->QUO & (1u << 31)) *quotient = 0 - *quotient;
*remainder = DIV->REMAIN & 0x7FFFFFFF;
if(DIV->REMAIN & (1u << 31)) *remainder = 0 - *remainder;
}
/******************************************************************************************************************************************
* : DIV_Root()
* : 使
* : uint32_t radicand
* uint32_t calcu_frac 0 16 1 16+16
* :
* :
******************************************************************************************************************************************/
static __INLINE void DIV_Root(uint32_t radicand, uint32_t calcu_fractional)
{
DIV->RADICAND = radicand;
DIV->CR = (1 << DIV_CR_ROOTGO_Pos) | (calcu_fractional << DIV_CR_ROOTMOD_Pos);
}
/******************************************************************************************************************************************
* : DIV_Root_IsBusy()
* :
* :
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
static __INLINE uint32_t DIV_Root_IsBusy(void)
{
return (DIV->SR & DIV_SR_ROOTBUSY_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : DIV_Root_Result()
* :
* :
* : uint32_t
* :
******************************************************************************************************************************************/
static __INLINE uint32_t DIV_Root_Result(void)
{
if(DIV->CR & DIV_CR_ROOTMOD_Msk)
{
return DIV->ROOT;
}
else
{
return DIV->ROOT >> 16;
}
}
#endif //__SWM221_DIV_H__

@ -0,0 +1,159 @@
/******************************************************************************************************************************************
* : SWM342_dma.c
* : SWM342DMA
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.0.0 2016130
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM221.h"
#include "SWM221_dma.h"
/******************************************************************************************************************************************
* : DMA_CH_Init()
* : DMA
* : uint32_t chn DMA_CH0DMA_CH1
* DMA_InitStructure * initStruct DMA
* :
* :
******************************************************************************************************************************************/
void DMA_CH_Init(uint32_t chn, DMA_InitStructure * initStruct)
{
DMA_CH_Close(chn); //关闭后配置
DMA->CH[chn].CR = (initStruct->Mode << DMA_CR_CIRC_Pos) |
(initStruct->Unit << DMA_CR_MSIZ_Pos) |
(initStruct->Unit << DMA_CR_PSIZ_Pos) |
(initStruct->MemoryAddrInc << DMA_CR_MINC_Pos) |
(initStruct->PeripheralAddrInc << DMA_CR_PINC_Pos) |
(initStruct->Priority << DMA_CR_PL_Pos);
DMA->CH[chn].NDT = ( initStruct->Count << DMA_NDT_LEN_Pos) |
((initStruct->Count / 2) << DMA_NDT_HALF_Pos);
DMA->CH[chn].MAR = initStruct->MemoryAddr;
DMA->CH[chn].PAR = initStruct->PeripheralAddr;
switch(initStruct->Handshake & DMA_HS_MSK)
{
case DMA_HS_NO:
DMA->CH[chn].MUX = 0;
DMA->CH[chn].CR |= DMA_CR_DIR_Msk | DMA_CR_MEM2MEM_Msk;
break;
case DMA_HS_MRD:
DMA->CH[chn].MUX = ((initStruct->Handshake & 0xF) << DMA_MUX_MRDHSSIG_Pos) | (1 << DMA_MUX_MRDHSEN_Pos);
DMA->CH[chn].CR |= DMA_CR_DIR_Msk;
break;
case DMA_HS_MWR:
DMA->CH[chn].MUX = ((initStruct->Handshake & 0xF) << DMA_MUX_MWRHSSIG_Pos) | (1 << DMA_MUX_MWRHSEN_Pos);
DMA->CH[chn].CR &= ~DMA_CR_DIR_Msk;
break;
case DMA_HS_EXT | DMA_HS_MRD:
DMA->CH[chn].MUX = ((initStruct->Handshake & 0xF) << DMA_MUX_EXTHSSIG_Pos) | (1 << DMA_MUX_EXTHSEN_Pos);
DMA->CH[chn].CR |= DMA_CR_DIR_Msk;
break;
case DMA_HS_EXT | DMA_HS_MWR:
DMA->CH[chn].MUX = ((initStruct->Handshake & 0xF) << DMA_MUX_EXTHSSIG_Pos) | (1 << DMA_MUX_EXTHSEN_Pos);
DMA->CH[chn].CR &= ~DMA_CR_DIR_Msk;
break;
}
DMA_CH_INTClr(chn, initStruct->INTEn);
DMA_CH_INTEn(chn, initStruct->INTEn);
if(initStruct->INTEn) NVIC_EnableIRQ(GPIOB1_GPIOA9_DMA_IRQn);
}
/******************************************************************************************************************************************
* : DMA_CH_Open()
* : DMA
* : uint32_t chn DMA_CH0DMA_CH1
* :
* :
******************************************************************************************************************************************/
void DMA_CH_Open(uint32_t chn)
{
DMA->CH[chn].CR |= DMA_CR_EN_Msk;
}
/******************************************************************************************************************************************
* : DMA_CH_Close()
* : DMA
* : uint32_t chn DMA_CH0DMA_CH1
* :
* :
******************************************************************************************************************************************/
void DMA_CH_Close(uint32_t chn)
{
DMA->CH[chn].CR &= ~DMA_CR_EN_Msk;
}
/******************************************************************************************************************************************
* : DMA_CH_INTEn()
* : DMA使
* : uint32_t chn DMA_CH0DMA_CH1
* uint32_t it interrupt type DMA_IT_DONEDMA_IT_HALFDMA_IT_ERROR
* :
* :
******************************************************************************************************************************************/
void DMA_CH_INTEn(uint32_t chn, uint32_t it)
{
DMA->CH[chn].CR |= it;
}
/******************************************************************************************************************************************
* : DMA_CH_INTDis()
* : DMA
* : uint32_t chn DMA_CH0DMA_CH1
* uint32_t it interrupt type DMA_IT_DONEDMA_IT_HALFDMA_IT_ERROR
* :
* :
******************************************************************************************************************************************/
void DMA_CH_INTDis(uint32_t chn, uint32_t it)
{
DMA->CH[chn].CR &= ~it;
}
/******************************************************************************************************************************************
* : DMA_CH_INTClr()
* : DMA
* : uint32_t chn DMA_CH0DMA_CH1
* uint32_t it interrupt type DMA_IT_DONEDMA_IT_HALFDMA_IT_ERROR
* :
* :
******************************************************************************************************************************************/
void DMA_CH_INTClr(uint32_t chn, uint32_t it)
{
DMA->IFC = (it << (chn * 4));
}
/******************************************************************************************************************************************
* : DMA_CH_INTStat()
* : DMA
* : uint32_t chn DMA_CH0DMA_CH1
* uint32_t it interrupt type DMA_IT_DONEDMA_IT_HALFDMA_IT_ERROR
* : uint32_t 0 0
* :
******************************************************************************************************************************************/
uint32_t DMA_CH_INTStat(uint32_t chn, uint32_t it)
{
return DMA->IF & (it << (chn * 4));
}

@ -0,0 +1,128 @@
#ifndef __SWM221_DMA_H__
#define __SWM221_DMA_H__
typedef struct {
uint8_t Mode; //DMA_MODE_SINGLE、DMA_MODE_CIRCLE
uint8_t Unit; //DMA_UNIT_BYTE、DMA_UNIT_HALFWORD、DMA_UNIT_WORD
uint32_t Count; //传输 Unit 个数最大取值0xFFFF
uint32_t MemoryAddr;
uint32_t PeripheralAddr;
uint8_t MemoryAddrInc; //0 地址固定 1 地址递增
uint8_t PeripheralAddrInc;
uint8_t Handshake; //传输握手信号DMA_HS_NO、DMA_CH0_UART0TX、DMA_CH0_SPI0TX、... ...
uint8_t Priority; //DMA_PRI_HIGHEST、DMA_PRI_VERY_HIGH、...、DMA_PRI_LOWEST
uint32_t INTEn; //中断使能,有效值有 DMA_IT_DONE、DMA_IT_HALF、DMA_IT_ERROR 及其“或”
} DMA_InitStructure;
#define DMA_CH0 0
#define DMA_CH1 1
#define DMA_MODE_SINGLE 0 // 单次模式,传输完成后停止
#define DMA_MODE_CIRCLE 1 // 环形模式,传输完成后从头执行下一轮传输
#define DMA_UNIT_BYTE 0
#define DMA_UNIT_HALFWORD 1
#define DMA_UNIT_WORD 2
#define DMA_PRI_HIGHEST 0
#define DMA_PRI_VERY_HIGH 2
#define DMA_PRI_HIGH 4
#define DMA_PRI_LOW 11
#define DMA_PRI_VERY_LOW 13
#define DMA_PRI_LOWEST 15
#define DMA_HS_NO (0 << 4) // 无握手信号,适用于 Memory to Memory 传输PeripheralAddr 用作目的地址
#define DMA_HS_MRD (1 << 4) // memory read handshake适用于 Memory to Peripheral 传输
#define DMA_HS_MWR (2 << 4) // memory write handshake适用于 Peripheral to Memory 传输
#define DMA_HS_EXT (4 << 4) // external handshake
#define DMA_HS_MSK (7 << 4)
// memory read handshake signal
#define DMA_CH0_UART0TX (0 | DMA_HS_MRD)
#define DMA_CH0_SPI0TX (1 | DMA_HS_MRD)
#define DMA_CH0_QSPI0TX (2 | DMA_HS_MRD)
#define DMA_CH1_USART0TX (0 | DMA_HS_MRD)
#define DMA_CH1_UART1TX (1 | DMA_HS_MRD)
#define DMA_CH1_MPUTX (2 | DMA_HS_MRD)
// memory write handshake signal
#define DMA_CH0_USART0RX (0 | DMA_HS_MWR)
#define DMA_CH0_UART1RX (1 | DMA_HS_MWR)
#define DMA_CH0_MPURX (2 | DMA_HS_MWR)
#define DMA_CH0_ADC0SEQ1 (3 | DMA_HS_MWR)
#define DMA_CH1_UART0RX (0 | DMA_HS_MWR)
#define DMA_CH1_SPI0RX (1 | DMA_HS_MWR)
#define DMA_CH1_QSPI0RX (2 | DMA_HS_MWR)
#define DMA_CH1_ADC1SEQ1 (3 | DMA_HS_MWR)
// 外部握手信号
#define DMA_EXMRD_TIMR0 (0 | DMA_HS_MRD | DMA_HS_EXT)
#define DMA_EXMRD_TIMR1 (1 | DMA_HS_MRD | DMA_HS_EXT)
#define DMA_EXMRD_TIMR2 (2 | DMA_HS_MRD | DMA_HS_EXT)
#define DMA_EXMRD_TIMR3 (3 | DMA_HS_MRD | DMA_HS_EXT)
#define DMA_EXMRD_TRIG0 (4 | DMA_HS_MRD | DMA_HS_EXT) // DMA_TRIG0引脚
#define DMA_EXMRD_TRIG1 (5 | DMA_HS_MRD | DMA_HS_EXT) // DMA_TRIG1引脚
#define DMA_EXMWR_TIMR0 (0 | DMA_HS_MWR | DMA_HS_EXT)
#define DMA_EXMWR_TIMR1 (1 | DMA_HS_MWR | DMA_HS_EXT)
#define DMA_EXMWR_TIMR2 (2 | DMA_HS_MWR | DMA_HS_EXT)
#define DMA_EXMWR_TIMR3 (3 | DMA_HS_MWR | DMA_HS_EXT)
#define DMA_EXMWR_TRIG0 (4 | DMA_HS_MWR | DMA_HS_EXT)
#define DMA_EXMWR_TRIG1 (5 | DMA_HS_MWR | DMA_HS_EXT)
/* Interrupt Type */
#define DMA_IT_DONE (1 << 1) //Transfer Done
#define DMA_IT_HALF (1 << 2) //Transfer Half
#define DMA_IT_ERROR (1 << 3) //Transfer Error
void DMA_CH_Init(uint32_t chn, DMA_InitStructure * initStruct); //DMA通道配置
void DMA_CH_Open(uint32_t chn);
void DMA_CH_Close(uint32_t chn);
static inline void DMA_CH_SetCount(uint32_t chn, uint32_t count)
{
DMA->CH[chn].NDT = ( count << DMA_NDT_LEN_Pos) |
((count / 2) << DMA_NDT_HALF_Pos);
}
static inline uint32_t DMA_CH_GetRemaining(uint32_t chn)
{
return (DMA->CH[chn].NDT & DMA_NDT_LEN_Msk);
}
static inline void DMA_CH_SetAddrAndCount(uint32_t chn, uint32_t addr, uint32_t count)
{
DMA->CH[chn].MAR = addr;
DMA_CH_SetCount(chn, count);
}
void DMA_CH_INTEn(uint32_t chn, uint32_t it); //DMA中断使能
void DMA_CH_INTDis(uint32_t chn, uint32_t it); //DMA中断禁止
void DMA_CH_INTClr(uint32_t chn, uint32_t it); //DMA中断标志清除
uint32_t DMA_CH_INTStat(uint32_t chn, uint32_t it); //DMA中断状态查询
#endif //__SWM221_DMA_H__

@ -0,0 +1,131 @@
/******************************************************************************************************************************************
* : SWM221_exti.c
* : SWM221
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.0.0 2016130
* :
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM221.h"
#include "SWM221_exti.h"
/******************************************************************************************************************************************
* : EXTI_Init()
* :
* : GPIO_TypeDef * GPIOx GPIOGPIOAGPIOBGPIOC
* uint32_t n GPIOPIN0PIN1PIN2... ... PIN14PIN15
* uint32_t mode EXTI_FALL_EDGEEXTI_RISE_EDGEEXTI_BOTH_EDGEEXTI_LOW_LEVELEXTI_HIGH_LEVEL
* :
* :
******************************************************************************************************************************************/
void EXTI_Init(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t mode)
{
EXTI_Close(GPIOx, n); //配置关键寄存器前先关闭
if(mode & 0x10)
{
GPIOx->INTLVLTRG |= (0x01 << n); //电平触发
if(mode & 0x01)
GPIOx->INTRISEEN |= (0x01 << n); //高电平触发
else
GPIOx->INTRISEEN &= ~(0x01 << n); //低电平触发
}
else
{
GPIOx->INTLVLTRG &= ~(0x01 << n); //边沿触发
if(mode & 0x02)
{
GPIOx->INTBE |= (0x01 << n); //双边沿触发
}
else
{
GPIOx->INTBE &= ~(0x01 << n); //单边沿触发
if(mode & 0x01)
GPIOx->INTRISEEN |= (0x01 << n); //上升沿触发
else
GPIOx->INTRISEEN &= ~(0x01 << n); //下降沿触发
}
}
GPIOx->INTCLR = (1 << n); //清除掉因为模式配置可能产生的中断
}
/******************************************************************************************************************************************
* : EXTI_Open()
* : 使
* : GPIO_TypeDef * GPIOx GPIOGPIOAGPIOBGPIOC
* uint32_t n GPIOPIN0PIN1PIN2... ... PIN14PIN15
* :
* :
******************************************************************************************************************************************/
void EXTI_Open(GPIO_TypeDef * GPIOx, uint32_t n)
{
GPIOx->INTEN |= (0x01 << n);
}
/******************************************************************************************************************************************
* : EXTI_Close()
* :
* : GPIO_TypeDef * GPIOx GPIOGPIOAGPIOBGPIOC
* uint32_t n GPIOPIN0PIN1PIN2... ... PIN14PIN15
* :
* :
******************************************************************************************************************************************/
void EXTI_Close(GPIO_TypeDef * GPIOx, uint32_t n)
{
GPIOx->INTEN &= ~(0x01 << n);
}
/******************************************************************************************************************************************
* : EXTI_State()
* :
* : GPIO_TypeDef * GPIOx GPIOGPIOAGPIOBGPIOC
* uint32_t n GPIOPIN0PIN1PIN2... ... PIN14PIN15
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t EXTI_State(GPIO_TypeDef * GPIOx, uint32_t n)
{
return (GPIOx->INTSTAT >> n) & 0x01;
}
/******************************************************************************************************************************************
* : EXTI_RawState()
* : //
* : GPIO_TypeDef * GPIOx GPIOGPIOAGPIOBGPIOC
* uint32_t n GPIOPIN0PIN1PIN2... ... PIN14PIN15
* : uint32_t 1 / 0 /
* :
******************************************************************************************************************************************/
uint32_t EXTI_RawState(GPIO_TypeDef * GPIOx, uint32_t n)
{
return (GPIOx->INTRAWSTAT >> n) & 0x01;
}
/******************************************************************************************************************************************
* : EXTI_Clear()
* :
* : GPIO_TypeDef * GPIOx GPIOGPIOAGPIOBGPIOC
* uint32_t n GPIOPIN0PIN1PIN2... ... PIN14PIN15
* :
* : 沿
******************************************************************************************************************************************/
void EXTI_Clear(GPIO_TypeDef * GPIOx, uint32_t n)
{
GPIOx->INTCLR = (0x01 << n);
}

@ -0,0 +1,20 @@
#ifndef __SWM221_EXTI_H__
#define __SWM221_EXTI_H__
void EXTI_Init(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t mode); //指定引脚外部中断初始化
void EXTI_Open(GPIO_TypeDef * GPIOx, uint32_t n); //指定引脚外部中断打开(即使能)
void EXTI_Close(GPIO_TypeDef * GPIOx, uint32_t n); //指定引脚外部中断关闭(即禁能)
uint32_t EXTI_State(GPIO_TypeDef * GPIOx, uint32_t n); //指定引脚是否触发了中断
uint32_t EXTI_RawState(GPIO_TypeDef * GPIOx, uint32_t n); //指定引脚是否满足过/了中断触发条件,当此中断关闭时可通过调用此函数以查询的方式检测引脚上是否满足过/了中断触发条件
void EXTI_Clear(GPIO_TypeDef * GPIOx, uint32_t n); //指定引脚外部中断清除(即清除中断标志,以免再次进入此中断)
#define EXTI_FALL_EDGE 0x00 //下降沿触发中断
#define EXTI_RISE_EDGE 0x01 //上升沿触发中断
#define EXTI_BOTH_EDGE 0x02 //双边沿触发中断
#define EXTI_LOW_LEVEL 0x10 //低电平触发中断
#define EXTI_HIGH_LEVEL 0x11 //高电平触发中断
#endif //__SWM221_EXTI_H__

@ -0,0 +1,166 @@
/******************************************************************************************************************************************
* : SWM221_flash.c
* : 使IAPFlashEEPROM
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.0.0 2016130
* :
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM221.h"
#include "SWM221_flash.h"
typedef int (*IAP_Flash_Param_t)(uint32_t param, uint32_t flag);
typedef int (*IAP_Flash_Erase_t)(uint32_t sector, uint32_t flag);
typedef int (*IAP_Flash_Write_t)(uint32_t flash_addr, uint32_t ram_addr, uint32_t count, uint32_t flag);
IAP_Flash_Erase_t IAP_Flash_Erase = (IAP_Flash_Erase_t)0x01000401;
IAP_Flash_Write_t IAP_Flash_Write = (IAP_Flash_Write_t)0x01000461;
IAP_Flash_Param_t IAP_Flash_Param = (IAP_Flash_Param_t)0x010004D1;
/******************************************************************************************************************************************
* : FLASH_Erase()
* : Flash
* : uint32_t addr 512 Byte
* : uint32_t FLASH_RES_OKFLASH_RES_TOFLASH_RES_ERR
* :
******************************************************************************************************************************************/
uint32_t FLASH_Erase(uint32_t addr)
{
__disable_irq();
IAP_Flash_Erase(addr / 0x200, 0x0B11FFAC);
Cache_Clear();
__enable_irq();
return FLASH_RES_OK;
}
/******************************************************************************************************************************************
* : FLASH_Write()
* : Flash
* : uint32_t addr
* uint32_t buff[]
* uint32_t count 22
* : uint32_t FLASH_RES_OKFLASH_RES_TOFLASH_RES_ERR
* : 22
******************************************************************************************************************************************/
uint32_t FLASH_Write(uint32_t addr, uint32_t buff[], uint32_t count)
{
__disable_irq();
IAP_Flash_Write(addr, (uint32_t)buff, count/2, 0x0B11FFAC);
Cache_Clear();
__enable_irq();
return FLASH_RES_OK;
}
/******************************************************************************************************************************************
* : Flash_Param_at_xMHz()
* : FlashxMHz
* : uint32_t x MHz
* :
* :
******************************************************************************************************************************************/
void Flash_Param_at_xMHz(uint32_t x)
{
__disable_irq();
IAP_Flash_Param(1000 / x, 0x0B11FFAC);
__enable_irq();
}
#if defined ( __CC_ARM ) || defined (__ARMCC_VERSION)
/* Code_Cache_Clear 中数据是此函数编译生成的指令
__asm void Cache_Clear(void)
{
NOP
NOP
NOP
NOP
MOVS R0, #0x40 // 0x40045000
LSLS R0, R0, #8
ADDS R0, R0, #0x04
LSLS R0, R0, #8
ADDS R0, R0, #0x50
LSLS R0, R0, #8
LDR R1,[R0, #0xC]
MOVS R2, #1
LSLS R2, R2, #31
ORRS R1, R1, R2
STR R1,[R0, #0xC]
NOP
NOP
NOP
NOP
BX LR
}
*/
uint16_t Code_Cache_Clear[] = {
0xBF00, 0xBF00, 0xBF00, 0xBF00, 0x2040, 0x0200, 0x1D00, 0x0200,
0x3050, 0x0200, 0x68C1, 0x2201, 0x07D2, 0x4311, 0x60C1, 0xBF00,
0xBF00, 0xBF00, 0xBF00, 0x4770,
};
#if defined ( __CC_ARM )
__asm void Cache_Clear(void) // AC5
{
IMPORT Code_Cache_Clear
PUSH {LR}
NOP
LDR R0,=Code_Cache_Clear
ADDS R0, R0, #1
NOP
BLX R0
POP {R0}
BX R0
}
#else
void Cache_Clear(void) // AC6
{
__asm(
"PUSH {LR}\n"
"NOP\n"
"LDR R0,=Code_Cache_Clear\n"
"ADDS R0, R0, #1\n"
"NOP\n"
"BLX R0\n"
"POP {R0}\n"
"BX R0\n");
}
#endif
#elif defined ( __ICCARM__ )
__ramfunc void Cache_Clear(void)
{
__NOP(); __NOP(); __NOP(); __NOP();
FMC->CACHE |= FMC_CACHE_CCLR_Msk; // Cache Clear
__NOP(); __NOP(); __NOP(); __NOP();
}
#endif

@ -0,0 +1,19 @@
#ifndef __SWM221_FLASH_H__
#define __SWM221_FLASH_H__
uint32_t FLASH_Erase(uint32_t addr);
uint32_t FLASH_Write(uint32_t addr, uint32_t buff[], uint32_t cnt);
void Flash_Param_at_xMHz(uint32_t x);
void Cache_Clear(void);
#define FLASH_SECTOR_SIZE 512
#define FLASH_RES_OK 0
#define FLASH_RES_TO 1 //Timeout
#define FLASH_RES_ERR 2
#endif //__SWM221_FLASH_H__

@ -0,0 +1,263 @@
/******************************************************************************************************************************************
* : SWM221_gpio.c
* : SWM221
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.0.0 2016130
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM221.h"
#include "SWM221_gpio.h"
/******************************************************************************************************************************************
* : GPIO_Init()
* :
* : GPIO_TypeDef * GPIOx GPIOGPIOAGPIOBGPIOC
* uint32_t n GPIOPIN0PIN1PIN2... ... PIN14PIN15
* uint32_t dir 0 1
* uint32_t pull_up 使
* uint32_t pull_down 使
* uint32_t open_drain 使
* :
* :
******************************************************************************************************************************************/
void GPIO_Init(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, uint32_t pull_down, uint32_t open_drain)
{
PORT_TypeDef * PORTx = PORTA;
switch((uint32_t)GPIOx)
{
case ((uint32_t)GPIOA):
SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_GPIOA_Pos);
PORTx = PORTA;
break;
case ((uint32_t)GPIOB):
SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_GPIOB_Pos);
PORTx = PORTB;
break;
case ((uint32_t)GPIOC):
SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_GPIOC_Pos);
PORTx = PORTC;
break;
}
PORT_Init(PORTx, n, 0, 1); //PORTx.PINn引脚配置为GPIO功能数字输入开启
if(dir == 1)
{
GPIOx->DIR |= (0x01 << n);
}
else
{
GPIOx->DIR &= ~(0x01 << n);
}
if(pull_up == 1) PORTx->PULLU |= (1 << n);
else PORTx->PULLU &= ~(1 << n);
if(pull_down == 1) PORTx->PULLD |= (1 << n);
else PORTx->PULLD &= ~(1 << n);
if(open_drain == 1) PORTx->OPEND |= (1 << n);
else PORTx->OPEND &= ~(1 << n);
}
/******************************************************************************************************************************************
* : GPIO_SetBit()
* :
* : GPIO_TypeDef * GPIOx GPIOGPIOAGPIOBGPIOC
* uint32_t n GPIOPIN0PIN1PIN2... ... PIN14PIN15
* :
* :
******************************************************************************************************************************************/
void GPIO_SetBit(GPIO_TypeDef * GPIOx, uint32_t n)
{
*(&GPIOx->DATAPIN0 + n) = 1;
}
/******************************************************************************************************************************************
* : GPIO_ClrBit()
* :
* : GPIO_TypeDef * GPIOx GPIOGPIOAGPIOBGPIOC
* uint32_t n GPIOPIN0PIN1PIN2... ... PIN14PIN15
* :
* :
******************************************************************************************************************************************/
void GPIO_ClrBit(GPIO_TypeDef * GPIOx, uint32_t n)
{
*(&GPIOx->DATAPIN0 + n) = 0;
}
/******************************************************************************************************************************************
* : GPIO_InvBit()
* :
* : GPIO_TypeDef * GPIOx GPIOGPIOAGPIOBGPIOC
* uint32_t n GPIOPIN0PIN1PIN2... ... PIN14PIN15
* :
* :
******************************************************************************************************************************************/
void GPIO_InvBit(GPIO_TypeDef * GPIOx, uint32_t n)
{
*(&GPIOx->DATAPIN0 + n) = 1 - *(&GPIOx->DATAPIN0 + n);
}
/******************************************************************************************************************************************
* : GPIO_GetBit()
* :
* : GPIO_TypeDef * GPIOx GPIOGPIOAGPIOBGPIOC
* uint32_t n GPIOPIN0PIN1PIN2... ... PIN14PIN15
* : 0 1
* :
******************************************************************************************************************************************/
uint32_t GPIO_GetBit(GPIO_TypeDef * GPIOx, uint32_t n)
{
return *(&GPIOx->DATAPIN0 + n);
}
/******************************************************************************************************************************************
* : GPIO_SetBits()
* : nw
* : GPIO_TypeDef * GPIOx GPIOGPIOAGPIOBGPIOC
* uint32_t n GPIOPIN0PIN1PIN2... ... PIN14PIN15
* uint32_t w
* :
* :
******************************************************************************************************************************************/
void GPIO_SetBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w)
{
uint32_t bits;
bits = 0xFFFF >> (16 - w);
GPIOx->ODR |= (bits << n);
}
/******************************************************************************************************************************************
* : GPIO_ClrBits()
* : nw
* : GPIO_TypeDef * GPIOx GPIOGPIOAGPIOBGPIOC
* uint32_t n GPIOPIN0PIN1PIN2... ... PIN14PIN15
* uint32_t w
* :
* :
******************************************************************************************************************************************/
void GPIO_ClrBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w)
{
uint32_t bits;
bits = 0xFFFF >> (16 - w);
GPIOx->ODR &= ~(bits << n);
}
/******************************************************************************************************************************************
* : GPIO_InvBits()
* : nw
* : GPIO_TypeDef * GPIOx GPIOGPIOAGPIOBGPIOC
* uint32_t n GPIOPIN0PIN1PIN2... ... PIN14PIN15
* uint32_t w
* :
* :
******************************************************************************************************************************************/
void GPIO_InvBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w)
{
uint32_t bits;
bits = 0xFFFF >> (16 - w);
GPIOx->ODR ^= (bits << n);
}
/******************************************************************************************************************************************
* : GPIO_GetBits()
* : nw
* : GPIO_TypeDef * GPIOx GPIOGPIOAGPIOBGPIOC
* uint32_t n GPIOPIN0PIN1PIN2... ... PIN14PIN15
* uint32_t w
* : nw 0 1
* 0n1n+1... ...wn+w
* :
******************************************************************************************************************************************/
uint32_t GPIO_GetBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w)
{
uint32_t bits;
bits = 0xFFFF >> (16 - w);
return ((GPIOx->IDR >> n) & bits);
}
/******************************************************************************************************************************************
* : GPIO_AtomicSetBits()
* : nw--ISR
* : GPIO_TypeDef * GPIOx GPIOGPIOAGPIOBGPIOC
* uint32_t n GPIOPIN0PIN1PIN2... ... PIN14PIN15
* uint32_t w
* :
* : GPIOx16ISRGPIOxGPIO_Atomic
******************************************************************************************************************************************/
void GPIO_AtomicSetBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w)
{
uint32_t bits;
bits = 0xFFFF >> (16 - w);
__disable_irq();
GPIOx->ODR |= (bits << n);
__enable_irq();
}
/******************************************************************************************************************************************
* : GPIO_AtomicClrBits()
* : nw--ISR
* : GPIO_TypeDef * GPIOx GPIOGPIOAGPIOBGPIOC
* uint32_t n GPIOPIN0PIN1PIN2... ... PIN14PIN15
* uint32_t w
* :
* : GPIOx16ISRGPIOxGPIO_Atomic
******************************************************************************************************************************************/
void GPIO_AtomicClrBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w)
{
uint32_t bits;
bits = 0xFFFF >> (16 - w);
__disable_irq();
GPIOx->ODR &= ~(bits << n);
__enable_irq();
}
/******************************************************************************************************************************************
* : GPIO_AtomicInvBits()
* : nw--ISR
* : GPIO_TypeDef * GPIOx GPIOGPIOAGPIOBGPIOC
* uint32_t n GPIOPIN0PIN1PIN2... ... PIN14PIN15
* uint32_t w
* :
* : GPIOx16ISRGPIOxGPIO_Atomic
******************************************************************************************************************************************/
void GPIO_AtomicInvBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w)
{
uint32_t bits;
bits = 0xFFFF >> (16 - w);
__disable_irq();
GPIOx->ODR ^= (bits << n);
__enable_irq();
}

@ -0,0 +1,38 @@
#ifndef __SWM221_GPIO_H__
#define __SWM221_GPIO_H__
void GPIO_Init(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, uint32_t pull_down, uint32_t open_drain); //引脚初始化,包含引脚方向、上拉、下拉、开漏
#define GPIO_INPUT ((0 << 0) | (0 << 1) | (0 << 2) | (0 << 3))
#define GPIO_INPUT_PullUp ((0 << 0) | (1 << 1) | (0 << 2) | (0 << 3))
#define GPIO_INPUT_PullDown ((0 << 0) | (0 << 1) | (1 << 2) | (0 << 3))
#define GPIO_OUTPUT ((1 << 0) | (0 << 1) | (0 << 2) | (0 << 3))
#define GPIO_OUTPUT_OpenDrain ((1 << 0) | (0 << 1) | (0 << 2) | (1 << 3))
#define GPIO_OUTPUT_OpenDrain_PullUp ((1 << 0) | (1 << 1) | (0 << 2) | (1 << 3))
#define GPIO_INIT(GPIOx, n, mode) GPIO_Init(GPIOx, n, (mode & 1) ? 1 : 0, (mode & 2) ? 1 : 0, (mode & 4) ? 1 : 0, (mode & 8) ? 1 : 0)
void GPIO_SetBit(GPIO_TypeDef * GPIOx, uint32_t n); //将参数指定的引脚电平置高
void GPIO_ClrBit(GPIO_TypeDef * GPIOx, uint32_t n); //将参数指定的引脚电平置低
void GPIO_InvBit(GPIO_TypeDef * GPIOx, uint32_t n); //将参数指定的引脚电平反转
uint32_t GPIO_GetBit(GPIO_TypeDef * GPIOx, uint32_t n); //读取参数指定的引脚的电平状态
void GPIO_SetBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w); //将参数指定的从n开始的w位连续引脚的电平置高
void GPIO_ClrBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w); //将参数指定的从n开始的w位连续引脚的电平置低
void GPIO_InvBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w); //将参数指定的从n开始的w位连续引脚的电平反转
uint32_t GPIO_GetBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w); //读取参数指定的从n开始的w位连续引脚的电平状态
void GPIO_AtomicSetBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w);
void GPIO_AtomicClrBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w);
void GPIO_AtomicInvBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w);
// for compatibility
#define GPIO_AtomicSetBit GPIO_SetBit
#define GPIO_AtomicClrBit GPIO_ClrBit
#define GPIO_AtomicInvBit GPIO_InvBit
#endif //__SWM221_GPIO_H__

@ -0,0 +1,308 @@
/******************************************************************************************************************************************
* : SWM221_i2c.c
* : SWM221I2C
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.0.0 2016130
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIES AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIEE. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIES ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM221.h"
#include "SWM221_i2c.h"
/******************************************************************************************************************************************
* : I2C_Init()
* : I2C
* : I2C_TypeDef * I2Cx I2CI2C0
* I2C_InitStructure * initStruct I2C
* :
* :
******************************************************************************************************************************************/
void I2C_Init(I2C_TypeDef * I2Cx, I2C_InitStructure * initStruct)
{
switch((uint32_t)I2Cx)
{
case ((uint32_t)I2C0):
SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_I2C0_Pos);
break;
}
__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();
I2C_Close(I2Cx); //一些关键寄存器只能在I2C关闭时设置
if(initStruct->Master == 1)
{
int total_clkdiv, clkdiv, scl_hi = 0;
I2Cx->CR |= (1 << I2C_CR_MASTER_Pos);
total_clkdiv = SystemCoreClock / initStruct->MstClk;
if(total_clkdiv < 17)
total_clkdiv = 17; //无法产生指定的频率,产生最接近的频率
do {
scl_hi++;
clkdiv = (total_clkdiv - 14) / (scl_hi + scl_hi * 2);
} while(clkdiv > 256);
I2Cx->CLK = ((scl_hi * 2 - 1) << I2C_CLK_SCLL_Pos) |
((scl_hi - 1) << I2C_CLK_SCLH_Pos) |
((clkdiv - 1) << I2C_CLK_DIV_Pos);
I2Cx->IF = 0xFFFFFFFF;
I2Cx->IE = (initStruct->TXEmptyIEn << I2C_IE_TXE_Pos) |
(initStruct->RXNotEmptyIEn << I2C_IE_RXNE_Pos);
switch((uint32_t)I2Cx)
{
case ((uint32_t)I2C0):
if(initStruct->TXEmptyIEn | initStruct->RXNotEmptyIEn)
{
NVIC_EnableIRQ(I2C0_IRQn);
}
else
{
NVIC_DisableIRQ(I2C0_IRQn);
}
break;
}
}
else
{
I2Cx->CR &= ~(1 << I2C_CR_MASTER_Pos);
I2Cx->SCR &= ~I2C_SCR_ADDR10_Msk;
I2Cx->SCR |= (initStruct->Addr10b << I2C_SCR_ADDR10_Pos);
if(initStruct->Addr10b)
I2Cx->SADDR = (initStruct->SlvAddr << I2C_SADDR_ADDR10_Pos) |
(initStruct->SlvAddrMsk << I2C_SADDR_MASK10_Pos);
else
I2Cx->SADDR = (initStruct->SlvAddr << I2C_SADDR_ADDR7_Pos) |
(initStruct->SlvAddrMsk << I2C_SADDR_MASK7_Pos);
I2Cx->IF = 0xFFFFFFFF;
I2Cx->IE = (initStruct->TXEmptyIEn << I2C_IE_TXE_Pos) |
(initStruct->RXNotEmptyIEn << I2C_IE_RXNE_Pos) |
(initStruct->SlvSTADetIEn << I2C_IE_RXSTA_Pos) |
(initStruct->SlvSTODetIEn << I2C_IE_RXSTO_Pos);
switch((uint32_t)I2Cx)
{
case ((uint32_t)I2C0):
if(initStruct->SlvSTADetIEn | initStruct->SlvSTODetIEn | initStruct->TXEmptyIEn | initStruct->RXNotEmptyIEn)
{
NVIC_EnableIRQ(I2C0_IRQn);
}
else
{
NVIC_DisableIRQ(I2C0_IRQn);
}
break;
}
}
}
/******************************************************************************************************************************************
* : I2C_Open()
* : I2C
* : I2C_TypeDef * I2Cx I2CI2C0
* :
* :
******************************************************************************************************************************************/
void I2C_Open(I2C_TypeDef * I2Cx)
{
I2Cx->CR |= (0x01 << I2C_CR_EN_Pos);
}
/******************************************************************************************************************************************
* : I2C_Close()
* : I2C
* : I2C_TypeDef * I2Cx I2CI2C0
* :
* :
******************************************************************************************************************************************/
void I2C_Close(I2C_TypeDef * I2Cx)
{
I2Cx->CR &= ~(0x01 << I2C_CR_EN_Pos);
}
/******************************************************************************************************************************************
* : I2C_Start()
* :
* : I2C_TypeDef * I2Cx I2CI2C0I2C1
* uint8_t addr
* uint8_t wait 1 0
* : uint8_t 1 ACK 0 NACK
* : I2C_StartDone() I2C_IsAck() ACKNACK
******************************************************************************************************************************************/
uint8_t I2C_Start(I2C_TypeDef * I2Cx, uint8_t addr, uint8_t wait)
{
I2Cx->TXDATA = addr;
I2Cx->MCR = (1 << I2C_MCR_STA_Pos) |
(1 << I2C_MCR_WR_Pos); //发送起始位和从机地址
if(wait == 0)
return 0;
while(I2Cx->MCR & I2C_MCR_WR_Msk) __NOP(); //等待发送完成
return (I2Cx->TR & I2C_TR_RXACK_Msk) ? 0 : 1;
}
uint8_t I2C_StartDone(I2C_TypeDef * I2Cx)
{
return (I2Cx->MCR & I2C_MCR_WR_Msk) ? 0 : 1;
}
uint8_t I2C_IsAck(I2C_TypeDef * I2Cx)
{
return (I2Cx->TR & I2C_TR_RXACK_Msk) ? 0 : 1;
}
/******************************************************************************************************************************************
* : I2C_Stop()
* :
* : I2C_TypeDef * I2Cx I2CI2C0I2C1
* uint8_t wait 1 0
* :
* : I2C_StopDone()
******************************************************************************************************************************************/
void I2C_Stop(I2C_TypeDef * I2Cx, uint8_t wait)
{
I2Cx->MCR = (1 << I2C_MCR_STO_Pos);
if(wait == 0)
return;
while(I2Cx->MCR & I2C_MCR_STO_Msk) __NOP(); //等待发送完成
}
uint8_t I2C_StopDone(I2C_TypeDef * I2Cx)
{
return (I2Cx->MCR & I2C_MCR_STO_Msk) ? 0 : 1;
}
/******************************************************************************************************************************************
* : I2C_Write()
* :
* : I2C_TypeDef * I2Cx I2CI2C0I2C1
* uint8_t data
* uint8_t wait 1 0
* : uint8_t 1 ACK 0 NACK
* : I2C_WriteDone() I2C_IsAck() ACKNACK
******************************************************************************************************************************************/
uint8_t I2C_Write(I2C_TypeDef * I2Cx, uint8_t data, uint8_t wait)
{
I2Cx->TXDATA = data;
I2Cx->MCR = (1 << I2C_MCR_WR_Pos);
if(wait == 0)
return 0;
while(I2Cx->MCR & I2C_MCR_WR_Msk) __NOP(); //等待发送完成
return (I2Cx->TR & I2C_TR_RXACK_Msk) ? 0 : 1;
}
uint8_t I2C_WriteDone(I2C_TypeDef * I2Cx)
{
return (I2Cx->MCR & I2C_MCR_WR_Msk) ? 0 : 1;
}
/******************************************************************************************************************************************
* : I2C_Read()
* :
* : I2C_TypeDef * I2Cx I2CI2C0I2C1
* uint8_t ack 1 ACK 0 NACK
* uint8_t wait 1 0
* : uint8_t
* : I2C_ReadDone() I2Cx->RXDATA
******************************************************************************************************************************************/
uint8_t I2C_Read(I2C_TypeDef * I2Cx, uint8_t ack, uint8_t wait)
{
I2Cx->TR = ((ack ? 0 : 1) << I2C_TR_TXACK_Pos);
I2Cx->MCR = (1 << I2C_MCR_RD_Pos);
if(wait == 0)
return 0;
while(I2Cx->MCR & I2C_MCR_RD_Msk) __NOP(); //等待接收完成
return I2Cx->RXDATA;
}
uint8_t I2C_ReadDone(I2C_TypeDef * I2Cx)
{
return (I2Cx->MCR & I2C_MCR_RD_Msk) ? 0 : 1;
}
/******************************************************************************************************************************************
* : I2C_INTEn()
* : 使
* : I2C_TypeDef * I2Cx I2CI2C0
* uint32_t it interrupt typeI2C_IT_TX_EMPTYI2C_IT_RX_NOT_EMPTYI2C_IT_RX_OVFI2C_IT_TX_DONEI2C_IT_RX_DONE
* I2C_IT_SLV_DET_STAI2C_IT_SLV_DET_STPI2C_IT_ARB_LOSTI2C_IT_SCL_LOW_TO
* :
* :
******************************************************************************************************************************************/
void I2C_INTEn(I2C_TypeDef * I2Cx, uint32_t it)
{
I2Cx->IE |= it;
}
/******************************************************************************************************************************************
* : I2C_INTDis()
* :
* : I2C_TypeDef * I2Cx I2CI2C0
* uint32_t it interrupt typeI2C_IT_TX_EMPTYI2C_IT_RX_NOT_EMPTYI2C_IT_RX_OVFI2C_IT_TX_DONEI2C_IT_RX_DONE
* I2C_IT_SLV_DET_STAI2C_IT_SLV_DET_STPI2C_IT_ARB_LOSTI2C_IT_SCL_LOW_TO
* :
* :
******************************************************************************************************************************************/
void I2C_INTDis(I2C_TypeDef * I2Cx, uint32_t it)
{
I2Cx->IE &= ~it;
}
/******************************************************************************************************************************************
* : I2C_INTClr()
* :
* : I2C_TypeDef * I2Cx I2CI2C0
* uint32_t it interrupt typeI2C_IT_TX_EMPTYI2C_IT_RX_NOT_EMPTYI2C_IT_RX_OVFI2C_IT_TX_DONEI2C_IT_RX_DONE
* I2C_IT_SLV_DET_STAI2C_IT_SLV_DET_STPI2C_IT_ARB_LOSTI2C_IT_SCL_LOW_TO
* :
* :
******************************************************************************************************************************************/
void I2C_INTClr(I2C_TypeDef * I2Cx, uint32_t it)
{
I2Cx->IF = it;
}
/******************************************************************************************************************************************
* : I2C_INTStat()
* :
* : I2C_TypeDef * I2Cx I2CI2C0
* uint32_t it interrupt typeI2C_IT_TX_EMPTYI2C_IT_RX_NOT_EMPTYI2C_IT_RX_OVFI2C_IT_TX_DONEI2C_IT_RX_DONE
* I2C_IT_SLV_DET_STAI2C_IT_SLV_DET_STPI2C_IT_ARB_LOSTI2C_IT_SCL_LOW_TO
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t I2C_INTStat(I2C_TypeDef * I2Cx, uint32_t it)
{
return (I2Cx->IF & it) ? 1 : 0;
}

@ -0,0 +1,53 @@
#ifndef __SWM221_I2C_H__
#define __SWM221_I2C_H__
typedef struct {
uint8_t Master; //1 主机模式 0 从机模式
uint32_t MstClk; //主机传输时钟频率
uint8_t Addr10b; //1 10位地址模式 0 7位地址模式
uint16_t SlvAddr; //从机地址
uint16_t SlvAddrMsk;
uint8_t TXEmptyIEn; //发送寄存器空中断使能
uint8_t RXNotEmptyIEn; //接收寄存器非空中断使能
uint8_t SlvSTADetIEn; //从机检测到起始中断使能
uint8_t SlvSTODetIEn; //从机检测到终止中断使能
} I2C_InitStructure;
/* Interrupt Type */
#define I2C_IT_TX_EMPTY (1 << 0) //TX FIFO Empty
#define I2C_IT_RX_NOT_EMPTY (1 << 1) //RX FIFO Not Empty
#define I2C_IT_RX_OVF (1 << 2) //RX FIFO Overflow
#define I2C_IT_TX_DONE (1 << 3) //发送完成接收到ACK
#define I2C_IT_RX_DONE (1 << 4) //接收完成发送出ACK
#define I2C_IT_SLV_DET_STA (1 << 8) //从机检测到起始位
#define I2C_IT_SLV_DET_STP (1 << 9) //从机检测到停止位
#define I2C_IT_ARB_LOST (1 << 16) //主机Arbitration lost
#define I2C_IT_SCL_LOW_TO (1 << 17) //主机SCL Low Timeout
void I2C_Init(I2C_TypeDef * I2Cx, I2C_InitStructure * initStruct);
void I2C_Open(I2C_TypeDef * I2Cx);
void I2C_Close(I2C_TypeDef * I2Cx);
uint8_t I2C_Start(I2C_TypeDef * I2Cx, uint8_t addr, uint8_t wait);
void I2C_Stop(I2C_TypeDef * I2Cx, uint8_t wait);
uint8_t I2C_Write(I2C_TypeDef * I2Cx, uint8_t data, uint8_t wait);
uint8_t I2C_Read(I2C_TypeDef * I2Cx, uint8_t ack, uint8_t wait);
uint8_t I2C_StartDone(I2C_TypeDef * I2Cx);
uint8_t I2C_StopDone(I2C_TypeDef * I2Cx);
uint8_t I2C_WriteDone(I2C_TypeDef * I2Cx);
uint8_t I2C_ReadDone(I2C_TypeDef * I2Cx);
uint8_t I2C_IsAck(I2C_TypeDef * I2Cx);
void I2C_INTEn(I2C_TypeDef * I2Cx, uint32_t it); //中断使能
void I2C_INTDis(I2C_TypeDef * I2Cx, uint32_t it); //中断禁止
void I2C_INTClr(I2C_TypeDef * I2Cx, uint32_t it); //中断标志清除
uint32_t I2C_INTStat(I2C_TypeDef * I2Cx, uint32_t it); //中断状态查询
#endif //__SWM221_I2C_H__

@ -0,0 +1,46 @@
/******************************************************************************************************************************************
* : SWM221_iofilt.c
* : SWM221IOPAD
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.0.0 2016130
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM221.h"
#include "SWM221_iofilt.h"
/******************************************************************************************************************************************
* : IOFILT_Init()
* : IO
* : uint32_t IOFILTn 0-1
* uint32_t signal IOFILTn = 0 IOFILT0_PB14IOFILT0_PB4IOFILT0_PB5IOFILT0_PB6
* IOFILTn = 1 IOFILT1_ACMP0IOFILT1_ACMP1
* uint32_t width width IOFILT_WIDTH_250nsIOFILT_WIDTH_500ns...
* :
* :
******************************************************************************************************************************************/
void IOFILT_Init(uint32_t IOFILTn, uint32_t signal, uint32_t width)
{
SYS->CLKSEL &= ~SYS_CLKSEL_IOFILT_Msk;
SYS->CLKSEL |= (0 << SYS_CLKSEL_IOFILT_Pos); //滤波器时钟源HRC
SYS->CLKEN0 |= SYS_CLKEN0_IOFILT_Msk;
for(int i = 0; i < 10; i++) __NOP();
*(&SYS->IOFILT0 + IOFILTn) = (signal << SYS_IOFILT_IO0EN_Pos) |
(0 << SYS_IOFILT_CLKDIV_Pos) |
(width << SYS_IOFILT_TIM_Pos);
}

@ -0,0 +1,35 @@
#ifndef __SWM221_IOFILT_H__
#define __SWM221_IOFILT_H__
/* 选择对哪个信号进行滤波 */
#define IOFILT0_PB14 1
#define IOFILT0_PB4 2
#define IOFILT0_PB5 4
#define IOFILT0_PB6 8
#define IOFILT1_ACMP0 1 // 对 ACMP0_OUT 滤波ACMP0 的状态SYS->ACMPSR.CMP0OUT、中断SYS->ACMPSR.CMP0IF、作为 PWM 刹车信号均被滤波
#define IOFILT1_ACMP1 2
#define IOFILT_WIDTH_250ns 1 // 滤波器时钟源为 HRC 且滤波时钟不分频时,每个滤波周期为 1/8MHz = 125ns
#define IOFILT_WIDTH_500ns 2
#define IOFILT_WIDTH_1us 3
#define IOFILT_WIDTH_2us 4
#define IOFILT_WIDTH_4us 5
#define IOFILT_WIDTH_8us 6
#define IOFILT_WIDTH_16us 7
#define IOFILT_WIDTH_32us 8
#define IOFILT_WIDTH_64us 9
#define IOFILT_WIDTH_128us 10
#define IOFILT_WIDTH_256us 11
#define IOFILT_WIDTH_512us 12
#define IOFILT_WIDTH_1024us 13
#define IOFILT_WIDTH_2048us 14
#define IOFILT_WIDTH_4096us 15
void IOFILT_Init(uint32_t IOFILTn, uint32_t signal, uint32_t width);
#endif // __SWM221_IOFILT_H__

@ -0,0 +1,90 @@
/******************************************************************************************************************************************
* : SWM221_mpu.c
* : SWM221MPU
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.0.0 2016130
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM221.h"
#include "SWM221_mpu.h"
/******************************************************************************************************************************************
* : MPU_Init()
* : MPU LCD
* : MPU_TypeDef * MPUx MPUMPU
* MPU_InitStructure * initStruct MPU LCD
* :
* :
******************************************************************************************************************************************/
void MPU_Init(MPU_TypeDef * MPUx, MPU_InitStructure * initStruct)
{
switch((uint32_t)MPUx)
{
case ((uint32_t)MPU):
SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_MPU_Pos);
__NOP();__NOP();__NOP();
break;
}
MPUx->SR = initStruct->ByteOrder << MPU_SR_ENDIAN_Pos;
MPUx->CR = ((initStruct->RDHoldTime - 1) << MPU_CR_RDHOLD_Pos) |
((initStruct->WRHoldTime - 1) << MPU_CR_WRHOLD_Pos) |
((initStruct->CSFall_WRFall - 1) << MPU_CR_CS0WR0_Pos) |
((initStruct->WRRise_CSRise - 1) << MPU_CR_WR1CS1_Pos) |
((initStruct->RDCSRise_Fall - 1) << MPU_CR_RCS1_0_Pos) |
((initStruct->WRCSRise_Fall - 1) << MPU_CR_WCS1_0_Pos);
}
static uint32_t MPU_IsBusy(MPU_TypeDef * MPUx)
{
return (MPUx->SR & MPU_SR_BUSY_Msk);
}
void MPU_WR_REG8(MPU_TypeDef * MPUx, uint8_t reg)
{
MPUx->IRB = reg;
while(MPU_IsBusy(MPUx)) {}
}
void MPU_WR_DATA8(MPU_TypeDef * MPUx, uint8_t val)
{
MPUx->DRB = val;
while(MPU_IsBusy(MPUx)) {}
}
void MPU_WR_DATA16(MPU_TypeDef * MPUx, uint16_t val)
{
MPUx->DRH = val;
while(MPU_IsBusy(MPUx)) {}
}
void MPU_WriteReg(MPU_TypeDef * MPUx, uint8_t reg, uint8_t val)
{
MPU_WR_REG8(MPUx, reg);
MPU_WR_DATA8(MPUx, val);
}
uint8_t MPU_ReadReg(MPU_TypeDef * MPUx, uint8_t reg)
{
MPU_WR_REG8(MPUx, reg);
return MPUx->DRB;
}

@ -0,0 +1,29 @@
#ifndef __SWM221_MPU_H__
#define __SWM221_MPU_H__
typedef struct {
uint8_t ByteOrder; //执行半字写入时,先发送低 8 位、还是先发送高 8 位,可取值 MPU_LITTLE_ENDIAN、MPU_BIG_ENDIAN
uint8_t RDHoldTime; //LCD_RD低电平保持时间,取值1--32
uint8_t WRHoldTime; //LCD_WR低电平保持时间,取值1--16
uint8_t CSFall_WRFall; //LCD_CS下降沿到LCD_WR下降沿延时取值1--4
uint8_t WRRise_CSRise; //LCD_WR上升沿到LCD_CS上升沿延时取值1--4
uint8_t RDCSRise_Fall; //读操作时LCD_CS上升沿到下降沿延时取值1--32
uint8_t WRCSRise_Fall; //写操作时LCD_CS上升沿到下降沿延时取值1--16
} MPU_InitStructure;
#define MPU_LITTLE_ENDIAN 0
#define MPU_BIG_ENDIAN 1
void MPU_Init(MPU_TypeDef * MPUx, MPU_InitStructure * initStruct);
void MPU_WR_REG8(MPU_TypeDef * MPUx, uint8_t reg);
void MPU_WR_DATA8(MPU_TypeDef * MPUx, uint8_t val);
void MPU_WR_DATA16(MPU_TypeDef * MPUx, uint16_t val);
void MPU_WriteReg(MPU_TypeDef * MPUx, uint8_t reg, uint8_t val);
uint8_t MPU_ReadReg(MPU_TypeDef * MPUx, uint8_t reg);
#endif // __SWM221_MPU_H__

@ -0,0 +1,49 @@
/******************************************************************************************************************************************
* : SWM221_port.c
* : SWM221
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.0.0 2016130
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM221.h"
/******************************************************************************************************************************************
* : PORT_Init()
* : "SWM221_port.h"
* : PORT_TypeDef * PORTx PORTPORTAPORTBPORTC
* uint32_t n PORTPIN0PIN1PIN2... ... PIN14PIN15
* uint32_t func "SWM221_port.h"
* uint32_t digit_in_en 使
* :
* :
******************************************************************************************************************************************/
void PORT_Init(PORT_TypeDef * PORTx, uint32_t n, uint32_t func, uint32_t digit_in_en)
{
if(n < PIN8)
{
PORTx->FUNC0 &= ~(0x0F << (n*4));
PORTx->FUNC0 |= (func << (n*4));
}
else
{
PORTx->FUNC1 &= ~(0x0F << ((n-8)*4));
PORTx->FUNC1 |= (func << ((n-8)*4));
}
if(digit_in_en) PORTx->INEN |= (1 << n);
else PORTx->INEN &= ~(1 << n);
}

@ -0,0 +1,268 @@
#ifndef __SWM221_PORT_H__
#define __SWM221_PORT_H__
void PORT_Init(PORT_TypeDef * PORTx, uint32_t n, uint32_t func, uint32_t digit_in_en); //端口引脚功能选择,其可取值如下:
#define PORTA_PIN0_GPIO 0
#define PORTA_PIN0_MPU_D7 1
#define PORTA_PIN0_I2C0_SCL 2
#define PORTA_PIN0_UART0_RX 3
#define PORTA_PIN0_PWM0AN 4
#define PORTA_PIN0_PWM1BN 5
#define PORTA_PIN0_PWM0A 6
#define PORTA_PIN1_GPIO 0
#define PORTA_PIN1_I2C0_SDA 1
#define PORTA_PIN1_UART0_TX 2
#define PORTA_PIN1_PWM1BN 3
#define PORTA_PIN1_PWM1B 4
#define PORTA_PIN2_GPIO 0
#define PORTA_PIN2_USART0_TX 1
#define PORTA_PIN2_PWM1AN 2
#define PORTA_PIN2_PWM0AN 3
#define PORTA_PIN2_PWM1A 4
#define PORTA_PIN3_GPIO 0
#define PORTA_PIN3_USART0_RX 1
#define PORTA_PIN3_PWM0A 2
#define PORTA_PIN3_PWM1AN 3
#define PORTA_PIN3_PWM0AN 4
#define PORTA_PIN4_GPIO 0
#define PORTA_PIN4_UART1_TX 1
#define PORTA_PIN4_PWM1B 2
#define PORTA_PIN4_PWM1AN 3
#define PORTA_PIN4_PWM1BN 4
#define PORTA_PIN5_GPIO 0
#define PORTA_PIN5_UART1_RX 1
#define PORTA_PIN5_PWM1A 2
#define PORTA_PIN5_PWM0AN 3
#define PORTA_PIN5_PWM1AN 4
#define PORTA_PIN6_GPIO 0
#define PORTA_PIN6_I2C0_SCL 1
#define PORTA_PIN6_USART0_TX 2
#define PORTA_PIN6_CAN0_RX 3
#define PORTA_PIN6_PWM0B 4
#define PORTA_PIN6_BTIMR0_OUT 5
#define PORTA_PIN7_GPIO 0
#define PORTA_PIN7_I2C0_SDA 1
#define PORTA_PIN7_USART0_RX 2
#define PORTA_PIN7_CAN0_TX 3
#define PORTA_PIN7_PWM0BN 4
#define PORTA_PIN7_BTIMR1_OUT 5
#define PORTA_PIN8_GPIO 0
#define PORTA_PIN8_MPU_D0 1
#define PORTA_PIN8_SPI0_SCLK 2
#define PORTA_PIN8_QSPI0_SCLK 3
#define PORTA_PIN8_ADC0_CH2 7
#define PORTA_PIN8_OPA1_OUT 7
#define PORTA_PIN9_GPIO 0
#define PORTA_PIN9_MPU_D1 1
#define PORTA_PIN9_USART0_TX 2
#define PORTA_PIN9_SPI0_MOSI 3
#define PORTA_PIN9_QSPI0_MOSI 4
#define PORTA_PIN9_OPA1_INP 7
#define PORTA_PIN10_GPIO 0
#define PORTA_PIN10_MPU_D2 1
#define PORTA_PIN10_USART0_RX 2
#define PORTA_PIN10_SPI0_MISO 3
#define PORTA_PIN10_QSPI0_MISO 4
#define PORTA_PIN10_OPA1_INN 7
#define PORTA_PIN11_GPIO 0
#define PORTA_PIN11_MPU_D3 1
#define PORTA_PIN11_SPI0_SSEL 2
#define PORTA_PIN11_QSPI0_SSEL 3
#define PORTA_PIN11_PWM_CLK1 4
#define PORTA_PIN11_ADC0_CH1 7
#define PORTA_PIN11_ADC_REFP 7
#define PORTA_PIN12_GPIO 0
#define PORTA_PIN12_MPU_D4 1
#define PORTA_PIN12_UART1_TX 2
#define PORTA_PIN12_QSPI0_D2 3
#define PORTA_PIN12_ADC1_CH1 7
#define PORTA_PIN12_ACMP1_INN 7
#define PORTA_PIN13_GPIO 0
#define PORTA_PIN13_MPU_D5 1
#define PORTA_PIN13_UART1_RX 2
#define PORTA_PIN13_QSPI0_D3 3
#define PORTA_PIN13_ADC1_CH0 7
#define PORTA_PIN14_GPIO 0
#define PORTA_PIN14_MPU_D6 1
#define PORTA_PIN14_TIMR0_IN 2
#define PORTA_PIN14_TIMR0_OUT 3
#define PORTA_PIN14_ADC0_CH0 7
#define PORTA_PIN14_ACMP1_INP 7
#define PORTA_PIN15_GPIO 0
#define PORTA_PIN15_QSPI0_MOSI 1
#define PORTA_PIN15_PWM1A 2
#define PORTA_PIN15_HALL_IN2 3
#define PORTB_PIN0_GPIO 0
#define PORTB_PIN0_UART1_TX 1
#define PORTB_PIN0_QSPI0_MISO 2
#define PORTB_PIN0_BTIMR2_OUT 3
#define PORTB_PIN0_TIMR0_IN 4
#define PORTB_PIN0_TIMR0_OUT 5
#define PORTB_PIN0_ADC1_CH6 7
#define PORTB_PIN0_OPA2_INN 7
#define PORTB_PIN1_GPIO 0
#define PORTB_PIN1_UART1_RX 1
#define PORTB_PIN1_QSPI0_D2 2
#define PORTB_PIN1_BTIMR3_OUT 3
#define PORTB_PIN1_TIMR2_IN 4
#define PORTB_PIN1_TIMR2_OUT 5
#define PORTB_PIN1_OPA2_INP 7
#define PORTB_PIN2_GPIO 0
#define PORTB_PIN2_UART0_TX 1
#define PORTB_PIN2_QSPI0_D3 2
#define PORTB_PIN2_BTIMR0_OUT 3
#define PORTB_PIN2_TIMR1_IN 4
#define PORTB_PIN2_TIMR1_OUT 5
#define PORTB_PIN2_ADC0_CH8 7
#define PORTB_PIN2_OPA2_OUT 7
#define PORTB_PIN3_GPIO 0
#define PORTB_PIN3_UART0_RX 1
#define PORTB_PIN3_BTIMR1_OUT 2
#define PORTB_PIN3_TIMR2_IN 3
#define PORTB_PIN3_TIMR2_OUT 4
#define PORTB_PIN3_ACMP0_INN 7
#define PORTB_PIN4_GPIO 0
#define PORTB_PIN4_MPU_CS 1
#define PORTB_PIN4_QEI_A 2
#define PORTB_PIN4_I2C0_SCL 3
#define PORTB_PIN4_QSPI0_MOSI 4
#define PORTB_PIN4_HALL_IN0 5
#define PORTB_PIN4_ADC0_CH7 7
#define PORTB_PIN4_ACMP0_INP2 7
#define PORTB_PIN5_GPIO 0
#define PORTB_PIN5_MPU_RS 1
#define PORTB_PIN5_QEI_B 2
#define PORTB_PIN5_I2C0_SDA 3
#define PORTB_PIN5_HALL_IN1 4
#define PORTB_PIN5_TIMR1_IN 5
#define PORTB_PIN5_TIMR1_OUT 6
#define PORTB_PIN5_ADC0_CH6 7
#define PORTB_PIN5_ACMP0_INP1 7
#define PORTB_PIN6_GPIO 0
#define PORTB_PIN6_MPU_WR 1
#define PORTB_PIN6_QEI_Z 2
#define PORTB_PIN6_PWM_BRK1 3
#define PORTB_PIN6_HALL_IN2 4
#define PORTB_PIN6_TIMR0_IN 5
#define PORTB_PIN6_TIMR0_OUT 6
#define PORTB_PIN6_ADC0_CH5 7
#define PORTB_PIN6_ACMP0_INP0 7
#define PORTB_PIN7_GPIO 0
#define PORTB_PIN7_QEI_DIR 1
#define PORTB_PIN7_UART1_TX 2
#define PORTB_PIN7_CAN0_RX 3
#define PORTB_PIN7_TIMR2_IN 4
#define PORTB_PIN7_TIMR2_OUT 5
#define PORTB_PIN7_ADC1_CH3 7
#define PORTB_PIN7_OPA0_INP 7
#define PORTB_PIN8_GPIO 0
#define PORTB_PIN8_UART1_RX 1
#define PORTB_PIN8_CAN0_TX 2
#define PORTB_PIN8_OPA0_INN 7
#define PORTB_PIN9_GPIO 0
#define PORTB_PIN9_MPU_RD 1
#define PORTB_PIN9_ADC1_CH2 7
#define PORTB_PIN9_OPA0_OUT 7
#define PORTB_PIN10_GPIO 0
#define PORTB_PIN10_UART1_TX 1
#define PORTB_PIN10_UART1_RX 2
#define PORTB_PIN10_SPI0_SCLK 3
#define PORTB_PIN10_PWM0AN 4
#define PORTB_PIN10_TIMR0_IN 5
#define PORTB_PIN10_TIMR0_OUT 6
#define PORTB_PIN11_GPIO 0
#define PORTB_PIN11_UART0_TX 1
#define PORTB_PIN11_SPI0_SCLK 2
#define PORTB_PIN11_PWM0BN 3
#define PORTB_PIN11_TIMR1_IN 4
#define PORTB_PIN11_TIMR1_OUT 5
#define PORTB_PIN11_XTAL_IN 7
#define PORTB_PIN12_GPIO 0
#define PORTB_PIN12_UART0_RX 1
#define PORTB_PIN12_SPI0_MOSI 2
#define PORTB_PIN12_PWM0B 3
#define PORTB_PIN12_TIMR2_IN 4
#define PORTB_PIN12_TIMR2_OUT 5
#define PORTB_PIN12_XTAL_OUT 7
#define PORTB_PIN13_GPIO 0
#define PORTB_PIN13_SPI0_MOSI 1
#define PORTB_PIN13_PWM0A 2
#define PORTB_PIN14_GPIO 0
#define PORTB_PIN14_USART0_TX 1
#define PORTB_PIN14_UART0_TX 2
#define PORTB_PIN14_SPI0_MISO 3
#define PORTB_PIN14_PWM_BRK0 4
#define PORTB_PIN14_BTIMR2_OUT 5
#define PORTB_PIN14_ADC1_CH9 7
#define PORTB_PIN15_GPIO 0
#define PORTB_PIN15_USART0_RX 1
#define PORTB_PIN15_UART0_RX 2
#define PORTB_PIN15_SPI0_SSEL 3
#define PORTB_PIN15_BTIMR3_OUT 4
#define PORTB_PIN15_TIMR0_IN 5
#define PORTB_PIN15_TIMR0_OUT 5
#define PORTB_PIN15_ADC1_CH8 7
#define PORTC_PIN0_GPIO 0
#define PORTC_PIN0_SWCLK 1
#define PORTC_PIN0_UART1_TX 2
#define PORTC_PIN0_PWM_CLK0 3
#define PORTC_PIN0_TIMR1_IN 4
#define PORTC_PIN0_TIMR1_OUT 5
#define PORTC_PIN0_ADC1_CH7 7
#define PORTC_PIN1_GPIO 0
#define PORTC_PIN1_SWDIO 1
#define PORTC_PIN1_UART1_RX 2
#define PORTC_PIN1_BTIMR3_OUT 3
#define PORTC_PIN2_GPIO 0
#define PORTC_PIN2_I2C0_SCL 1
#define PORTC_PIN2_UART0_TX 2
#define PORTC_PIN2_QSPI0_SSEL 3
#define PORTC_PIN2_CAN0_RX 4
#define PORTC_PIN2_PWM0A 5
#define PORTC_PIN2_HALL_IN0 6
#define PORTC_PIN3_GPIO 0
#define PORTC_PIN3_I2C0_SDA 1
#define PORTC_PIN3_UART0_RX 2
#define PORTC_PIN3_QSPI0_SCLK 3
#define PORTC_PIN3_CAN0_TX 4
#define PORTC_PIN3_PWM0B 5
#define PORTC_PIN3_HALL_IN1 7
#endif //__SWM221_PORT_H__

@ -0,0 +1,528 @@
/******************************************************************************************************************************************
* : SWM221_pwm.c
* : SWM221PWM
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.0.0 2016130
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM221.h"
#include "SWM221_pwm.h"
/******************************************************************************************************************************************
* : PWM_Init()
* : PWM
* : PWM_TypeDef * PWMx PWMPWM0PWM1
* PWM_InitStructure * initStruct PWM
* :
* :
******************************************************************************************************************************************/
void PWM_Init(PWM_TypeDef * PWMx, PWM_InitStructure * initStruct)
{
SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_PWM_Pos);
PWMx->CR = (initStruct->Mode << PWM_CR_MODE_Pos) |
(1 << PWM_CR_MULT_Pos) | // 多次计数模式(即非单次)
(0 << PWM_CR_DIR_Pos) | // 向上计数
(0 << PWM_CR_CLKSRC_Pos) | // 系统时钟
((initStruct->Clkdiv - 1) << PWM_CR_CLKDIV_Pos) |
(0 << PWM_CR_RPTNUM_Pos); // 每次计数器溢出都执行寄存器重加载
PWMx->OCR = ((initStruct->IdleLevelA ? 1 : 0) << PWM_OCR_IDLEA_Pos) |
((initStruct->IdleLevelB ? 1 : 0) << PWM_OCR_IDLEB_Pos) |
((initStruct->IdleLevelAN ? 1 : 0) << PWM_OCR_IDLEAN_Pos) |
((initStruct->IdleLevelBN ? 1 : 0) << PWM_OCR_IDLEBN_Pos) |
((initStruct->OutputInvA ? 1 : 0) << PWM_OCR_INVA_Pos) |
((initStruct->OutputInvB ? 1 : 0) << PWM_OCR_INVB_Pos) |
((initStruct->OutputInvAN ? 1 : 0) << PWM_OCR_INVAN_Pos) |
((initStruct->OutputInvBN ? 1 : 0) << PWM_OCR_INVBN_Pos);
PWMx->PERIOD = initStruct->Period - 1;
PWMx->CMPA = initStruct->HdutyA;
PWMx->CMPA2 = initStruct->HdutyA2;
PWMx->DZA = initStruct->DeadzoneA;
PWMx->CMPB = initStruct->HdutyB;
PWMx->CMPB2 = initStruct->HdutyB2;
PWMx->DZB = initStruct->DeadzoneB;
PWMG->RELOADEN = 0x3F;
PWMx->IF = 0x3F;
PWMx->IE = ((initStruct->UpOvfIE ? 1 : 0) << PWM_IE_UPOVF_Pos) |
((initStruct->DownOvfIE ? 1 : 0) << PWM_IE_DNOVF_Pos) |
((initStruct->UpCmpAIE ? 1 : 0) << PWM_IE_UPCMPA_Pos) |
((initStruct->DownCmpAIE ? 1 : 0) << PWM_IE_DNCMPA_Pos) |
((initStruct->UpCmpBIE ? 1 : 0) << PWM_IE_UPCMPB_Pos) |
((initStruct->DownCmpBIE ? 1 : 0) << PWM_IE_DNCMPB_Pos);
if(initStruct->UpOvfIE || initStruct->DownOvfIE || initStruct->UpCmpAIE ||
initStruct->DownCmpAIE || initStruct->UpCmpBIE || initStruct->DownCmpBIE)
{
switch((uint32_t)PWMx)
{
case((uint32_t)PWM0):
NVIC_EnableIRQ(PWM0_IRQn);
break;
case((uint32_t)PWM1):
NVIC_EnableIRQ(PWM1_IRQn);
break;
}
}
}
/******************************************************************************************************************************************
* : PWM_Start()
* : PWMPWM
* : uint32_t pwm PWM0_MSKPWM1_MSKPWM2_MSKPWM3_MSKPWM4_MSKPWM5_MSK
* :
* :
******************************************************************************************************************************************/
void PWM_Start(uint32_t pwm)
{
PWMG->START |= pwm;
}
/******************************************************************************************************************************************
* : PWM_Stop()
* : PWMPWM
* : uint32_t pwm PWM0_MSKPWM1_MSKPWM2_MSKPWM3_MSKPWM4_MSKPWM5_MSK
* :
* :
******************************************************************************************************************************************/
void PWM_Stop(uint32_t pwm)
{
PWMG->START &= ~pwm;
}
/******************************************************************************************************************************************
* : PWM_Restart()
* : PWMPWM使
* : uint32_t pwm PWM0_MSKPWM1_MSKPWM2_MSKPWM3_MSKPWM4_MSKPWM5_MSK
* :
* :
******************************************************************************************************************************************/
void PWM_Restart(uint32_t pwm)
{
PWMG->RESTART = (pwm << PWMG_RESTART_PWM0_Pos);
}
/******************************************************************************************************************************************
* : PWM_ReloadEn()
* : Reload Enable PERIODCMPACMPBDZADZB
* : uint32_t pwm PWM0_MSKPWM1_MSKPWM2_MSKPWM3_MSKPWM4_MSKPWM5_MSK
* :
* : PERIODCMPACMPBDZADZB
* PWM_ReloadDis(PWM0_MSK | PWM1_MSK);
* PERIODCMPACMPBDZADZB
* PWM_ReloadEn(PWM0_MSK | PWM1_MSK);
******************************************************************************************************************************************/
void PWM_ReloadEn(uint32_t pwm)
{
PWMG->RELOADEN |= pwm;
}
/******************************************************************************************************************************************
* : PWM_ReloadDis()
* : Reload Enable PERIODCMPACMPBDZADZB
* : uint32_t pwm PWM0_MSKPWM1_MSKPWM2_MSKPWM3_MSKPWM4_MSKPWM5_MSK
* :
* :
******************************************************************************************************************************************/
void PWM_ReloadDis(uint32_t pwm)
{
PWMG->RELOADEN &= ~pwm;
}
/******************************************************************************************************************************************
* : PWM_BrkInPolarity()
* :
* : uint32_t brk PWM_BRK0PWM_BRK1PWM_BRK2
* uint32_t level 0 1
* :
* :
******************************************************************************************************************************************/
void PWM_BrkInPolarity(uint32_t brk, uint32_t level)
{
if(level)
PWMG->BRKPOL |= brk;
else
PWMG->BRKPOL &= ~brk;
}
/******************************************************************************************************************************************
* : PWM_BrkConfig()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1
* uint32_t chn PWMPWM_CH_APWM_CH_B
* uint32_t brk PWM_BRK0PWM_BRK1PWM_BRK2
* uint32_t out PWMxA/PWMxB
* uint32_t outN PWMxAN/PWMxBN
* uint32_t outHold 0 1
* uint32_t stpCount 1
* :
* :
******************************************************************************************************************************************/
void PWM_BrkConfig(PWM_TypeDef * PWMx, uint32_t chn, uint32_t brk, uint32_t out, uint32_t outN, uint32_t outHold, uint32_t stpCount)
{
if(chn == PWM_CH_A)
{
PWMx->BRKIN &= ~(0x7 << PWM_BRKIN_BRK0A_Pos);
PWMx->BRKIN |= (brk << PWM_BRKIN_BRK0A_Pos);
PWMx->BRKCR &= ~(PWM_BRKCR_OUTA_Msk | PWM_BRKCR_OUTAN_Msk | PWM_BRKCR_OFFA_Msk);
PWMx->BRKCR |= (out << PWM_BRKCR_OUTA_Pos) |
(outN << PWM_BRKCR_OUTAN_Pos) |
(outHold << PWM_BRKCR_OFFA_Pos) |
(stpCount << PWM_BRKCR_STPCNT_Pos);
}
else
{
PWMx->BRKIN &= ~(0x7 << PWM_BRKIN_BRK0B_Pos);
PWMx->BRKIN |= (brk << PWM_BRKIN_BRK0B_Pos);
PWMx->BRKCR &= ~(PWM_BRKCR_OUTB_Msk | PWM_BRKCR_OUTBN_Msk | PWM_BRKCR_OFFB_Msk);
PWMx->BRKCR |= (out << PWM_BRKCR_OUTB_Pos) |
(outN << PWM_BRKCR_OUTBN_Pos) |
(outHold << PWM_BRKCR_OFFB_Pos) |
(stpCount << PWM_BRKCR_STPCNT_Pos);
}
}
/******************************************************************************************************************************************
* : PWM_OvfTrigger()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1
* uint32_t en_up
* uint32_t en_down
* uint32_t trig_chn 8PWM_TRG_0PWM_TRG_1...PWM_TRG_7
* :
* :
******************************************************************************************************************************************/
void PWM_OvfTrigger(PWM_TypeDef * PWMx, uint32_t en_up, uint32_t en_down, uint32_t trig_chn)
{
PWMx->OVFTRG = (en_up << PWM_OVFTRG_UPEN_Pos) |
(en_down << PWM_OVFTRG_DNEN_Pos) |
(trig_chn << PWM_OVFTRG_MUX_Pos);
}
/******************************************************************************************************************************************
* : PWM_CmpTrigger()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1
* uint16_t match match
* uint32_t dir PWM_DIR_UP match PWM_DIR_DOWN match
* uint32_t width 04812...252 PWM
* uint32_t trig_chn 8PWM_TRG_0PWM_TRG_1...PWM_TRG_7
* uint32_t trig_interval 0 1 1 2 2 ... 7 7
* :
* :
******************************************************************************************************************************************/
void PWM_CmpTrigger(PWM_TypeDef * PWMx, uint16_t match, uint32_t dir, uint32_t width, uint32_t trig_chn, uint32_t trig_interval)
{
PWMx->CMPTRG = (1 << PWM_CMPTRG_EN_Pos) |
(match << PWM_CMPTRG_CMP_Pos) |
(dir << PWM_CMPTRG_DIR_Pos) |
((width/4) << PWM_CMPTRG_WIDTH_Pos) |
(trig_chn << PWM_CMPTRG_MUX_Pos) |
/* 在发出指定宽度触发信号的同时,还会在该触发信号宽度的 PWM->CMPTRG.ATP/8 位置处发出adc触发信号取值0--7 */
(3 << PWM_CMPTRG_ATP_Pos);
PWMx->CMPTRG2 = (trig_interval << PWM_CMPTRG2_INTV_Pos);
}
/******************************************************************************************************************************************
* : PWM_OutMask()
* : PWM
* : PWM_TypeDef * PWMx PWMPWM0PWM1
* uint32_t chn PWMPWM_CH_APWM_CH_B
* uint32_t evt PWMxY event PWM_EVT_DISPWM_EVT_0PWM_EVT_1...PWM_EVT_6
* uint32_t out PWMxY
* uint32_t evt_n PWMxYN event PWM_EVT_DISPWM_EVT_0PWM_EVT_1...PWM_EVT_6
* uint32_t out_n PWMxYN
* :
* :
******************************************************************************************************************************************/
void PWM_OutMask(PWM_TypeDef * PWMx, uint32_t chn, uint32_t evt, uint32_t out, uint32_t evt_n, uint32_t out_n)
{
if(chn == PWM_CH_A)
{
PWMx->EVMUX &= ~(PWM_EVMUX_MASKA_Msk | PWM_EVMUX_MASKAN_Msk);
PWMx->EVMUX |= (evt << PWM_EVMUX_MASKA_Pos) |
(evt_n << PWM_EVMUX_MASKAN_Pos);
PWMx->EVMSK &= ~(PWM_EVMSK_OUTA_Msk | PWM_EVMSK_OUTAN_Msk);
PWMx->EVMSK |= (out << PWM_EVMSK_OUTA_Pos) |
(out_n << PWM_EVMSK_OUTAN_Pos) |
(1 << PWM_EVMSK_IMME_Pos);
}
else
{
PWMx->EVMUX &= ~(PWM_EVMUX_MASKB_Msk | PWM_EVMUX_MASKBN_Msk);
PWMx->EVMUX |= (evt << PWM_EVMUX_MASKB_Pos) |
(evt_n << PWM_EVMUX_MASKBN_Pos);
PWMx->EVMSK &= ~(PWM_EVMSK_OUTB_Msk | PWM_EVMSK_OUTBN_Msk);
PWMx->EVMSK |= (out << PWM_EVMSK_OUTB_Pos) |
(out_n << PWM_EVMSK_OUTBN_Pos) |
(1 << PWM_EVMSK_IMME_Pos);
}
}
/******************************************************************************************************************************************
* : PWM_SetPeriod()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1
* uint16_t period
* :
* :
******************************************************************************************************************************************/
void PWM_SetPeriod(PWM_TypeDef * PWMx, uint16_t period)
{
PWMx->PERIOD = period - 1;
}
/******************************************************************************************************************************************
* : PWM_GetPeriod()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1
* : uint16_t
* :
******************************************************************************************************************************************/
uint16_t PWM_GetPeriod(PWM_TypeDef * PWMx)
{
return PWMx->PERIOD + 1;
}
/******************************************************************************************************************************************
* : PWM_SetHDuty()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1
* uint32_t chn PWMPWM_CH_APWM_CH_B
* uint16_t hduty
* :
* :
******************************************************************************************************************************************/
void PWM_SetHDuty(PWM_TypeDef * PWMx, uint32_t chn, uint16_t hduty)
{
if(chn == PWM_CH_A)
PWMx->CMPA = hduty;
else
PWMx->CMPB = hduty;
}
/******************************************************************************************************************************************
* : PWM_GetHDuty()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1
* uint32_t chn PWMPWM_CH_APWM_CH_B
* : uint16_t
* :
******************************************************************************************************************************************/
uint16_t PWM_GetHDuty(PWM_TypeDef * PWMx, uint32_t chn)
{
if(chn == PWM_CH_A)
return PWMx->CMPA;
else
return PWMx->CMPB;
}
/******************************************************************************************************************************************
* : PWM_SetHDuty2()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1
* uint32_t chn PWMPWM_CH_APWM_CH_B
* uint16_t hduty
* uint16_t hduty2
* :
* :
******************************************************************************************************************************************/
void PWM_SetHDuty2(PWM_TypeDef * PWMx, uint32_t chn, uint16_t hduty, uint16_t hduty2)
{
if(chn == PWM_CH_A)
{
PWMx->CMPA = hduty;
PWMx->CMPA2 = hduty2;
}
else
{
PWMx->CMPB = hduty;
PWMx->CMPB2 = hduty2;
}
}
/******************************************************************************************************************************************
* : PWM_GetHDuty2()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1
* uint32_t chn PWMPWM_CH_APWM_CH_B
* : uint16_t *hduty
* uint16_t *hduty2
* :
******************************************************************************************************************************************/
void PWM_GetHDuty2(PWM_TypeDef * PWMx, uint32_t chn, uint16_t *hduty, uint16_t *hduty2)
{
if(chn == PWM_CH_A)
{
*hduty = PWMx->CMPA;
*hduty2 = PWMx->CMPA2;
}
else
{
*hduty = PWMx->CMPB;
*hduty2 = PWMx->CMPB2;
}
}
/******************************************************************************************************************************************
* : PWM_SetDeadzone()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1
* uint32_t chn PWMPWM_CH_APWM_CH_B
* uint16_t deadzone 0--1023
* :
* :
******************************************************************************************************************************************/
void PWM_SetDeadzone(PWM_TypeDef * PWMx, uint32_t chn, uint16_t deadzone)
{
if(chn == PWM_CH_A)
PWMx->DZA = deadzone;
else
PWMx->DZB = deadzone;
}
/******************************************************************************************************************************************
* : PWM_GetDeadzone()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1
* uint32_t chn PWMPWM_CH_APWM_CH_B
* : uint16_t
* :
******************************************************************************************************************************************/
uint16_t PWM_GetDeadzone(PWM_TypeDef * PWMx, uint32_t chn)
{
if(chn == PWM_CH_A)
return PWMx->DZA;
else
return PWMx->DZB;
}
/******************************************************************************************************************************************
* : PWM_IntEn()
* : 使
* : PWM_TypeDef * PWMx PWMPWM0PWM1
* uint32_t it interrupt typePWM_IT_OVF_UPPWM_IT_OVF_DOWNPWM_IT_CMPA_UPPWM_IT_CMPB_UP
* PWM_IT_CMPA_DOWNPWM_IT_CMPB_DOWN
* :
* :
******************************************************************************************************************************************/
void PWM_IntEn(PWM_TypeDef * PWMx, uint32_t it)
{
PWMx->IE |= it;
}
/******************************************************************************************************************************************
* : PWM_IntDis()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1
* uint32_t it interrupt typePWM_IT_OVF_UPPWM_IT_OVF_DOWNPWM_IT_CMPA_UPPWM_IT_CMPB_UP
* PWM_IT_CMPA_DOWNPWM_IT_CMPB_DOWN
* :
* :
******************************************************************************************************************************************/
void PWM_IntDis(PWM_TypeDef * PWMx, uint32_t it)
{
PWMx->IE &= ~it;
}
/******************************************************************************************************************************************
* : PWM_IntClr()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1
* uint32_t it interrupt typePWM_IT_OVF_UPPWM_IT_OVF_DOWNPWM_IT_CMPA_UPPWM_IT_CMPB_UP
* PWM_IT_CMPA_DOWNPWM_IT_CMPB_DOWN
* :
* :
******************************************************************************************************************************************/
void PWM_IntClr(PWM_TypeDef * PWMx, uint32_t it)
{
PWMx->IF = it;
}
/******************************************************************************************************************************************
* : PWM_IntStat()
* :
* : PWM_TypeDef * PWMx PWMPWM0PWM1
* uint32_t it interrupt typePWM_IT_OVF_UPPWM_IT_OVF_DOWNPWM_IT_CMPA_UPPWM_IT_CMPB_UP
* PWM_IT_CMPA_DOWNPWM_IT_CMPB_DOWN
* : uint32_t 0 0
* :
******************************************************************************************************************************************/
uint32_t PWM_IntStat(PWM_TypeDef * PWMx, uint32_t it)
{
return (PWMx->IF & it);
}
/******************************************************************************************************************************************
* : PWM_BrkIntEn()
* : 使
* : uint32_t brkit brake interrupt type PWM_BRKIT_BRK0PWM_BRKIT_BRK1PWM_BRKIT_BRK2
* :
* :
******************************************************************************************************************************************/
void PWM_BrkIntEn(uint32_t brkit)
{
PWMG->BRKIE |= brkit;
}
/******************************************************************************************************************************************
* : PWM_BrkIntDis()
* :
* : uint32_t brkit brake interrupt type PWM_BRKIT_BRK0PWM_BRKIT_BRK1PWM_BRKIT_BRK2
* :
* :
******************************************************************************************************************************************/
void PWM_BrkIntDis(uint32_t brkit)
{
PWMG->BRKIE &= ~brkit;
}
/******************************************************************************************************************************************
* : PWM_BrkIntClr()
* :
* : uint32_t brkit brake interrupt type PWM_BRKIT_BRK0PWM_BRKIT_BRK1PWM_BRKIT_BRK2
* :
* :
******************************************************************************************************************************************/
void PWM_BrkIntClr(uint32_t brkit)
{
PWMG->BRKIF = brkit;
}
/******************************************************************************************************************************************
* : PWM_BrkIntStat()
* :
* : uint32_t brkit brake interrupt type PWM_BRKIT_BRK0PWM_BRKIT_BRK1PWM_BRKIT_BRK2
* : uint32_t 0 0
* :
******************************************************************************************************************************************/
uint32_t PWM_BrkIntStat(uint32_t brkit)
{
return (PWMG->BRKIF & brkit);
}

@ -0,0 +1,122 @@
#ifndef __SWM221_PWM_H__
#define __SWM221_PWM_H__
typedef struct {
uint8_t Mode; //PWM_EDGE_ALIGNED、PWM_CENTER_ALIGNED、PWM_ASYM_CENTER_ALIGNED
uint16_t Clkdiv; //1--1024
uint16_t Period; //周期
uint16_t HdutyA; //占空比高电平时长PWM_ASYM_CENTER_ALIGNED 模式下设定前半周期的高电平时长
uint16_t HdutyA2; //只在 PWM_ASYM_CENTER_ALIGNED 模式下使用,用于设定后半周期的高电平时长
uint16_t DeadzoneA; //死区时长取值0--1023
uint8_t IdleLevelA; //停止状态下PWMxA输出电平
uint8_t IdleLevelAN; //停止状态下PWMxAN输出电平
uint8_t OutputInvA; //PWMxA输出取反
uint8_t OutputInvAN; //PWMxAN输出取反
uint16_t HdutyB;
uint16_t HdutyB2;
uint16_t DeadzoneB;
uint8_t IdleLevelB;
uint8_t IdleLevelBN;
uint8_t OutputInvB;
uint8_t OutputInvBN;
uint8_t UpOvfIE; //上升沿计数器溢出中断使能PWM_EDGE_ALIGNED 模式下向上计数,因此只有上升沿
uint8_t DownOvfIE; //下降沿计数器溢出中断使能,另外两种模式下先向上计数、后向下计数,上升沿是前半周期、下降沿是后半周期
uint8_t UpCmpAIE; //上升沿比较器A匹配中断使能
uint8_t DownCmpAIE; //下降沿比较器A匹配中断使能
uint8_t UpCmpBIE; //上升沿比较器B匹配中断使能
uint8_t DownCmpBIE; //下降沿比较器B匹配中断使能
} PWM_InitStructure;
#define PWM_EDGE_ALIGNED 0
#define PWM_CENTER_ALIGNED 1
#define PWM_ASYM_CENTER_ALIGNED 2 // 非对称中心对齐模式,上升沿和下降沿具有不同的翻转点比较值
#define PWM_CH_A 0
#define PWM_CH_B 1
#define PWM0_MSK (1 << 0)
#define PWM1_MSK (1 << 1)
#define PWM_BRK0 (1 << 0)
#define PWM_BRK1 (1 << 1)
#define PWM_BRK2 (1 << 2)
#define PWM_DIR_UP 0
#define PWM_DIR_DOWN 1
#define PWM_TRG_0 0 //计数器溢出或与指定值相等时 PWM 输出触发信号
#define PWM_TRG_1 1
#define PWM_TRG_2 2
#define PWM_TRG_3 3
#define PWM_TRG_4 4
#define PWM_TRG_5 5
#define PWM_TRG_6 6
#define PWM_TRG_7 7
#define PWM_EVT_DIS 0 //外部事件信号为高时 PWM 启动计数、停止计数、暂停计数、屏蔽输出
#define PWM_EVT_0 1
#define PWM_EVT_1 2
#define PWM_EVT_2 3
#define PWM_EVT_3 4
#define PWM_EVT_4 5
#define PWM_EVT_TIMR0 6
#define PWM_EVT_TIMR1 7
/* Interrupt Type */
#define PWM_IT_OVF_UP (1 << 0) //向上计数时计数器溢出PWM_EDGE_ALIGNED 模式下向上计数,因此只有上升沿
#define PWM_IT_OVF_DOWN (1 << 1) //向下计数时计数器溢出,另外两种模式下先向上计数、后向下计数,上升沿是前半周期、下降沿是后半周期
#define PWM_IT_CMPA_UP (1 << 2) //向上计数时计数器值与CMPA相等
#define PWM_IT_CMPB_UP (1 << 3) //向上计数时计数器值与CMPB相等
#define PWM_IT_CMPA_DOWN (1 << 4) //向下计数时计数器值与CMPA相等
#define PWM_IT_CMPB_DOWN (1 << 5) //向下计数时计数器值与CMPB相等
#define PWM_BRKIT_BRK0 (1 << 0) //PWM_BRK0引脚上出现刹车信号
#define PWM_BRKIT_BRK1 (1 << 1)
#define PWM_BRKIT_BRK2 (1 << 2)
void PWM_Init(PWM_TypeDef * PWMx, PWM_InitStructure * initStruct); //PWM初始化
void PWM_Start(uint32_t pwm); //启动PWM开始PWM输出
void PWM_Stop(uint32_t pwm); //关闭PWM停止PWM输出
void PWM_Restart(uint32_t pwm);
void PWM_ReloadEn(uint32_t pwm);
void PWM_ReloadDis(uint32_t pwm);
void PWM_BrkInPolarity(uint32_t brk, uint32_t level);
void PWM_BrkConfig(PWM_TypeDef * PWMx, uint32_t chn, uint32_t brk, uint32_t out, uint32_t outN, uint32_t outHold, uint32_t stpCount);
void PWM_OvfTrigger(PWM_TypeDef * PWMx, uint32_t en_up, uint32_t en_down, uint32_t trig_chn);
void PWM_CmpTrigger(PWM_TypeDef * PWMx, uint16_t match, uint32_t dir, uint32_t width, uint32_t trig_chn, uint32_t trig_interval);
void PWM_OutMask(PWM_TypeDef * PWMx, uint32_t chn, uint32_t evt, uint32_t out, uint32_t evt_n, uint32_t out_n);
void PWM_SetPeriod(PWM_TypeDef * PWMx, uint16_t period); //设置周期
uint16_t PWM_GetPeriod(PWM_TypeDef * PWMx); //获取周期
void PWM_SetHDuty(PWM_TypeDef * PWMx, uint32_t chn, uint16_t hduty); //设置高电平时长
uint16_t PWM_GetHDuty(PWM_TypeDef * PWMx, uint32_t chn); //获取高电平时长
void PWM_SetHDuty2(PWM_TypeDef * PWMx, uint32_t chn, uint16_t hduty, uint16_t hduty2); //设置高电平时长,用于非对称中心对齐模式
void PWM_GetHDuty2(PWM_TypeDef * PWMx, uint32_t chn, uint16_t *hduty, uint16_t *hduty2); //获取高电平时长,用于非对称中心对齐模式
void PWM_SetDeadzone(PWM_TypeDef * PWMx, uint32_t chn, uint16_t deadzone); //设置死区时长
uint16_t PWM_GetDeadzone(PWM_TypeDef * PWMx, uint32_t chn); //获取死区时长
void PWM_IntEn(PWM_TypeDef * PWMx, uint32_t it); //中断使能
void PWM_IntDis(PWM_TypeDef * PWMx, uint32_t it); //中断禁能
void PWM_IntClr(PWM_TypeDef * PWMx, uint32_t it); //中断标志清除
uint32_t PWM_IntStat(PWM_TypeDef * PWMx, uint32_t it); //中断标志查询
void PWM_BrkIntEn(uint32_t brkit); //刹车中断使能
void PWM_BrkIntDis(uint32_t brkit); //刹车中断禁能
void PWM_BrkIntClr(uint32_t brkit); //刹车中断标志清除
uint32_t PWM_BrkIntStat(uint32_t brkit); //刹车中断标志查询
#endif //__SWM221_PWM_H__

@ -0,0 +1,146 @@
/******************************************************************************************************************************************
* : SWM221_qei.c
* : SWM221QEI
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.0.0 20130630
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM221.h"
#include "SWM221_qei.h"
/******************************************************************************************************************************************
* : QEI_Init()
* : QEI
* : QEI_TypeDef * QEIx QEI
* QEI_InitStructure * initStruct
* :
* :
******************************************************************************************************************************************/
void QEI_Init(QEI_TypeDef * QEIx,QEI_InitStructure * initStruct)
{
switch((uint32_t)QEIx)
{
case ((uint32_t)QEI):
SYS->CLKEN0 |= (1 << SYS_CLKEN0_QEI_Pos);
break;
}
QEI_Stop(QEIx); //配置前关闭QEI模块
QEIx->CR = (initStruct->swapAB << QEI_CR_ABSWAP_Pos) |
(initStruct->mode << QEI_CR_X2X4_Pos) |
(1 << QEI_CR_RSTSRC_Pos) |
(1 << QEI_CR_MODE_Pos);
QEIx->POSCNT = 0;
QEIx->MAXCNT = initStruct->maxcnt;
QEIx->IC = 0x0F;
QEIx->IE = 0x0F;
QEIx->IM = (initStruct->intINDEXEn << QEI_IM_INDEX_Pos) |
(initStruct->intMATCHEn << QEI_IM_MATCH_Pos) |
(initStruct->intCNTOVEn << QEI_IM_CNTOV_Pos) |
(initStruct->intERROREn << QEI_IM_ERROR_Pos);
if(initStruct->intINDEXEn | initStruct->intMATCHEn | initStruct->intCNTOVEn | initStruct->intERROREn)
{
NVIC_EnableIRQ(GPIOB4_GPIOB10_QEI_IRQn);
}
}
/******************************************************************************************************************************************
* : QEI_Start()
* : QEI
* : QEI_TypeDef * QEIx QEI
* :
* :
******************************************************************************************************************************************/
void QEI_Start(QEI_TypeDef * QEIx)
{
QEIx->CR |= (1 << QEI_CR_ENA_Pos);
}
/******************************************************************************************************************************************
* : QEI_Stop()
* : QEI
* : QEI_TypeDef * QEIx QEI
* :
* :
******************************************************************************************************************************************/
void QEI_Stop(QEI_TypeDef * QEIx)
{
QEIx->CR &= ~(1 << QEI_CR_ENA_Pos);
}
/******************************************************************************************************************************************
* : QEI_IntEn()
* : QEI使
* : QEI_TypeDef * QEIx QEI
* uint32_t it interrupt typeQEI_IT_INDEXQEI_IT_MATCHQEI_IT_CNTOVQEI_IT_ERROR
* :
* :
******************************************************************************************************************************************/
void QEI_IntEn(QEI_TypeDef * QEIx, uint32_t it)
{
QEIx->IM |= it;
switch((uint32_t)QEIx)
{
case ((uint32_t)QEI):
NVIC_EnableIRQ(GPIOB4_GPIOB10_QEI_IRQn);
break;
}
}
/******************************************************************************************************************************************
* : QEI_IntDis()
* : QEI
* : QEI_TypeDef * QEIx QEI
* uint32_t it interrupt typeQEI_IT_INDEXQEI_IT_MATCHQEI_IT_CNTOVQEI_IT_ERROR
* :
* :
******************************************************************************************************************************************/
void QEI_IntDis(QEI_TypeDef * QEIx, uint32_t it)
{
QEIx->IM &= ~it;
}
/******************************************************************************************************************************************
* : QEI_IntClr()
* : QEI
* : QEI_TypeDef * QEIx QEI
* uint32_t it interrupt typeQEI_IT_INDEXQEI_IT_MATCHQEI_IT_CNTOVQEI_IT_ERROR
* :
* :
******************************************************************************************************************************************/
void QEI_IntClr(QEI_TypeDef * QEIx, uint32_t it)
{
QEIx->IC = it;
}
/******************************************************************************************************************************************
* : QEI_IntStat()
* : QEI
* : QEI_TypeDef * QEIx QEI
* uint32_t it interrupt typeQEI_IT_INDEXQEI_IT_MATCHQEI_IT_CNTOVQEI_IT_ERROR
* : uint32_t 0 0
* :
******************************************************************************************************************************************/
uint32_t QEI_IntStat(QEI_TypeDef * QEIx, uint32_t it)
{
return (QEIx->IF & it);
}

@ -0,0 +1,37 @@
#ifndef __SWM221_QEI_H__
#define __SWM221_QEI_H__
typedef struct {
uint8_t mode; //QEI_MODE_X2、QEI_MODE_X4
uint16_t maxcnt; //最大计数值
uint8_t swapAB; //1 交换A、B引脚
uint8_t intINDEXEn; //检测到Index脉冲中断使能
uint8_t intMATCHEn; //POSCNT递增到与MAXCNT相等或POSCNT从MAXCNT递减到0中断使能
uint8_t intCNTOVEn; //Counter Overrun计数器溢出中断使能
uint8_t intERROREn; //计数器错误中断使能
} QEI_InitStructure;
#define QEI_MODE_X2 0
#define QEI_MODE_X4 1
#define QEI_IT_INDEX (1 << 0)
#define QEI_IT_MATCH (1 << 1)
#define QEI_IT_CNTOV (1 << 2)
#define QEI_IT_ERROR (1 << 3)
void QEI_Init(QEI_TypeDef * QEIx, QEI_InitStructure * initStruct); //QEI初始化
void QEI_Start(QEI_TypeDef * QEIx); //启动QEI
void QEI_Stop(QEI_TypeDef * QEIx); //关闭QEI
uint32_t QEI_IndexLvl(QEI_TypeDef * QEIx); //QEI Index引脚电平
uint32_t QEI_CountDir(QEI_TypeDef * QEIx); //QEI计数方向0 反向计数 1 正向计数
void QEI_IntEn(QEI_TypeDef * QEIx, uint32_t it); //QEI中断使能
void QEI_IntDis(QEI_TypeDef * QEIx, uint32_t it); //QEI中断关闭
void QEI_IntClr(QEI_TypeDef * QEIx, uint32_t it); //QEI中断标志清除
uint32_t QEI_IntStat(QEI_TypeDef * QEIx, uint32_t it); //QEI中断状态查询
#endif //__SWM221_QEI_H__

@ -0,0 +1,734 @@
/******************************************************************************************************************************************
* : SWM342_qspi.c
* : SWM342QSPI
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.1.0 20171025
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM221.h"
#include "SWM221_qspi.h"
static uint8_t AddressSize;
/******************************************************************************************************************************************
* : QSPI_Init()
* : QSPI
* : QSPI_TypeDef * QSPIx QSPIQSPI0
* QSPI_InitStructure * initStruct QSPI
* :
* :
******************************************************************************************************************************************/
void QSPI_Init(QSPI_TypeDef * QSPIx, QSPI_InitStructure * initStruct)
{
switch((uint32_t)QSPIx)
{
case ((uint32_t)QSPI0):
SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_QSPI0_Pos);
break;
}
QSPI_Close(QSPIx);
QSPIx->CR = (0 << QSPI_CR_SSHIFT_Pos) |
(7 << QSPI_CR_FFTHR_Pos) |
(initStruct->IntEn << QSPI_CR_ERRIE_Pos) |
((initStruct->ClkDiv-1) << QSPI_CR_CLKDIV_Pos);
QSPIx->DCR = (initStruct->ClkMode << QSPI_DCR_CLKMOD_Pos) |
(3 << QSPI_DCR_CSHIGH_Pos) |
(initStruct->Size << QSPI_DCR_FLSIZE_Pos);
AddressSize = initStruct->Size / 8;
QSPIx->SSHIFT = ((initStruct->SampleShift & 0x0F) << QSPI_SSHIFT_CYCLE_Pos) |
(2 << QSPI_SSHIFT_SPACE_Pos);
QSPIx->FCR = 0x1B;
if(initStruct->IntEn)
{
switch((uint32_t)QSPIx)
{
case ((uint32_t)QSPI0): NVIC_EnableIRQ(QSPI0_IRQn); break;
}
}
}
/******************************************************************************************************************************************
* : QSPI_Open()
* : QSPI
* : QSPI_TypeDef * QSPIx QSPIQSPI0
* :
* :
******************************************************************************************************************************************/
void QSPI_Open(QSPI_TypeDef * QSPIx)
{
QSPIx->CR |= QSPI_CR_EN_Msk;
}
/******************************************************************************************************************************************
* : QSPI_Close()
* : QSPI
* : QSPI_TypeDef * QSPIx QSPIQSPI0
* :
* :
******************************************************************************************************************************************/
void QSPI_Close(QSPI_TypeDef * QSPIx)
{
QSPIx->CR &= ~QSPI_CR_EN_Msk;
}
void QSPI_CmdStructClear(QSPI_CmdStructure * cmdStruct)
{
cmdStruct->Instruction = 0;
cmdStruct->InstructionMode = 0;
cmdStruct->Address = 0;
cmdStruct->AddressMode = 0;
cmdStruct->AddressSize = 0;
cmdStruct->AlternateBytes = 0;
cmdStruct->AlternateBytesMode = 0;
cmdStruct->AlternateBytesSize = 0;
cmdStruct->DummyCycles = 0;
cmdStruct->DataMode = 0;
cmdStruct->DataCount = 0;
cmdStruct->SendInstOnlyOnce = 0;
}
/******************************************************************************************************************************************
* : QSPI_Command()
* : QSPI
* : QSPI_TypeDef * QSPIx QSPIQSPI0
* QSPI_CmdStructure * cmdStruct
* :
* :
******************************************************************************************************************************************/
void QSPI_Command(QSPI_TypeDef * QSPIx, uint8_t cmdMode, QSPI_CmdStructure * cmdStruct)
{
if(cmdStruct->AlternateBytesMode != QSPI_PhaseMode_None)
QSPIx->ABR = cmdStruct->AlternateBytes;
if(cmdStruct->DataMode != QSPI_PhaseMode_None)
QSPIx->DLR = cmdStruct->DataCount - 1;
QSPIx->CCR = (cmdStruct->Instruction << QSPI_CCR_CODE_Pos) |
(cmdStruct->InstructionMode << QSPI_CCR_IMODE_Pos) |
(cmdStruct->AddressMode << QSPI_CCR_AMODE_Pos) |
(cmdStruct->AddressSize << QSPI_CCR_ASIZE_Pos) |
(cmdStruct->AlternateBytesMode << QSPI_CCR_ABMODE_Pos) |
(cmdStruct->AlternateBytesSize << QSPI_CCR_ABSIZE_Pos) |
(cmdStruct->DummyCycles << QSPI_CCR_DUMMY_Pos) |
(cmdStruct->DataMode << QSPI_CCR_DMODE_Pos) |
(cmdMode << QSPI_CCR_MODE_Pos) |
(cmdStruct->SendInstOnlyOnce << QSPI_CCR_SIOO_Pos);
if(cmdStruct->AddressMode != QSPI_PhaseMode_None)
QSPIx->AR = cmdStruct->Address;
for(int i = 0; i < 3; i++) __NOP();
}
/******************************************************************************************************************************************
* : QSPI_Erase_()
* : QSPI Flash
* : QSPI_TypeDef * QSPIx QSPIQSPI0
* uint32_t addr SPI Flash
* uint16_t block_size kbytes 464
* uint8_t wait SPI Flash 1 0
* :
* : wait == 0 QSPI_FlashBusy() SPI Flash
******************************************************************************************************************************************/
void QSPI_Erase_(QSPI_TypeDef * QSPIx, uint32_t addr, uint16_t block_size, uint8_t wait)
{
QSPI_CmdStructure cmdStruct;
QSPI_CmdStructClear(&cmdStruct);
uint8_t instruction;
switch(block_size)
{
case 4:
instruction = (AddressSize == QSPI_PhaseSize_32bit) ? QSPI_C4B_ERASE_SECTOR : QSPI_CMD_ERASE_SECTOR;
break;
case 64:
instruction = (AddressSize == QSPI_PhaseSize_32bit) ? QSPI_C4B_ERASE_BLOCK64KB : QSPI_CMD_ERASE_BLOCK64KB;
break;
}
cmdStruct.InstructionMode = QSPI_PhaseMode_1bit;
cmdStruct.Instruction = instruction;
cmdStruct.AddressMode = QSPI_PhaseMode_1bit;
cmdStruct.AddressSize = AddressSize;
cmdStruct.Address = addr;
cmdStruct.AlternateBytesMode = QSPI_PhaseMode_None;
cmdStruct.DummyCycles = 0;
cmdStruct.DataMode = QSPI_PhaseMode_None;
QSPI_WriteEnable(QSPIx);
QSPI_Command(QSPIx, QSPI_Mode_IndirectWrite, &cmdStruct);
while(QSPI_Busy(QSPIx)) __NOP();
if(wait)
while(QSPI_FlashBusy(QSPIx)) __NOP();
}
/******************************************************************************************************************************************
* : QSPI_Write_()
* : QSPI Flash
* : QSPI_TypeDef * QSPIx QSPIQSPI0
* uint32_t addr SPI Flash
* uint8_t buff[] SPI Flash
* uint32_t count SPI Flash 256
* uint8_t data_width 使线 14
* uint8_t data_phase DMA
* :
* :
******************************************************************************************************************************************/
void QSPI_Write_(QSPI_TypeDef * QSPIx, uint32_t addr, uint8_t buff[], uint32_t count, uint8_t data_width, uint8_t data_phase)
{
QSPI_CmdStructure cmdStruct;
QSPI_CmdStructClear(&cmdStruct);
uint8_t instruction, dataMode;
switch(data_width)
{
case 1:
instruction = (AddressSize == QSPI_PhaseSize_32bit) ? QSPI_C4B_PAGE_PROGRAM : QSPI_CMD_PAGE_PROGRAM;
dataMode = QSPI_PhaseMode_1bit;
break;
case 4:
instruction = (AddressSize == QSPI_PhaseSize_32bit) ? QSPI_C4B_PAGE_PROGRAM_4bit : QSPI_CMD_PAGE_PROGRAM_4bit;
dataMode = QSPI_PhaseMode_4bit;
break;
}
cmdStruct.InstructionMode = QSPI_PhaseMode_1bit;
cmdStruct.Instruction = instruction;
cmdStruct.AddressMode = QSPI_PhaseMode_1bit;
cmdStruct.AddressSize = AddressSize;
cmdStruct.Address = addr;
cmdStruct.AlternateBytesMode = QSPI_PhaseMode_None;
cmdStruct.DummyCycles = 0;
cmdStruct.DataMode = dataMode;
cmdStruct.DataCount = count;
QSPI_WriteEnable(QSPIx);
QSPI_Command(QSPIx, QSPI_Mode_IndirectWrite, &cmdStruct);
if(data_phase == 0)
return;
if((uint32_t)buff % 4 == 0) // word aligned
{
uint32_t n_word = count / 4;
for(int i = 0; i < n_word; i++)
{
uint32_t * p_word = (uint32_t *)buff;
while(QSPI_FIFOSpace(QSPIx) < 4) __NOP();
QSPIx->DRW = p_word[i];
}
if((count % 4) / 2)
{
uint16_t * p_half = (uint16_t *)&buff[n_word * 4];
while(QSPI_FIFOSpace(QSPIx) < 2) __NOP();
QSPIx->DRH = p_half[0];
}
if(count % 2)
{
while(QSPI_FIFOSpace(QSPIx) < 1) __NOP();
QSPIx->DRB = buff[count - 1];
}
}
else
{
for(int i = 0; i < count; i++)
{
while(QSPI_FIFOSpace(QSPIx) < 1) __NOP();
QSPIx->DRB = buff[i];
}
}
while(QSPI_Busy(QSPIx)) __NOP();
while(QSPI_FlashBusy(QSPIx)) __NOP();
}
/******************************************************************************************************************************************
* : QSPI_Read_()
* : QSPI Flash
* : QSPI_TypeDef * QSPIx QSPIQSPI0
* uint32_t addr SPI Flash
* uint8_t buff[]
* uint32_t count
* uint8_t addr_width 使线 124
* uint8_t data_width 使线 124
* uint8_t data_phase DMA
* :
* :
******************************************************************************************************************************************/
void QSPI_Read_(QSPI_TypeDef * QSPIx, uint32_t addr, uint8_t buff[], uint32_t count, uint8_t addr_width, uint8_t data_width, uint8_t data_phase)
{
QSPI_CmdStructure cmdStruct;
QSPI_CmdStructClear(&cmdStruct);
uint8_t instruction, addressMode, dataMode, dummyCycles;
uint8_t alternateBytesMode, alternateBytesSize, alternateBytes;
switch((addr_width << 4) | data_width)
{
case 0x11:
instruction = (AddressSize == QSPI_PhaseSize_32bit) ? QSPI_C4B_FAST_READ : QSPI_CMD_FAST_READ;
addressMode = QSPI_PhaseMode_1bit;
alternateBytesMode = QSPI_PhaseMode_None;
alternateBytesSize = 0;
dummyCycles = 8;
dataMode = QSPI_PhaseMode_1bit;
break;
case 0x12:
instruction = (AddressSize == QSPI_PhaseSize_32bit) ? QSPI_C4B_FAST_READ_2bit : QSPI_CMD_FAST_READ_2bit;
addressMode = QSPI_PhaseMode_1bit;
alternateBytesMode = QSPI_PhaseMode_None;
alternateBytesSize = 0;
dummyCycles = 8;
dataMode = QSPI_PhaseMode_2bit;
break;
case 0x22:
instruction = (AddressSize == QSPI_PhaseSize_32bit) ? QSPI_C4B_FAST_READ_IO2bit : QSPI_CMD_FAST_READ_IO2bit;
addressMode = QSPI_PhaseMode_2bit;
alternateBytesMode = QSPI_PhaseMode_2bit;
alternateBytesSize = QSPI_PhaseSize_8bit;
alternateBytes = 0xFF;
dummyCycles = 0;
dataMode = QSPI_PhaseMode_2bit;
break;
case 0x14:
instruction = (AddressSize == QSPI_PhaseSize_32bit) ? QSPI_C4B_FAST_READ_4bit : QSPI_CMD_FAST_READ_4bit;
addressMode = QSPI_PhaseMode_1bit;
alternateBytesMode = QSPI_PhaseMode_None;
alternateBytesSize = 0;
dummyCycles = 8;
dataMode = QSPI_PhaseMode_4bit;
break;
case 0x44:
instruction = (AddressSize == QSPI_PhaseSize_32bit) ? QSPI_C4B_FAST_READ_IO4bit : QSPI_CMD_FAST_READ_IO4bit;
addressMode = QSPI_PhaseMode_4bit;
alternateBytesMode = QSPI_PhaseMode_4bit;
alternateBytesSize = QSPI_PhaseSize_8bit;
alternateBytes = 0xFF;
dummyCycles = 4;
dataMode = QSPI_PhaseMode_4bit;
break;
}
cmdStruct.InstructionMode = QSPI_PhaseMode_1bit;
cmdStruct.Instruction = instruction;
cmdStruct.AddressMode = addressMode;
cmdStruct.AddressSize = AddressSize;
cmdStruct.Address = addr;
cmdStruct.AlternateBytesMode = alternateBytesMode;
cmdStruct.AlternateBytesSize = alternateBytesSize;
cmdStruct.AlternateBytes = alternateBytes;
cmdStruct.DummyCycles = dummyCycles;
cmdStruct.DataMode = dataMode;
cmdStruct.DataCount = count;
QSPI_Command(QSPIx, QSPI_Mode_IndirectRead, &cmdStruct);
if(data_phase == 0)
return;
if((uint32_t)buff % 4 == 0) // word aligned
{
uint32_t n_word = count / 4;
for(int i = 0; i < n_word; i++)
{
uint32_t * p_word = (uint32_t *)buff;
while(QSPI_FIFOCount(QSPIx) < 4) __NOP();
p_word[i] = QSPIx->DRW;
}
if((count % 4) / 2)
{
uint16_t * p_half = (uint16_t *)&buff[n_word * 4];
while(QSPI_FIFOCount(QSPIx) < 2) __NOP();
p_half[0] = QSPIx->DRH;
}
if(count % 2)
{
while(QSPI_FIFOCount(QSPIx) < 1) __NOP();
buff[count - 1] = QSPIx->DRB;
}
}
else
{
for(int i = 0; i < count; i++)
{
while(QSPI_FIFOCount(QSPIx) < 1) __NOP();
buff[i] = QSPIx->DRB;
}
}
QSPI_Abort(QSPIx);
}
/******************************************************************************************************************************************
* : QSPI_FlashBusy()
* : QSPI Flash
* : QSPI_TypeDef * QSPIx QSPIQSPI0
* : bool SPI Flash
* :
******************************************************************************************************************************************/
bool QSPI_FlashBusy(QSPI_TypeDef * QSPIx)
{
uint16_t reg = QSPI_ReadReg(QSPIx, QSPI_CMD_READ_STATUS_REG1, 1);
bool busy = (reg & (1 << QSPI_STATUS_REG1_BUSY_Pos));
return busy;
}
/******************************************************************************************************************************************
* : QSPI_QuadState()
* : QSPI Flash QE
* : QSPI_TypeDef * QSPIx QSPIQSPI0
* : uint8_t 1 QE 使 0 QE
* : SPI Flash QE Status Register
******************************************************************************************************************************************/
uint8_t QSPI_QuadState(QSPI_TypeDef * QSPIx)
{
uint8_t reg = QSPI_ReadReg(QSPIx, QSPI_CMD_READ_STATUS_REG2, 1);
return (reg & (1 << QSPI_STATUS_REG2_QUAD_Pos)) ? 1 : 0;
}
/******************************************************************************************************************************************
* : QSPI_QuadSwitch()
* : QSPI Flash QE
* : QSPI_TypeDef * QSPIx QSPIQSPI0
* uint8_t on 1 QE 使 0 QE
* :
* : SPI Flash QE Status Register
******************************************************************************************************************************************/
void QSPI_QuadSwitch(QSPI_TypeDef * QSPIx, uint8_t on)
{
uint8_t reg = QSPI_ReadReg(QSPIx, QSPI_CMD_READ_STATUS_REG2, 1);
if(on)
reg |= (1 << QSPI_STATUS_REG2_QUAD_Pos);
else
reg &= ~(1 << QSPI_STATUS_REG2_QUAD_Pos);
QSPI_WriteEnable(QSPIx);
QSPI_WriteReg(QSPIx, QSPI_CMD_WRITE_STATUS_REG2, reg, 1);
while(QSPI_FlashBusy(QSPIx)) __NOP();
}
/******************************************************************************************************************************************
* : QSPI_ReadReg()
* : QSPI Flash 4
* : QSPI_TypeDef * QSPIx QSPIQSPI0
* uint8_t cmd
* uint8_t n_bytes 1234
* : uint32_t MSB
* :
******************************************************************************************************************************************/
uint32_t QSPI_ReadReg(QSPI_TypeDef * QSPIx, uint8_t cmd, uint8_t n_bytes)
{
QSPI_CmdStructure cmdStruct;
QSPI_CmdStructClear(&cmdStruct);
cmdStruct.InstructionMode = QSPI_PhaseMode_1bit;
cmdStruct.Instruction = cmd;
cmdStruct.AddressMode = QSPI_PhaseMode_None;
cmdStruct.AlternateBytesMode = QSPI_PhaseMode_None;
cmdStruct.DummyCycles = 0;
cmdStruct.DataMode = QSPI_PhaseMode_1bit;
cmdStruct.DataCount = n_bytes;
QSPI_Command(QSPIx, QSPI_Mode_IndirectRead, &cmdStruct);
while(QSPI_FIFOCount(QSPIx) < n_bytes) __NOP();
uint32_t data = 0;
for(int i = n_bytes; i > 0; i--)
((uint8_t *)&data)[i-1] = QSPIx->DRB;
return data;
}
/******************************************************************************************************************************************
* : QSPI_WriteReg()
* : QSPI Flash 4
* : QSPI_TypeDef * QSPIx QSPIQSPI0
* uint8_t cmd
* uint32_t data MSB
* uint8_t n_bytes 12340
* :
* :
******************************************************************************************************************************************/
void QSPI_WriteReg(QSPI_TypeDef * QSPIx, uint8_t cmd, uint32_t data, uint8_t n_bytes)
{
QSPI_CmdStructure cmdStruct;
QSPI_CmdStructClear(&cmdStruct);
cmdStruct.InstructionMode = QSPI_PhaseMode_1bit;
cmdStruct.Instruction = cmd;
cmdStruct.AddressMode = QSPI_PhaseMode_None;
cmdStruct.AlternateBytesMode = QSPI_PhaseMode_None;
cmdStruct.DummyCycles = 0;
cmdStruct.DataMode = n_bytes ? QSPI_PhaseMode_1bit : QSPI_PhaseMode_None;
cmdStruct.DataCount = n_bytes;
QSPI_Command(QSPIx, QSPI_Mode_IndirectWrite, &cmdStruct);
for(int i = n_bytes; i > 0; i--)
QSPIx->DRB = ((uint8_t *)&data)[i-1];
while(QSPI_Busy(QSPIx)) __NOP();
}
/******************************************************************************************************************************************
* : QSPI_INTEn()
* : 使
* : QSPI_TypeDef * QSPIx QSPIQSPI0
* uint32_t it interrupt type QSPI_IT_ERRQSPI_IT_DONEQSPI_IT_FFTHRQSPI_IT_PSMATQSPI_IT_TO
* :
* :
******************************************************************************************************************************************/
void QSPI_INTEn(QSPI_TypeDef * QSPIx, uint32_t it)
{
QSPIx->CR |= (it << 16);
}
/******************************************************************************************************************************************
* : QSPI_INTDis()
* :
* : QSPI_TypeDef * QSPIx QSPIQSPI0
* uint32_t it interrupt type QSPI_IT_ERRQSPI_IT_DONEQSPI_IT_FFTHRQSPI_IT_PSMATQSPI_IT_TO
* :
* :
******************************************************************************************************************************************/
void QSPI_INTDis(QSPI_TypeDef * QSPIx, uint32_t it)
{
QSPIx->CR &= ~(it << 16);
}
/******************************************************************************************************************************************
* : QSPI_INTClr()
* :
* : QSPI_TypeDef * QSPIx QSPIQSPI0
* uint32_t it interrupt type QSPI_IT_ERRQSPI_IT_DONEQSPI_IT_PSMATQSPI_IT_TO
* :
* :
******************************************************************************************************************************************/
void QSPI_INTClr(QSPI_TypeDef * QSPIx, uint32_t it)
{
QSPIx->FCR = it;
}
/******************************************************************************************************************************************
* : QSPI_INTStat()
* :
* : QSPI_TypeDef * QSPIx QSPIQSPI0
* uint32_t it interrupt type QSPI_IT_ERRQSPI_IT_DONEQSPI_IT_FFTHRQSPI_IT_PSMATQSPI_IT_TO
* : uint32_t 0 0
* :
******************************************************************************************************************************************/
uint32_t QSPI_INTStat(QSPI_TypeDef * QSPIx, uint32_t it)
{
return QSPIx->SR & it;
}
/******************************************************************************************************************************************
* : QSPI_SPI_Write_()
* : QSPI SPI
* : QSPI_TypeDef * QSPIx QSPIQSPI0
* uint8_t buff[]
* uint32_t count
* uint8_t data_width 使线 124
* uint8_t data_phase DMA
* :
* :
******************************************************************************************************************************************/
void QSPI_SPI_Write_(QSPI_TypeDef * QSPIx, uint8_t buff[], uint32_t count, uint8_t data_width, uint8_t data_phase)
{
QSPI_CmdStructure cmdStruct;
QSPI_CmdStructClear(&cmdStruct);
cmdStruct.InstructionMode = QSPI_PhaseMode_None;
cmdStruct.AddressMode = QSPI_PhaseMode_None;
cmdStruct.AlternateBytesMode = QSPI_PhaseMode_None;
cmdStruct.DummyCycles = 0;
cmdStruct.DataMode = (data_width == 1) ? QSPI_PhaseMode_1bit : ((data_width == 2) ? QSPI_PhaseMode_2bit : QSPI_PhaseMode_4bit);
cmdStruct.DataCount = count;
QSPI_Command(QSPIx, QSPI_Mode_IndirectWrite, &cmdStruct);
if(data_phase == 0)
return;
if((uint32_t)buff % 4 == 0) // word aligned
{
uint32_t n_word = count / 4;
for(int i = 0; i < n_word; i++)
{
uint32_t * p_word = (uint32_t *)buff;
while(QSPI_FIFOSpace(QSPIx) < 4) __NOP();
QSPIx->DRW = p_word[i];
}
if((count % 4) / 2)
{
uint16_t * p_half = (uint16_t *)&buff[n_word * 4];
while(QSPI_FIFOSpace(QSPIx) < 2) __NOP();
QSPIx->DRH = p_half[0];
}
if(count % 2)
{
while(QSPI_FIFOSpace(QSPIx) < 1) __NOP();
QSPIx->DRB = buff[count - 1];
}
}
else
{
for(int i = 0; i < count; i++)
{
while(QSPI_FIFOSpace(QSPIx) < 1) __NOP();
QSPIx->DRB = buff[i];
}
}
while(QSPI_Busy(QSPIx)) __NOP();
}
/******************************************************************************************************************************************
* : QSPI_SPI_Read_()
* : QSPI SPI
* : QSPI_TypeDef * QSPIx QSPIQSPI0
* uint8_t buff[]
* uint32_t count
* uint8_t data_width 使线 124
* uint8_t data_phase DMA
* :
* :
******************************************************************************************************************************************/
void QSPI_SPI_Read_(QSPI_TypeDef * QSPIx, uint8_t buff[], uint32_t count, uint8_t data_width, uint8_t data_phase)
{
QSPI_CmdStructure cmdStruct;
QSPI_CmdStructClear(&cmdStruct);
cmdStruct.InstructionMode = QSPI_PhaseMode_None;
cmdStruct.AddressMode = QSPI_PhaseMode_None;
cmdStruct.AlternateBytesMode = QSPI_PhaseMode_None;
cmdStruct.DummyCycles = 0;
cmdStruct.DataMode = (data_width == 1) ? QSPI_PhaseMode_1bit : ((data_width == 2) ? QSPI_PhaseMode_2bit : QSPI_PhaseMode_4bit);
cmdStruct.DataCount = count;
QSPI_Command(QSPIx, QSPI_Mode_IndirectRead, &cmdStruct);
if(data_phase == 0)
return;
if((uint32_t)buff % 4 == 0) // word aligned
{
uint32_t n_word = count / 4;
for(int i = 0; i < n_word; i++)
{
uint32_t * p_word = (uint32_t *)buff;
while(QSPI_FIFOCount(QSPIx) < 4) __NOP();
p_word[i] = QSPIx->DRW;
}
if((count % 4) / 2)
{
uint16_t * p_half = (uint16_t *)&buff[n_word * 4];
while(QSPI_FIFOCount(QSPIx) < 2) __NOP();
p_half[0] = QSPIx->DRH;
}
if(count % 2)
{
while(QSPI_FIFOCount(QSPIx) < 1) __NOP();
buff[count - 1] = QSPIx->DRB;
}
}
else
{
for(int i = 0; i < count; i++)
{
while(QSPI_FIFOCount(QSPIx) < 1) __NOP();
buff[i] = QSPIx->DRB;
}
}
QSPI_Abort(QSPIx);
}

@ -0,0 +1,215 @@
#ifndef __SWM221_QSPI_H__
#define __SWM221_QSPI_H__
typedef struct {
uint16_t Size; // Flash 大小
uint16_t ClkDiv; // 可取值 2--256
uint8_t ClkMode; // 可取值 QSPI_ClkMode_0、QSPI_ClkMode_3
uint8_t SampleShift; // 可取值 QSPI_SampleShift_None、QSPI_SampleShift_1_SYSCLK、...
uint8_t IntEn; // 可取值 QSPI_IT_ERR、QSPI_IT_DONE、QSPI_IT_FFTHR、QSPI_IT_PSMAT、QSPI_IT_TO 及其“或”
} QSPI_InitStructure;
#define QSPI_Size_1MB 19
#define QSPI_Size_2MB 20
#define QSPI_Size_4MB 21
#define QSPI_Size_8MB 22
#define QSPI_Size_16MB 23
#define QSPI_Size_32MB 24
#define QSPI_Size_64MB 25
#define QSPI_Size_128MB 26
#define QSPI_Size_256MB 27
#define QSPI_Size_512MB 28
#define QSPI_ClkMode_0 0
#define QSPI_ClkMode_3 1
#define QSPI_SampleShift_NONE 0
#define QSPI_SampleShift_1_SYSCLK 1
#define QSPI_SampleShift_2_SYSCLK 2
#define QSPI_SampleShift_3_SYSCLK 3
#define QSPI_SampleShift_4_SYSCLK 4
#define QSPI_SampleShift_5_SYSCLK 5
#define QSPI_SampleShift_6_SYSCLK 6
#define QSPI_SampleShift_7_SYSCLK 7
typedef struct {
uint8_t Instruction; // 指令码
uint8_t InstructionMode; // 可取值QSPI_PhaseMode_None、QSPI_PhaseMode_1bit、QSPI_PhaseMode_2bit、QSPI_PhaseMode_4bit
uint32_t Address;
uint8_t AddressMode; // 可取值QSPI_PhaseMode_None、QSPI_PhaseMode_1bit、QSPI_PhaseMode_2bit、QSPI_PhaseMode_4bit
uint8_t AddressSize; // 可取值QSPI_PhaseSize_8bit、QSPI_PhaseSize_16bit、QSPI_PhaseSize_24bit、QSPI_PhaseSize_32bit
uint32_t AlternateBytes;
uint8_t AlternateBytesMode; // 可取值QSPI_PhaseMode_None、QSPI_PhaseMode_1bit、QSPI_PhaseMode_2bit、QSPI_PhaseMode_4bit
uint8_t AlternateBytesSize; // 可取值QSPI_PhaseSize_8bit、QSPI_PhaseSize_16bit、QSPI_PhaseSize_24bit、QSPI_PhaseSize_32bit
uint8_t DummyCycles; // 可取值0--31
uint8_t DataMode; // 可取值QSPI_PhaseMode_None、QSPI_PhaseMode_1bit、QSPI_PhaseMode_2bit、QSPI_PhaseMode_4bit
uint32_t DataCount; // 要读写数据的字节个数0 表示一直读写直到存储器末尾
uint8_t SendInstOnlyOnce;
} QSPI_CmdStructure;
#define QSPI_PhaseMode_None 0 // there is no this phase
#define QSPI_PhaseMode_1bit 1 // 单线传输
#define QSPI_PhaseMode_2bit 2 // 双线传输
#define QSPI_PhaseMode_4bit 3 // 四线传输
#define QSPI_PhaseSize_8bit 0
#define QSPI_PhaseSize_16bit 1
#define QSPI_PhaseSize_24bit 2
#define QSPI_PhaseSize_32bit 3
#define QSPI_Mode_IndirectWrite 0
#define QSPI_Mode_IndirectRead 1
#define QSPI_Mode_AutoPolling 2
#define QSPI_CMD_READ_JEDEC 0x9F
#define QSPI_CMD_FAST_READ 0x0B
#define QSPI_CMD_FAST_READ_2bit 0x3B
#define QSPI_CMD_FAST_READ_IO2bit 0xBB
#define QSPI_CMD_FAST_READ_4bit 0x6B
#define QSPI_CMD_FAST_READ_IO4bit 0xEB
#define QSPI_CMD_WRITE_ENABLE 0x06
#define QSPI_CMD_WRITE_DISABLE 0x04
#define QSPI_CMD_PAGE_PROGRAM 0x02
#define QSPI_CMD_PAGE_PROGRAM_4bit 0x32
#define QSPI_CMD_ERASE_CHIP 0x60
#define QSPI_CMD_ERASE_SECTOR 0x20
#define QSPI_CMD_ERASE_BLOCK32KB 0x52
#define QSPI_CMD_ERASE_BLOCK64KB 0xD8
#define QSPI_CMD_READ_STATUS_REG1 0x05
#define QSPI_CMD_READ_STATUS_REG2 0x35
#define QSPI_CMD_READ_STATUS_REG3 0x15
#define QSPI_CMD_WRITE_STATUS_REG1 0x01
#define QSPI_CMD_WRITE_STATUS_REG2 0x31
#define QSPI_CMD_WRITE_STATUS_REG3 0x11
#define QSPI_CMD_WRITE_EXT_ADDR 0xC5 // Write Extended Address Register
#define QSPI_CMD_READ_EXT_ADDR 0xC8
#define QSPI_CMD_4BYTE_ADDR_ENTER 0xB7
#define QSPI_CMD_4BYTE_ADDR_EXIT 0xE9
/* Command with 4-byte address */
#define QSPI_C4B_FAST_READ 0x0C
#define QSPI_C4B_FAST_READ_2bit 0x3C
#define QSPI_C4B_FAST_READ_IO2bit 0xBC
#define QSPI_C4B_FAST_READ_4bit 0x6C
#define QSPI_C4B_FAST_READ_IO4bit 0xEC
#define QSPI_C4B_PAGE_PROGRAM 0x12
#define QSPI_C4B_PAGE_PROGRAM_4bit 0x34
#define QSPI_C4B_ERASE_SECTOR 0x21
#define QSPI_C4B_ERASE_BLOCK64KB 0xDC
#define QSPI_STATUS_REG1_BUSY_Pos 0
#define QSPI_STATUS_REG2_QUAD_Pos 1
#define QSPI_STATUS_REG3_ADS_Pos 0 // Current Address Mode, Status Only
#define QSPI_STATUS_REG3_ADP_Pos 1 // PowerUp Address Mode, Non-Volatile Writable
/* Interrupt Type */
#define QSPI_IT_ERR (1 << QSPI_CR_ERR_Pos)
#define QSPI_IT_DONE (1 << QSPI_CR_DONE_Pos)
#define QSPI_IT_FFTHR (1 << QSPI_CR_FFTHR_Pos)
#define QSPI_IT_PSMAT (1 << QSPI_CR_PSMAT_Pos)
#define QSPI_IT_TO (1 << QSPI_CR_TOIE_Pos)
void QSPI_Init(QSPI_TypeDef * QSPIx, QSPI_InitStructure * initStruct);
void QSPI_Open(QSPI_TypeDef * QSPIx);
void QSPI_Close(QSPI_TypeDef * QSPIx);
void QSPI_CmdStructClear(QSPI_CmdStructure * cmdStruct);
void QSPI_Command(QSPI_TypeDef * QSPIx, uint8_t cmdMode, QSPI_CmdStructure * cmdStruct);
void QSPI_Erase_(QSPI_TypeDef * QSPIx, uint32_t addr, uint16_t block_size, uint8_t wait);
#define QSPI_Erase(QSPIx, addr, wait) QSPI_Erase_(QSPIx, (addr), 4, (wait));
#define QSPI_Erase_Block64KB(QSPIx, addr, wait) QSPI_Erase_(QSPIx, (addr), 64, (wait));
void QSPI_Write_(QSPI_TypeDef * QSPIx, uint32_t addr, uint8_t buff[], uint32_t count, uint8_t data_width, uint8_t data_phase);
#define QSPI_Write(QSPIx, addr, buff, count) QSPI_Write_(QSPIx, (addr), (buff), (count), 1, 1)
#define QSPI_Write_4bit(QSPIx, addr, buff, count) QSPI_Write_(QSPIx, (addr), (buff), (count), 4, 1)
void QSPI_Read_(QSPI_TypeDef * QSPIx, uint32_t addr, uint8_t buff[], uint32_t count, uint8_t addr_width, uint8_t data_width, uint8_t data_phase);
#define QSPI_Read(QSPIx, addr, buff, count) QSPI_Read_(QSPIx, (addr), (buff), (count), 1, 1, 1)
#define QSPI_Read_2bit(QSPIx, addr, buff, count) QSPI_Read_(QSPIx, (addr), (buff), (count), 1, 2, 1)
#define QSPI_Read_4bit(QSPIx, addr, buff, count) QSPI_Read_(QSPIx, (addr), (buff), (count), 1, 4, 1)
#define QSPI_Read_IO2bit(QSPIx, addr, buff, count) QSPI_Read_(QSPIx, (addr), (buff), (count), 2, 2, 1)
#define QSPI_Read_IO4bit(QSPIx, addr, buff, count) QSPI_Read_(QSPIx, (addr), (buff), (count), 4, 4, 1)
bool QSPI_FlashBusy(QSPI_TypeDef * QSPIx);
uint8_t QSPI_QuadState(QSPI_TypeDef * QSPIx);
void QSPI_QuadSwitch(QSPI_TypeDef * QSPIx, uint8_t on);
uint32_t QSPI_ReadReg(QSPI_TypeDef * QSPIx, uint8_t cmd, uint8_t n_bytes);
void QSPI_WriteReg(QSPI_TypeDef * QSPIx, uint8_t cmd, uint32_t data, uint8_t n_bytes);
#define QSPI_ReadJEDEC(QSPIx) QSPI_ReadReg(QSPIx, QSPI_CMD_READ_JEDEC, 3)
#define QSPI_WriteEnable(QSPIx) QSPI_WriteReg(QSPIx, QSPI_CMD_WRITE_ENABLE, 0, 0)
#define QSPI_WriteDisable(QSPIx) QSPI_WriteReg(QSPIx, QSPI_CMD_WRITE_DISABLE, 0, 0)
#define QSPI_4ByteAddrEnable(QSPIx) QSPI_WriteReg(QSPIx, QSPI_CMD_4BYTE_ADDR_ENTER, 0, 0)
#define QSPI_4ByteAddrDisable(QSPIx) QSPI_WriteReg(QSPIx, QSPI_CMD_4BYTE_ADDR_EXIT, 0, 0)
static inline bool QSPI_Busy(QSPI_TypeDef * QSPIx)
{
return QSPIx->SR & QSPI_SR_BUSY_Msk;
}
static inline void QSPI_Abort(QSPI_TypeDef * QSPIx)
{
QSPIx->CR |= QSPI_CR_ABORT_Msk;
}
static inline uint32_t QSPI_FIFOCount(QSPI_TypeDef * QSPIx)
{
return (QSPIx->SR & QSPI_SR_FFLVL_Msk) >> QSPI_SR_FFLVL_Pos;
}
static inline uint32_t QSPI_FIFOSpace(QSPI_TypeDef * QSPIx)
{
return 16 - QSPI_FIFOCount(QSPIx);
}
static inline bool QSPI_FIFOEmpty(QSPI_TypeDef * QSPIx)
{
return QSPI_FIFOCount(QSPIx) == 0;
}
static inline void QSPI_DMAEnable(QSPI_TypeDef * QSPIx, uint32_t mode)
{
/* 必须先设置正确的读写模式,然后再置位 QSPI->CR.DMAEN且在设置 CCR.MODE 时不能写 CCR.CODE 域 */
*((uint8_t *)((uint32_t)&QSPIx->CCR + 3)) = (mode << (QSPI_CCR_MODE_Pos - 24));
QSPIx->CR |= QSPI_CR_DMAEN_Msk;
}
static inline void QSPI_DMADisable(QSPI_TypeDef * QSPIx)
{
QSPIx->CR &= ~QSPI_CR_DMAEN_Msk;
}
void QSPI_INTEn(QSPI_TypeDef * QSPIx, uint32_t it);
void QSPI_INTDis(QSPI_TypeDef * QSPIx, uint32_t it);
void QSPI_INTClr(QSPI_TypeDef * QSPIx, uint32_t it);
uint32_t QSPI_INTStat(QSPI_TypeDef * QSPIx, uint32_t it);
/******** QSPI use as normal SPI (half-duplex) ********/
void QSPI_SPI_Write_(QSPI_TypeDef * QSPIx, uint8_t buff[], uint32_t count, uint8_t data_width, uint8_t data_phase);
#define QSPI_SPI_Write(QSPIx, buff, count) QSPI_SPI_Write_(QSPIx, (buff), (count), 1, 1)
#define QSPI_SPI_Write_2bit(QSPIx, buff, count) QSPI_SPI_Write_(QSPIx, (buff), (count), 2, 1)
#define QSPI_SPI_Write_4bit(QSPIx, buff, count) QSPI_SPI_Write_(QSPIx, (buff), (count), 4, 1)
void QSPI_SPI_Read_(QSPI_TypeDef * QSPIx, uint8_t buff[], uint32_t count, uint8_t data_width, uint8_t data_phase);
#define QSPI_SPI_Read(QSPIx, buff, count) QSPI_SPI_Read_(QSPIx, (buff), (count), 1, 1)
#define QSPI_SPI_Read_2bit(QSPIx, buff, count) QSPI_SPI_Read_(QSPIx, (buff), (count), 2, 1)
#define QSPI_SPI_Read_4bit(QSPIx, buff, count) QSPI_SPI_Read_(QSPIx, (buff), (count), 4, 1)
#endif //__SWM221_QSPI_H__

@ -0,0 +1,267 @@
/******************************************************************************************************************************************
* : SWM221_spi.c
* : SWM221SPI
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.0.0 2016130
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM221.h"
#include "SWM221_spi.h"
/******************************************************************************************************************************************
* : SPI_Init()
* : SPIFIFO
* : SPI_TypeDef * SPIx SPISPI0
* SPI_InitStructure * initStruct SPI
* :
* :
******************************************************************************************************************************************/
void SPI_Init(SPI_TypeDef * SPIx, SPI_InitStructure * initStruct)
{
uint32_t fast = 0, no_sync = 0;
switch((uint32_t)SPIx)
{
case ((uint32_t)SPI0):
SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_SPI0_Pos);
break;
}
SPI_Close(SPIx); //一些关键寄存器只能在SPI关闭时设置
if(initStruct->clkDiv == SPI_CLKDIV_2)
{
fast = 1;
no_sync = 1;
}
else if(initStruct->clkDiv == SPI_CLKDIV_4)
{
no_sync = 1;
}
SPIx->CTRL &= ~(SPI_CTRL_FFS_Msk | SPI_CTRL_CPHA_Msk | SPI_CTRL_CPOL_Msk | SPI_CTRL_SIZE_Msk | SPI_CTRL_MSTR_Msk |
SPI_CTRL_CLKDIV_Msk | SPI_CTRL_SSN_H_Msk | SPI_CTRL_RFTHR_Msk | SPI_CTRL_TFTHR_Msk);
SPIx->CTRL |= (initStruct->FrameFormat << SPI_CTRL_FFS_Pos) |
(initStruct->SampleEdge << SPI_CTRL_CPHA_Pos) |
(initStruct->IdleLevel << SPI_CTRL_CPOL_Pos) |
((initStruct->WordSize-1) << SPI_CTRL_SIZE_Pos) |
(initStruct->Master << SPI_CTRL_MSTR_Pos) |
(fast << SPI_CTRL_FAST_Pos) |
(no_sync << SPI_CTRL_NSYNC_Pos) |
((initStruct->clkDiv & 7) << SPI_CTRL_CLKDIV_Pos) |
(0 << SPI_CTRL_SSN_H_Pos) |
((initStruct->RXThreshold > 0 ? initStruct->RXThreshold-1 : 0) << SPI_CTRL_RFTHR_Pos) |
(initStruct->TXThreshold << SPI_CTRL_TFTHR_Pos) |
(1 << SPI_CTRL_RFCLR_Pos) |
(1 << SPI_CTRL_TFCLR_Pos);
SPIx->CTRL &= ~(SPI_CTRL_RFCLR_Msk | SPI_CTRL_TFCLR_Msk);
SPIx->IF = 0x37F; //清除中断标志
SPIx->IE = 0x000;
SPIx->IE |= (initStruct->RXThresholdIEn << SPI_IE_RFTHR_Pos) |
(initStruct->TXThresholdIEn << SPI_IE_TFTHR_Pos) |
(initStruct->TXCompleteIEn << SPI_IE_FTC_Pos);
switch((uint32_t)SPIx)
{
case ((uint32_t)SPI0):
if(initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TXCompleteIEn)
{
NVIC_EnableIRQ(GPIOB3_GPIOA11_SPI0_IRQn);
}
else
{
NVIC_DisableIRQ(GPIOB3_GPIOA11_SPI0_IRQn);
}
break;
}
}
/******************************************************************************************************************************************
* : SPI_Open()
* : SPI
* : SPI_TypeDef * SPIx SPISPI0
* :
* :
******************************************************************************************************************************************/
void SPI_Open(SPI_TypeDef * SPIx)
{
SPIx->CTRL |= (0x01 << SPI_CTRL_EN_Pos);
}
/******************************************************************************************************************************************
* : SPI_Close()
* : SPI
* : SPI_TypeDef * SPIx SPISPI0
* :
* :
******************************************************************************************************************************************/
void SPI_Close(SPI_TypeDef * SPIx)
{
SPIx->CTRL &= ~SPI_CTRL_EN_Msk;
}
/******************************************************************************************************************************************
* : SPI_Read()
* :
* : SPI_TypeDef * SPIx SPISPI0
* : uint32_t
* :
******************************************************************************************************************************************/
uint32_t SPI_Read(SPI_TypeDef * SPIx)
{
return SPIx->DATA;
}
/******************************************************************************************************************************************
* : SPI_Write()
* :
* : SPI_TypeDef * SPIx SPISPI0
* uint32_t
* :
* :
******************************************************************************************************************************************/
void SPI_Write(SPI_TypeDef * SPIx, uint32_t data)
{
SPIx->DATA = data;
}
/******************************************************************************************************************************************
* : SPI_WriteWithWait()
* :
* : SPI_TypeDef * SPIx SPISPI0
* uint32_t
* :
* :
******************************************************************************************************************************************/
void SPI_WriteWithWait(SPI_TypeDef * SPIx, uint32_t data)
{
SPIx->STAT |= (1 << SPI_STAT_WTC_Pos);
SPIx->DATA = data;
while((SPIx->STAT & SPI_STAT_WTC_Msk) == 0);
}
/******************************************************************************************************************************************
* : SPI_ReadWrite()
* :
* : SPI_TypeDef * SPIx SPISPI0
* uint32_t data
* : uint32_t
* : SPISPI_Write()SPI_Write()SPI_STAT_RFNE
******************************************************************************************************************************************/
uint32_t SPI_ReadWrite(SPI_TypeDef * SPIx, uint32_t data)
{
SPIx->DATA = data;
while(!(SPIx->STAT & SPI_STAT_RFNE_Msk));
return SPIx->DATA;
}
/******************************************************************************************************************************************
* : SPI_IsRXEmpty()
* : FIFOSPI_Read()
* : SPI_TypeDef * SPIx SPISPI0
* : uint32_t 1 FIFO 0 FIFO
* :
******************************************************************************************************************************************/
uint32_t SPI_IsRXEmpty(SPI_TypeDef * SPIx)
{
return (SPIx->STAT & SPI_STAT_RFNE_Msk) ? 0 : 1;
}
/******************************************************************************************************************************************
* : SPI_IsTXFull()
* : FIFOSPI_Write()
* : SPI_TypeDef * SPIx SPISPI0
* : uint32_t 1 FIFO 0 FIFO
* :
******************************************************************************************************************************************/
uint32_t SPI_IsTXFull(SPI_TypeDef * SPIx)
{
return (SPIx->STAT & SPI_STAT_TFNF_Msk) ? 0 : 1;
}
/******************************************************************************************************************************************
* : SPI_IsTXEmpty()
* : FIFO
* : SPI_TypeDef * SPIx SPISPI0
* : uint32_t 1 FIFO 0 FIFO
* :
******************************************************************************************************************************************/
uint32_t SPI_IsTXEmpty(SPI_TypeDef * SPIx)
{
return (SPIx->STAT & SPI_STAT_TFE_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : SPI_INTEn()
* : 使
* : SPI_TypeDef * SPIx SPISPI0
* uint32_t it interrupt typeSPI_IT_RX_OVFSPI_IT_RX_FULLSPI_IT_RX_HFULLSPI_IT_TX_EMPTYSPI_IT_TX_HFULL
* SPI_IT_RX_THRESSPI_IT_TX_THRESSPI_IT_TX_DONESPI_IT_CS_FALLSPI_IT_CS_RISE
* :
* :
******************************************************************************************************************************************/
void SPI_INTEn(SPI_TypeDef * SPIx, uint32_t it)
{
SPIx->IE |= it;
}
/******************************************************************************************************************************************
* : SPI_INTDis()
* :
* : SPI_TypeDef * SPIx SPISPI0
* uint32_t it interrupt typeSPI_IT_RX_OVFSPI_IT_RX_FULLSPI_IT_RX_HFULLSPI_IT_TX_EMPTYSPI_IT_TX_HFULL
* SPI_IT_RX_THRESSPI_IT_TX_THRESSPI_IT_TX_DONESPI_IT_CS_FALLSPI_IT_CS_RISE
* :
* :
******************************************************************************************************************************************/
void SPI_INTDis(SPI_TypeDef * SPIx, uint32_t it)
{
SPIx->IE &= ~it;
}
/******************************************************************************************************************************************
* : SPI_INTClr()
* :
* : SPI_TypeDef * SPIx SPISPI0
* uint32_t it interrupt typeSPI_IT_RX_OVFSPI_IT_RX_FULLSPI_IT_RX_HFULLSPI_IT_TX_EMPTYSPI_IT_TX_HFULL
* SPI_IT_RX_THRESSPI_IT_TX_THRESSPI_IT_TX_DONESPI_IT_CS_FALLSPI_IT_CS_RISE
* :
* :
******************************************************************************************************************************************/
void SPI_INTClr(SPI_TypeDef * SPIx, uint32_t it)
{
SPIx->IF = it;
}
/******************************************************************************************************************************************
* : SPI_INTStat()
* :
* : SPI_TypeDef * SPIx SPISPI0
* uint32_t it interrupt typeSPI_IT_RX_OVFSPI_IT_RX_FULLSPI_IT_RX_HFULLSPI_IT_TX_EMPTYSPI_IT_TX_HFULL
* SPI_IT_RX_THRESSPI_IT_TX_THRESSPI_IT_TX_DONESPI_IT_CS_FALLSPI_IT_CS_RISE
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t SPI_INTStat(SPI_TypeDef * SPIx, uint32_t it)
{
return (SPIx->IF & it) ? 1 : 0;
}

@ -0,0 +1,112 @@
#ifndef __SWM221_SPI_H__
#define __SWM221_SPI_H__
typedef struct {
uint8_t FrameFormat; //帧格式SPI_FORMAT_SPI、SPI_FORMAT_TI_SSI
uint8_t SampleEdge; //在SPI帧格式下选择数据采样边沿SPI_FIRST_EDGE、SPI_SECOND_EDGE
uint8_t IdleLevel; //在SPI帧格式下选择空闲时无数据传输时时钟线的电平SPI_LOW_LEVEL、SPI_HIGH_LEVEL
uint8_t WordSize; //字长度, 有效值4-16
uint8_t Master; //1 主机模式 0 从机模式
uint8_t clkDiv; //SPI_CLK = SYS_CLK / clkDiv有效值SPI_CLKDIV_2、SPI_CLKDIV_4、... ... 、SPI_CLKDIV_512
uint8_t RXThreshold; //取值1--8
uint8_t RXThresholdIEn;//当RX FIFO中数据个数 >= RXThreshold时触发中断
uint8_t TXThreshold; //取值0--7
uint8_t TXThresholdIEn;//当TX FIFO中数据个数 <= TXThreshold时触发中断
uint8_t TXCompleteIEn; //发送FIFO空且发送移位寄存器空中断使能
} SPI_InitStructure;
#define SPI_FORMAT_SPI 0 //Motorola SPI 格式
#define SPI_FORMAT_TI_SSI 1 //TI SSI 格式
#define SPI_FIRST_EDGE 0 //第一个时钟沿开始采样
#define SPI_SECOND_EDGE 1 //第二个时钟沿开始采样
#define SPI_LOW_LEVEL 0 //空闲时时钟线保持低电平
#define SPI_HIGH_LEVEL 1 //空闲时时钟线保持高电平
#define SPI_CLKDIV_2 8
#define SPI_CLKDIV_4 0
#define SPI_CLKDIV_8 1
#define SPI_CLKDIV_16 2
#define SPI_CLKDIV_32 3
#define SPI_CLKDIV_64 4
#define SPI_CLKDIV_128 5
#define SPI_CLKDIV_256 6
#define SPI_CLKDIV_512 7
/* Interrupt Type */
#define SPI_IT_RX_OVF (1 << 0) //RX FIFO Overflow
#define SPI_IT_RX_FULL (1 << 1) //RX FIFO Full
#define SPI_IT_RX_HFULL (1 << 2) //RX FIFO Half Full
#define SPI_IT_TX_EMPTY (1 << 3) //TX FIFO Empty
#define SPI_IT_TX_HFULL (1 << 4) //TX FIFO Half Full
#define SPI_IT_RX_THRES (1 << 5) //RX FIFO Threshold接收FIFO中数据个数大于CTRL.RFTHR设定值
#define SPI_IT_TX_THRES (1 << 6) //TX FIFO Threshold发送FIFO中数据个数小于CTRL.TFTHR设定值
#define SPI_IT_TX_DONE (1 << 9) //TX Done发送FIFO空且发送移位寄存器空
#define SPI_IT_CS_FALL (1 << 10) //从机模式下CS下降沿中断
#define SPI_IT_CS_RISE (1 << 11) //从机模式下CS上升沿中断
void SPI_Init(SPI_TypeDef * SPIx, SPI_InitStructure * initStruct); //SPI初始化
void SPI_Open(SPI_TypeDef * SPIx); //SPI打开允许收发
void SPI_Close(SPI_TypeDef * SPIx); //SPI关闭禁止收发
uint32_t SPI_Read(SPI_TypeDef * SPIx);
void SPI_Write(SPI_TypeDef * SPIx, uint32_t data);
void SPI_WriteWithWait(SPI_TypeDef * SPIx, uint32_t data);
uint32_t SPI_ReadWrite(SPI_TypeDef * SPIx, uint32_t data);
uint32_t SPI_IsRXEmpty(SPI_TypeDef * SPIx); //接收FIFO是否空如果不空则可以继续SPI_Read()
uint32_t SPI_IsTXFull(SPI_TypeDef * SPIx); //发送FIFO是否满如果不满则可以继续SPI_Write()
uint32_t SPI_IsTXEmpty(SPI_TypeDef * SPIx); //发送FIFO是否空
void SPI_INTEn(SPI_TypeDef * SPIx, uint32_t it); //中断使能
void SPI_INTDis(SPI_TypeDef * SPIx, uint32_t it); //中断禁止
void SPI_INTClr(SPI_TypeDef * SPIx, uint32_t it); //中断标志清除
uint32_t SPI_INTStat(SPI_TypeDef * SPIx, uint32_t it); //中断状态查询
typedef struct {
uint8_t Mode; //I2S_MASTER_TX、I2S_MASTER_RX、I2S_MASTER_TX_RX、I2S_SLAVE_TX、I2S_SLAVE_RX、I2S_SLAVE_TX_RX
uint8_t FrameFormat; //I2S_I2S_PHILIPS、I2S_MSB_JUSTIFIED、I2S_PCM_SHORT、I2S_PCM_LONG0、I2S_PCM_LONG1
uint8_t DataLen; //I2S_DATALEN_8、I2S_DATALEN_16、I2S_DATALEN_24、I2S_DATALEN_32
uint32_t ClkFreq; //I2S_SCLK Frequency
uint8_t RXThreshold; //取值1--8
uint8_t RXThresholdIEn;//当RX FIFO中数据个数 >= RXThreshold时触发中断
uint8_t TXThreshold; //取值0--7
uint8_t TXThresholdIEn;//当TX FIFO中数据个数 <= TXThreshold时触发中断
uint8_t TXCompleteIEn; //发送FIFO空且发送移位寄存器空中断使能
} I2S_InitStructure;
#define I2S_MASTER_RX 5
#define I2S_MASTER_TX 6
#define I2S_SLAVE_RX 1
#define I2S_SLAVE_TX 2
#define I2S_I2S_PHILIPS 0
#define I2S_MSB_JUSTIFIED 1
#define I2S_PCM_SHORT 2
#define I2S_PCM_LONG0 3 //PCM Long Mode Sync Width 1 SCLK period
#define I2S_PCM_LONG1 4 //PCM Long Mode Sync Width 1 Data Length
#define I2S_DATALEN_8 0
#define I2S_DATALEN_16 1
#define I2S_DATALEN_24 2
#define I2S_DATALEN_32 3
void I2S_Init(SPI_TypeDef * SPIx, I2S_InitStructure * initStruct); //I2S初始化
void I2S_Open(SPI_TypeDef * SPIx); //I2S打开允许收发
void I2S_Close(SPI_TypeDef * SPIx); //I2S关闭禁止收发
void I2S_MCLKConfig(SPI_TypeDef * SPIx, uint32_t output_enable, uint32_t mclk_freq);
#endif //__SWM221_SPI_H__

@ -0,0 +1,564 @@
/******************************************************************************************************************************************
* : SWM221_timr.c
* : SWM221/
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.0.0 2016130
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM221.h"
#include "SWM221_timr.h"
/******************************************************************************************************************************************
* : TIMR_Init()
* : TIMR/
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3
* uint32_t mode TIMR0~3: TIMR_MODE_TIMERTIMR_MODE_COUNTERTIMR_MODE_OCTIMR_MODE_IC
* BTIMR0~3: TIMR_MODE_TIMERTIMR_MODE_OC
* uint32_t prediv 1-256
* uint32_t period /1-16777216
* uint32_t int_en 使
* :
* :
******************************************************************************************************************************************/
void TIMR_Init(TIMR_TypeDef * TIMRx, uint32_t mode, uint32_t prediv, uint32_t period, uint32_t int_en)
{
if((TIMRx == TIMR0) || (TIMRx == TIMR1) || (TIMRx == TIMR2))
{
SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_TIMR_Pos);
}
else if((TIMRx == BTIMR0) || (TIMRx == BTIMR1) || (TIMRx == BTIMR2) || (TIMRx == BTIMR3))
{
SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_BTIMR_Pos);
}
TIMR_Stop(TIMRx); //一些关键寄存器只能在定时器停止时设置
TIMRx->CR &= ~(TIMR_CR_MODE_Msk | TIMR_CR_CLKSRC_Msk);
TIMRx->CR |= (mode << TIMR_CR_CLKSRC_Pos);
TIMRx->PREDIV = prediv - 1;
TIMRx->LOAD = period - 1;
TIMRx->IF = (1 << TIMR_IF_TO_Pos); //清除中断标志
if(int_en) TIMRx->IE |= (1 << TIMR_IE_TO_Pos);
else TIMRx->IE &= ~(1 << TIMR_IE_TO_Pos);
switch((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
if(int_en) NVIC_EnableIRQ(TIMR0_IRQn);
break;
case ((uint32_t)TIMR1):
if(int_en) NVIC_EnableIRQ(TIMR1_IRQn);
break;
case ((uint32_t)TIMR2):
if(int_en) NVIC_EnableIRQ(GPIOB0_GPIOA8_TIMR2_IRQn);
break;
case ((uint32_t)BTIMR0):
if(int_en) NVIC_EnableIRQ(BTIMR0_IRQn);
break;
case ((uint32_t)BTIMR1):
if(int_en) NVIC_EnableIRQ(BTIMR1_IRQn);
break;
case ((uint32_t)BTIMR2):
if(int_en) NVIC_EnableIRQ(BTIMR2_IRQn);
break;
case ((uint32_t)BTIMR3):
if(int_en) NVIC_EnableIRQ(BTIMR3_IRQn);
break;
}
}
/******************************************************************************************************************************************
* : TIMR_Start()
* : /
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3
* :
* :
******************************************************************************************************************************************/
void TIMR_Start(TIMR_TypeDef * TIMRx)
{
switch((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
TIMRG->EN |= (1 << TIMRG_EN_TIMR0_Pos);
break;
case ((uint32_t)TIMR1):
TIMRG->EN |= (1 << TIMRG_EN_TIMR1_Pos);
break;
case ((uint32_t)TIMR2):
TIMRG->EN |= (1 << TIMRG_EN_TIMR2_Pos);
break;
case ((uint32_t)BTIMR0):
BTIMRG->EN |= (1 << TIMRG_EN_TIMR0_Pos);
break;
case ((uint32_t)BTIMR1):
BTIMRG->EN |= (1 << TIMRG_EN_TIMR1_Pos);
break;
case ((uint32_t)BTIMR2):
BTIMRG->EN |= (1 << TIMRG_EN_TIMR2_Pos);
break;
case ((uint32_t)BTIMR3):
BTIMRG->EN |= (1 << TIMRG_EN_TIMR3_Pos);
break;
}
}
/******************************************************************************************************************************************
* : TIMR_Stop()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3
* :
* :
******************************************************************************************************************************************/
void TIMR_Stop(TIMR_TypeDef * TIMRx)
{
switch((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
TIMRG->EN &= ~(1 << TIMRG_EN_TIMR0_Pos);
break;
case ((uint32_t)TIMR1):
TIMRG->EN &= ~(1 << TIMRG_EN_TIMR1_Pos);
break;
case ((uint32_t)TIMR2):
TIMRG->EN &= ~(1 << TIMRG_EN_TIMR2_Pos);
break;
case ((uint32_t)BTIMR0):
BTIMRG->EN &= ~(1 << TIMRG_EN_TIMR0_Pos);
break;
case ((uint32_t)BTIMR1):
BTIMRG->EN &= ~(1 << TIMRG_EN_TIMR1_Pos);
break;
case ((uint32_t)BTIMR2):
BTIMRG->EN &= ~(1 << TIMRG_EN_TIMR2_Pos);
break;
case ((uint32_t)BTIMR3):
BTIMRG->EN &= ~(1 << TIMRG_EN_TIMR3_Pos);
break;
}
}
/******************************************************************************************************************************************
* : TIMR_Halt()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2
* :
* :
******************************************************************************************************************************************/
void TIMR_Halt(TIMR_TypeDef * TIMRx)
{
TIMRx->HALT = 1;
}
/******************************************************************************************************************************************
* : TIMR_Resume()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2
* :
* :
******************************************************************************************************************************************/
void TIMR_Resume(TIMR_TypeDef * TIMRx)
{
TIMRx->HALT = 0;
}
/******************************************************************************************************************************************
* : TIMR_GetCurValue()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3
* : uint32_t
* :
******************************************************************************************************************************************/
uint32_t TIMR_GetCurValue(TIMR_TypeDef * TIMRx)
{
return TIMRx->VALUE;
}
/******************************************************************************************************************************************
* : TIMR_INTEn()
* : 使
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3
* :
* :
******************************************************************************************************************************************/
void TIMR_INTEn(TIMR_TypeDef * TIMRx)
{
TIMRx->IE |= (1 << TIMR_IE_TO_Pos);
}
/******************************************************************************************************************************************
* : TIMR_INTDis()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3
* :
* :
******************************************************************************************************************************************/
void TIMR_INTDis(TIMR_TypeDef * TIMRx)
{
TIMRx->IE &= ~(1 << TIMR_IE_TO_Pos);
}
/******************************************************************************************************************************************
* : TIMR_INTClr()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3
* :
* :
******************************************************************************************************************************************/
void TIMR_INTClr(TIMR_TypeDef * TIMRx)
{
TIMRx->IF = (1 << TIMR_IF_TO_Pos);
}
/******************************************************************************************************************************************
* : TIMR_INTStat()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3
* : uint32_t 0 TIMRx 1 TIMRx
* :
******************************************************************************************************************************************/
uint32_t TIMR_INTStat(TIMR_TypeDef * TIMRx)
{
return (TIMRx->IF & TIMR_IF_TO_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : TIMR_OC_Init()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3
* uint32_t match match
* uint32_t match_int_en match
* uint32_t init_lvl Timer
* :
* :
******************************************************************************************************************************************/
void TIMR_OC_Init(TIMR_TypeDef * TIMRx, uint32_t match, uint32_t match_int_en, uint32_t init_lvl)
{
TIMRx->OCMAT = match;
if(init_lvl) TIMRx->OCCR |= (1 << TIMR_OCCR_INITLVL_Pos);
else TIMRx->OCCR &= ~(1 << TIMR_OCCR_INITLVL_Pos);
TIMRx->IF = (1 << TIMR_IF_OC0_Pos); //清除中断标志
if(match_int_en) TIMRx->IE |= (1 << TIMR_IE_OC0_Pos);
else TIMRx->IE &= ~(1 << TIMR_IE_OC0_Pos);
switch((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
if(match_int_en) NVIC_EnableIRQ(TIMR0_IRQn);
break;
case ((uint32_t)TIMR1):
if(match_int_en) NVIC_EnableIRQ(TIMR1_IRQn);
break;
case ((uint32_t)TIMR2):
if(match_int_en) NVIC_EnableIRQ(GPIOB0_GPIOA8_TIMR2_IRQn);
break;
case ((uint32_t)BTIMR0):
if(match_int_en) NVIC_EnableIRQ(BTIMR0_IRQn);
break;
case ((uint32_t)BTIMR1):
if(match_int_en) NVIC_EnableIRQ(BTIMR1_IRQn);
break;
case ((uint32_t)BTIMR2):
if(match_int_en) NVIC_EnableIRQ(BTIMR2_IRQn);
break;
case ((uint32_t)BTIMR3):
if(match_int_en) NVIC_EnableIRQ(BTIMR3_IRQn);
break;
}
}
/******************************************************************************************************************************************
* : TIMR_OC_OutputEn()
* : 使
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3
* :
* :
******************************************************************************************************************************************/
void TIMR_OC_OutputEn(TIMR_TypeDef * TIMRx)
{
TIMRx->OCCR &= ~(TIMR_OCCR_FORCEEN_Pos);
}
/******************************************************************************************************************************************
* : TIMR_OC_OutputDis()
* : level
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3
* uint32_t level
* :
* :
******************************************************************************************************************************************/
void TIMR_OC_OutputDis(TIMR_TypeDef * TIMRx, uint32_t level)
{
if(level) TIMRx->OCCR |= (1 << TIMR_OCCR_FORCELVL_Pos);
else TIMRx->OCCR &= ~(1 << TIMR_OCCR_FORCELVL_Pos);
TIMRx->OCCR |= (TIMR_OCCR_FORCEEN_Pos);
}
/******************************************************************************************************************************************
* : TIMR_OC_SetMatch()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3
* uint32_t match
* :
* :
******************************************************************************************************************************************/
void TIMR_OC_SetMatch(TIMR_TypeDef * TIMRx, uint32_t match)
{
TIMRx->OCMAT = match;
}
/******************************************************************************************************************************************
* : TIMR_OC_GetMatch()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3
* : uint32_t
* :
******************************************************************************************************************************************/
uint32_t TIMR_OC_GetMatch(TIMR_TypeDef * TIMRx)
{
return TIMRx->OCMAT;
}
/******************************************************************************************************************************************
* : TIMR_OC_INTEn()
* : 使
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3
* :
* :
******************************************************************************************************************************************/
void TIMR_OC_INTEn(TIMR_TypeDef * TIMRx)
{
TIMRx->IE |= (1 << TIMR_IE_OC0_Pos);
}
/******************************************************************************************************************************************
* : TIMR_OC_INTDis()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3
* :
* :
******************************************************************************************************************************************/
void TIMR_OC_INTDis(TIMR_TypeDef * TIMRx)
{
TIMRx->IE &= ~(1 << TIMR_IE_OC0_Pos);
}
/******************************************************************************************************************************************
* : TIMR_OC_INTClr()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3
* :
* :
******************************************************************************************************************************************/
void TIMR_OC_INTClr(TIMR_TypeDef * TIMRx)
{
TIMRx->IF = (1 << TIMR_IF_OC0_Pos);
}
/******************************************************************************************************************************************
* : TIMR_OC_INTStat()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3
* : uint32_t 0 match 1 match
* :
******************************************************************************************************************************************/
uint32_t TIMR_OC_INTStat(TIMR_TypeDef * TIMRx)
{
return (TIMRx->IF & TIMR_IF_OC0_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : TIMR_IC_Init()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2
* uint32_t captureH_int_en 使
* uint32_t captureL_int_en 使
* :
* :
******************************************************************************************************************************************/
void TIMR_IC_Init(TIMR_TypeDef * TIMRx, uint32_t captureH_int_en, uint32_t captureL_int_en)
{
TIMRx->IF = (TIMR_IF_ICR_Msk | TIMR_IF_ICF_Msk);
if(captureH_int_en) TIMRx->IE |= (1 << TIMR_IE_ICF_Pos);
else TIMRx->IE &= ~(1 << TIMR_IE_ICF_Pos);
if(captureL_int_en) TIMRx->IE |= (1 << TIMR_IE_ICR_Pos);
else TIMRx->IE &= ~(1 << TIMR_IE_ICR_Pos);
switch((uint32_t)TIMRx)
{
case ((uint32_t)TIMR0):
if(captureH_int_en | captureL_int_en) NVIC_EnableIRQ(TIMR0_IRQn);
break;
case ((uint32_t)TIMR1):
if(captureH_int_en | captureL_int_en) NVIC_EnableIRQ(TIMR1_IRQn);
break;
case ((uint32_t)TIMR2):
if(captureH_int_en | captureL_int_en) NVIC_EnableIRQ(GPIOB0_GPIOA8_TIMR2_IRQn);
break;
}
}
/******************************************************************************************************************************************
* : TIMR_IC_GetCaptureH()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2
* : uint32_t
* :
******************************************************************************************************************************************/
uint32_t TIMR_IC_GetCaptureH(TIMR_TypeDef * TIMRx)
{
return TIMRx->ICHIGH;
}
/******************************************************************************************************************************************
* : TIMR_IC_GetCaptureL()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2
* : uint32_t
* :
******************************************************************************************************************************************/
uint32_t TIMR_IC_GetCaptureL(TIMR_TypeDef * TIMRx)
{
return TIMRx->ICLOW;
}
/******************************************************************************************************************************************
* : TIMR_IC_CaptureH_INTEn()
* : 使
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2
* :
* :
******************************************************************************************************************************************/
void TIMR_IC_CaptureH_INTEn(TIMR_TypeDef * TIMRx)
{
TIMRx->IE |= (1 << TIMR_IE_ICF_Pos);
}
/******************************************************************************************************************************************
* : TIMR_IC_CaptureH_INTDis()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2
* :
* :
******************************************************************************************************************************************/
void TIMR_IC_CaptureH_INTDis(TIMR_TypeDef * TIMRx)
{
TIMRx->IE &= ~(1 << TIMR_IE_ICF_Pos);
}
/******************************************************************************************************************************************
* : TIMR_IC_CaptureH_INTClr()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2
* :
* :
******************************************************************************************************************************************/
void TIMR_IC_CaptureH_INTClr(TIMR_TypeDef * TIMRx)
{
TIMRx->IF = (1 << TIMR_IF_ICF_Pos);
}
/******************************************************************************************************************************************
* : TIMR_IC_CaptureH_INTStat()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2
* : uint32_t 0 1
* :
******************************************************************************************************************************************/
uint32_t TIMR_IC_CaptureH_INTStat(TIMR_TypeDef * TIMRx)
{
return (TIMRx->IF & TIMR_IF_ICF_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : TIMR_IC_CaptureL_INTEn()
* : 使
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2
* :
* :
******************************************************************************************************************************************/
void TIMR_IC_CaptureL_INTEn(TIMR_TypeDef * TIMRx)
{
TIMRx->IE |= (1 << TIMR_IE_ICR_Pos);
}
/******************************************************************************************************************************************
* : TIMR_IC_CaptureL_INTDis()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2
* :
* :
******************************************************************************************************************************************/
void TIMR_IC_CaptureL_INTDis(TIMR_TypeDef * TIMRx)
{
TIMRx->IE &= ~(1 << TIMR_IE_ICR_Pos);
}
/******************************************************************************************************************************************
* : TIMR_IC_CaptureL_INTClr()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2
* :
* :
******************************************************************************************************************************************/
void TIMR_IC_CaptureL_INTClr(TIMR_TypeDef * TIMRx)
{
TIMRx->IF = (1 << TIMR_IF_ICR_Pos);
}
/******************************************************************************************************************************************
* : TIMR_IC_CaptureL_INTStat()
* :
* : TIMR_TypeDef * TIMRx TIMR0TIMR1TIMR2
* : uint32_t 0 1
* :
******************************************************************************************************************************************/
uint32_t TIMR_IC_CaptureL_INTStat(TIMR_TypeDef * TIMRx)
{
return (TIMRx->IF & TIMR_IF_ICR_Msk) ? 1 : 0;
}

@ -0,0 +1,63 @@
#ifndef __SWM221_TIMR_H__
#define __SWM221_TIMR_H__
#define TIMR_MODE_TIMER ((0 << 2) | 0)
#define TIMR_MODE_IC ((1 << 2) | 0) //输入捕获
#define TIMR_MODE_OC ((2 << 2) | 0) //输出比较
#define TIMR_MODE_COUNTER ((0 << 2) | 2) //计数上升沿
void TIMR_Init(TIMR_TypeDef * TIMRx, uint32_t mode, uint32_t prediv, uint32_t period, uint32_t int_en); //定时器/计数器初始化
void TIMR_Start(TIMR_TypeDef * TIMRx); //启动定时器,从初始值开始计时/计数
void TIMR_Stop(TIMR_TypeDef * TIMRx); //停止定时器
void TIMR_Halt(TIMR_TypeDef * TIMRx); //暂停定时器,计数值保持不变
void TIMR_Resume(TIMR_TypeDef * TIMRx); //恢复定时器,从暂停处继续计数
uint32_t TIMR_SetPrediv(TIMR_TypeDef * TIMRx, uint32_t prediv); //设置预分频
void TIMR_SetPeriod(TIMR_TypeDef * TIMRx, uint32_t period); //设置定时/计数周期
uint32_t TIMR_GetPeriod(TIMR_TypeDef * TIMRx); //获取定时/计数周期
uint32_t TIMR_GetCurValue(TIMR_TypeDef * TIMRx); //获取当前计数值
void TIMR_INTEn(TIMR_TypeDef * TIMRx); //使能中断
void TIMR_INTDis(TIMR_TypeDef * TIMRx); //禁能中断
void TIMR_INTClr(TIMR_TypeDef * TIMRx); //清除中断标志
uint32_t TIMR_INTStat(TIMR_TypeDef * TIMRx); //获取中断状态
void TIMR_OC_Init(TIMR_TypeDef * TIMRx, uint32_t match, uint32_t match_int_en, uint32_t init_lvl);
void TIMR_OC_OutputEn(TIMR_TypeDef * TIMRx);
void TIMR_OC_OutputDis(TIMR_TypeDef * TIMRx, uint32_t level);
void TIMR_OC_SetMatch(TIMR_TypeDef * TIMRx, uint32_t match);
uint32_t TIMR_OC_GetMatch(TIMR_TypeDef * TIMRx);
void TIMR_OC_INTEn(TIMR_TypeDef * TIMRx);
void TIMR_OC_INTDis(TIMR_TypeDef * TIMRx);
void TIMR_OC_INTClr(TIMR_TypeDef * TIMRx);
uint32_t TIMR_OC_INTStat(TIMR_TypeDef * TIMRx);
void TIMR_IC_Init(TIMR_TypeDef * TIMRx, uint32_t captureH_int_en, uint32_t captureL_int_en);
void TIMR_IC_Start(TIMR_TypeDef * TIMRx);
void TIMR_IC_Start_Multi(uint32_t timr0, uint32_t timr1, uint32_t timr2, uint32_t timr3);
void TIMR_IC_Stop(TIMR_TypeDef * TIMRx);
uint32_t TIMR_IC_GetCaptureH(TIMR_TypeDef * TIMRx);
uint32_t TIMR_IC_GetCaptureL(TIMR_TypeDef * TIMRx);
void TIMR_IC_CaptureH_INTEn(TIMR_TypeDef * TIMRx);
void TIMR_IC_CaptureH_INTDis(TIMR_TypeDef * TIMRx);
void TIMR_IC_CaptureH_INTClr(TIMR_TypeDef * TIMRx);
uint32_t TIMR_IC_CaptureH_INTStat(TIMR_TypeDef * TIMRx);
void TIMR_IC_CaptureL_INTEn(TIMR_TypeDef * TIMRx);
void TIMR_IC_CaptureL_INTDis(TIMR_TypeDef * TIMRx);
void TIMR_IC_CaptureL_INTClr(TIMR_TypeDef * TIMRx);
uint32_t TIMR_IC_CaptureL_INTStat(TIMR_TypeDef * TIMRx);
void TIMR_IC_CaptureOV_INTEn(TIMR_TypeDef * TIMRx);
void TIMR_IC_CaptureOV_INTDis(TIMR_TypeDef * TIMRx);
void TIMR_IC_CaptureOV_INTClr(TIMR_TypeDef * TIMRx);
uint32_t TIMR_IC_CaptureOV_INTStat(TIMR_TypeDef * TIMRx);
#endif //__SWM221_TIMR_H__

@ -0,0 +1,498 @@
/******************************************************************************************************************************************
* : SWM221_uart.c
* : SWM221UART
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.0.0 2016130
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM221.h"
#include "SWM221_uart.h"
/******************************************************************************************************************************************
* : UART_Init()
* : UART
* : UART_TypeDef * UARTx UARTUART0UART1
* UART_InitStructure * initStruct UART
* :
* :
******************************************************************************************************************************************/
void UART_Init(UART_TypeDef * UARTx, UART_InitStructure * initStruct)
{
switch((uint32_t)UARTx)
{
case ((uint32_t)UART0):
SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_UART0_Pos);
break;
case ((uint32_t)UART1):
SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_UART1_Pos);
break;
}
UART_Close(UARTx); //一些关键寄存器只能在串口关闭时设置
UARTx->BAUD &= ~(UART_BAUD_BAUD_Msk | UART_BAUD_FRAC_Msk);
UARTx->BAUD |= (((SystemCoreClock/initStruct->Baudrate - 1) / 16) << UART_BAUD_BAUD_Pos) |
(((SystemCoreClock/initStruct->Baudrate - 1) % 16) << UART_BAUD_FRAC_Pos);
UARTx->CTRL &= ~(UART_CTRL_DATA9b_Msk | UART_CTRL_PARITY_Msk | UART_CTRL_STOP2b_Msk);
UARTx->CTRL |= (initStruct->DataBits << UART_CTRL_DATA9b_Pos) |
(initStruct->Parity << UART_CTRL_PARITY_Pos) |
(initStruct->StopBits << UART_CTRL_STOP2b_Pos);
UARTx->FIFO &= ~(UART_FIFO_RXTHR_Msk | UART_FIFO_TXTHR_Msk);
UARTx->FIFO |= (initStruct->RXThreshold << UART_FIFO_RXTHR_Pos) |
(initStruct->TXThreshold << UART_FIFO_TXTHR_Pos);
UARTx->TOCR &= ~UART_TOCR_TIME_Msk;
UARTx->TOCR |= (1 << UART_TOCR_MODE_Pos) |
(initStruct->TimeoutTime << UART_TOCR_TIME_Pos);
UARTx->CTRL &= ~(UART_CTRL_RXIE_Msk | UART_CTRL_TXIE_Msk | UART_CTRL_TOIE_Msk);
UARTx->CTRL |= (initStruct->RXThresholdIEn << UART_CTRL_RXIE_Pos) |
(initStruct->TXThresholdIEn << UART_CTRL_TXIE_Pos) |
(initStruct->TimeoutIEn << UART_CTRL_TOIE_Pos);
switch((uint32_t)UARTx)
{
case ((uint32_t)UART0):
if(initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TimeoutIEn)
{
NVIC_EnableIRQ(UART0_IRQn);
}
else
{
NVIC_DisableIRQ(UART0_IRQn);
}
break;
case ((uint32_t)UART1):
if(initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TimeoutIEn)
{
NVIC_EnableIRQ(UART1_IRQn);
}
else
{
NVIC_DisableIRQ(UART1_IRQn);
}
break;
}
}
/******************************************************************************************************************************************
* : UART_Open()
* : UART
* : UART_TypeDef * UARTx UARTUART0UART1
* :
* :
******************************************************************************************************************************************/
void UART_Open(UART_TypeDef * UARTx)
{
UARTx->CTRL |= (0x01 << UART_CTRL_EN_Pos);
}
/******************************************************************************************************************************************
* : UART_Close()
* : UART
* : UART_TypeDef * UARTx UARTUART0UART1
* :
* :
******************************************************************************************************************************************/
void UART_Close(UART_TypeDef * UARTx)
{
UARTx->CTRL &= ~(0x01 << UART_CTRL_EN_Pos);
}
/******************************************************************************************************************************************
* : UART_WriteByte()
* :
* : UART_TypeDef * UARTx UARTUART0UART1UART4
* uint8_t data
* :
* :
******************************************************************************************************************************************/
void UART_WriteByte(UART_TypeDef * UARTx, uint8_t data)
{
UARTx->DATA = data;
}
/******************************************************************************************************************************************
* : UART_ReadByte()
* : Valid
* : UART_TypeDef * UARTx UARTUART0UART1UART4
* uint32_t * data
* : uint32_t 0 UART_ERR_PARITY
* :
******************************************************************************************************************************************/
uint32_t UART_ReadByte(UART_TypeDef * UARTx, uint32_t * data)
{
uint32_t reg = UARTx->DATA;
*data = (reg & UART_DATA_DATA_Msk);
if(reg & UART_DATA_PAERR_Msk) return UART_ERR_PARITY;
return 0;
}
/******************************************************************************************************************************************
* : UART_IsTXBusy()
* : UART
* : UART_TypeDef * UARTx UARTUART0UART1
* : uint32_t 1 UART 0
* :
******************************************************************************************************************************************/
uint32_t UART_IsTXBusy(UART_TypeDef * UARTx)
{
return (UARTx->CTRL & UART_CTRL_TXIDLE_Msk) ? 0 : 1;
}
/******************************************************************************************************************************************
* : UART_IsRXFIFOEmpty()
* : FIFO
* : UART_TypeDef * UARTx UARTUART0UART1
* : uint32_t 1 FIFO 0 FIFO
* :
******************************************************************************************************************************************/
uint32_t UART_IsRXFIFOEmpty(UART_TypeDef * UARTx)
{
return (UARTx->CTRL & UART_CTRL_RXNE_Msk) ? 0 : 1;
}
/******************************************************************************************************************************************
* : UART_IsTXFIFOFull()
* : FIFO
* : UART_TypeDef * UARTx UARTUART0UART1
* : uint32_t 1 FIFO 0 FIFO
* :
******************************************************************************************************************************************/
uint32_t UART_IsTXFIFOFull(UART_TypeDef * UARTx)
{
return (UARTx->CTRL & UART_CTRL_TXFF_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : UART_SetBaudrate()
* :
* : UART_TypeDef * UARTx UARTUART0UART1
* uint32_t baudrate
* :
* : 使UART_Close()
******************************************************************************************************************************************/
void UART_SetBaudrate(UART_TypeDef * UARTx, uint32_t baudrate)
{
UARTx->BAUD &= ~(UART_BAUD_BAUD_Msk | UART_BAUD_FRAC_Msk);
UARTx->BAUD |= (((SystemCoreClock/baudrate - 1) / 16) << UART_BAUD_BAUD_Pos) |
(((SystemCoreClock/baudrate - 1) % 16) << UART_BAUD_FRAC_Pos);
}
/******************************************************************************************************************************************
* : UART_GetBaudrate()
* :
* : UART_TypeDef * UARTx UARTUART0UART1
* : uint32_t
* :
******************************************************************************************************************************************/
uint32_t UART_GetBaudrate(UART_TypeDef * UARTx)
{
return SystemCoreClock/(((UARTx->BAUD & UART_BAUD_BAUD_Msk) >> UART_BAUD_BAUD_Pos) * 16 +
((UARTx->BAUD & UART_BAUD_FRAC_Msk) >> UART_BAUD_FRAC_Pos) + 1);
}
/******************************************************************************************************************************************
* : UART_CTSConfig()
* : UART CTS
* : UART_TypeDef * UARTx UARTUART0UART1
* uint32_t enable 1 使CTS 0 CTS
* uint32_t polarity 0 CTS 1 CTS
* :
* :
******************************************************************************************************************************************/
void UART_CTSConfig(UART_TypeDef * UARTx, uint32_t enable, uint32_t polarity)
{
UARTx->CTSCR &= ~(UART_CTSCR_EN_Msk | UART_CTSCR_POL_Msk);
UARTx->CTSCR |= (enable << UART_CTSCR_EN_Pos) |
(polarity << UART_CTSCR_POL_Pos);
}
/******************************************************************************************************************************************
* : UART_CTSLineState()
* : UART CTS线
* : UART_TypeDef * UARTx UARTUART0UART1
* : uint32_t 0 CTS线 1 CTS线
* :
******************************************************************************************************************************************/
uint32_t UART_CTSLineState(UART_TypeDef * UARTx)
{
return (UARTx->CTSCR & UART_CTSCR_STAT_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : UART_RTSConfig()
* : UART RTS
* : UART_TypeDef * UARTx UARTUART0UART1
* uint32_t enable 1 使RTS 0 RTS
* uint32_t polarity 0 RTS 1 RTS
* uint32_t threshold RTSUART_RTS_1BYTEUART_RTS_2BYTEUART_RTS_4BYTEUART_RTS_6BYTE
* :
* :
******************************************************************************************************************************************/
void UART_RTSConfig(UART_TypeDef * UARTx, uint32_t enable, uint32_t polarity, uint32_t threshold)
{
UARTx->RTSCR &= ~(UART_RTSCR_EN_Msk | UART_RTSCR_POL_Msk | UART_RTSCR_THR_Msk);
UARTx->RTSCR |= (enable << UART_RTSCR_EN_Pos) |
(polarity << UART_RTSCR_POL_Pos) |
(threshold << UART_RTSCR_THR_Pos);
}
/******************************************************************************************************************************************
* : UART_RTSLineState()
* : UART RTS线
* : UART_TypeDef * UARTx UARTUART0UART1
* : uint32_t 0 RTS线 1 RTS线
* :
******************************************************************************************************************************************/
uint32_t UART_RTSLineState(UART_TypeDef * UARTx)
{
return (UARTx->RTSCR & UART_RTSCR_STAT_Msk) ? 1 : 0;
}
/******************************************************************************************************************************************
* : UART_LINConfig()
* : UART LIN
* : UART_TypeDef * UARTx UARTUART0UART1
* uint32_t detectedLen Break1--16
* uint32_t detectedIEn Break使
* uint32_t generatedLen Break1--15
* uint32_t generatedIEn Break使
* :
* :
******************************************************************************************************************************************/
void UART_LINConfig(UART_TypeDef * UARTx, uint32_t detectedLen, uint32_t detectedIEn, uint32_t generatedLen, uint32_t generatedIEn)
{
UARTx->CFG &= ~(UART_CFG_BRKTXLEN_Msk | UART_CFG_BRKRXLEN_Msk);
UARTx->CFG |= ((detectedLen-1) << UART_CFG_BRKRXLEN_Pos) |
(generatedLen << UART_CFG_BRKTXLEN_Pos);
UARTx->LINCR &= ~(UART_LINCR_BRKDETIE_Msk | UART_LINCR_GENBRKIE_Msk);
UARTx->LINCR |= (detectedIEn << UART_LINCR_BRKDETIE_Pos) |
(generatedIEn << UART_LINCR_GENBRKIE_Pos);
}
/******************************************************************************************************************************************
* : UART_LINGenerate()
* : UART LIN/Break
* : UART_TypeDef * UARTx UARTUART0UART1
* :
* :
******************************************************************************************************************************************/
void UART_LINGenerate(UART_TypeDef * UARTx)
{
UARTx->LINCR |= (1 << UART_LINCR_GENBRK_Pos);
}
/******************************************************************************************************************************************
* : UART_LININTEn()
* : LIN 使
* : UART_TypeDef * UARTx UARTUART0UART1
* uint32_t it interrupt type UART_IT_LIN_DETUART_IT_LIN_GEN
* :
* :
******************************************************************************************************************************************/
void UART_LININTEn(UART_TypeDef * UARTx, uint32_t it)
{
UARTx->LINCR |= it;
}
/******************************************************************************************************************************************
* : UART_LININTDis()
* : LIN
* : UART_TypeDef * UARTx UARTUART0UART1
* uint32_t it interrupt type UART_IT_LIN_DETUART_IT_LIN_GEN
* :
* :
******************************************************************************************************************************************/
void UART_LININTDis(UART_TypeDef * UARTx, uint32_t it)
{
UARTx->LINCR &= ~it;
}
/******************************************************************************************************************************************
* : UART_LININTClr()
* : LIN
* : UART_TypeDef * UARTx UARTUART0UART1
* uint32_t it interrupt type UART_IT_LIN_DETUART_IT_LIN_GEN
* :
* :
******************************************************************************************************************************************/
void UART_LININTClr(UART_TypeDef * UARTx, uint32_t it)
{
UARTx->LINCR |= (it << 1);
}
/******************************************************************************************************************************************
* : UART_LININTStat()
* : LIN
* : UART_TypeDef * UARTx UARTUART0UART1
* uint32_t it interrupt type UART_IT_LIN_DETUART_IT_LIN_GEN
* : uint32_t 0 0
* :
******************************************************************************************************************************************/
uint32_t UART_LININTStat(UART_TypeDef * UARTx, uint32_t it)
{
return (UARTx->LINCR & (it << 1));
}
uint8_t UART_LIN_IDParity(uint8_t lin_id)
{
struct {
uint8_t b0 : 1;
uint8_t b1 : 1;
uint8_t b2 : 1;
uint8_t b3 : 1;
uint8_t b4 : 1;
uint8_t b5 : 1;
uint8_t b6 : 1;
uint8_t b7 : 1;
} * bits = (void *)&lin_id;
uint8_t id_P0 = (bits->b0 ^ bits->b1 ^ bits->b2 ^ bits->b4);
uint8_t id_P1 = ~(bits->b1 ^ bits->b3 ^ bits->b4 ^ bits->b5);
return (lin_id & 0x3F) | (id_P0 << 6) | (id_P1 << 7);
}
uint8_t UART_LIN_Checksum(uint8_t lin_id, uint8_t data[], uint32_t count, bool enhanced_checksum)
{
uint16_t checksum;
if(enhanced_checksum && ((lin_id & 0x3F) != 60) && ((lin_id & 0x3F) != 61))
checksum = lin_id;
else
checksum = 0x00;
for(int i = 0; i < count; i++)
{
checksum += data[i];
checksum = (checksum & 0xFF) + (checksum >> 8);
}
return ~checksum;
}
/******************************************************************************************************************************************
* : UART_ABRStart()
* : UART
* : UART_TypeDef * UARTx UARTUART0UART1
* uint32_t detectChar
* 80xFF0xFE0xF80x800xFF0xFE0xF80x80
* 90x1FF0x1FE0x1F80x1800x1FF0x1FE0x1F80x180
* :
* :
******************************************************************************************************************************************/
void UART_ABRStart(UART_TypeDef * UARTx, uint32_t detectChar)
{
uint32_t bits;
if((detectChar == 0xFF) || (detectChar == 0x1FF)) bits = 0;
else if((detectChar == 0xFE) || (detectChar == 0x1FE)) bits = 1;
else if((detectChar == 0xF8) || (detectChar == 0x1F8)) bits = 2;
else if((detectChar == 0x80) || (detectChar == 0x180)) bits = 3;
else while(1);
UARTx->BAUD &= ~(UART_BAUD_ABREN_Msk | UART_BAUD_ABRBIT_Msk);
UARTx->BAUD |= (1 << UART_BAUD_ABREN_Pos) |
(bits << UART_BAUD_ABRBIT_Pos);
}
/******************************************************************************************************************************************
* : UART_ABRIsDone()
* : UART
* : UART_TypeDef * UARTx UARTUART0UART1
* : uint32_t 0 UART_ABR_RES_OK UART_ABR_RES_ERR
* :
******************************************************************************************************************************************/
uint32_t UART_ABRIsDone(UART_TypeDef * UARTx)
{
if(UARTx->BAUD & UART_BAUD_ABREN_Msk)
{
return 0;
}
else if(UARTx->BAUD & UART_BAUD_ABRERR_Msk)
{
return UART_ABR_RES_ERR;
}
else
{
return UART_ABR_RES_OK;
}
}
/******************************************************************************************************************************************
* : UART_INTEn()
* : 使
* : UART_TypeDef * UARTx UARTUART0UART1UART2UART3
* uint32_t it interrupt type UART_IT_RX_THRUART_IT_RX_TOUTUART_IT_TX_THRUART_IT_TX_DONE
* :
* :
******************************************************************************************************************************************/
void UART_INTEn(UART_TypeDef * UARTx, uint32_t it)
{
UARTx->CTRL |= it;
}
/******************************************************************************************************************************************
* : UART_INTDis()
* :
* : UART_TypeDef * UARTx UARTUART0UART1UART2UART3
* uint32_t it interrupt type UART_IT_RX_THRUART_IT_RX_TOUTUART_IT_TX_THRUART_IT_TX_DONE
* :
* :
******************************************************************************************************************************************/
void UART_INTDis(UART_TypeDef * UARTx, uint32_t it)
{
UARTx->CTRL &= ~it;
}
/******************************************************************************************************************************************
* : UART_INTClr()
* :
* : UART_TypeDef * UARTx UARTUART0UART1UART2UART3
* uint32_t it interrupt type UART_IT_RX_TOUT
* :
* :
******************************************************************************************************************************************/
void UART_INTClr(UART_TypeDef * UARTx, uint32_t it)
{
if(it & UART_IT_RX_TOUT)
UARTx->TOCR |= UART_TOCR_IFCLR_Msk;
}
/******************************************************************************************************************************************
* : UART_INTStat()
* :
* : UART_TypeDef * UARTx UARTUART0UART1UART2UART3
* uint32_t it interrupt type UART_IT_RX_THRUART_IT_RX_TOUTUART_IT_TX_THRUART_IT_TX_DONE
* : uint32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t UART_INTStat(UART_TypeDef * UARTx, uint32_t it)
{
return (((it & UART_IT_RX_THR) && (UARTx->BAUD & UART_BAUD_RXIF_Msk)) ||
((it & UART_IT_RX_TOUT) && (UARTx->BAUD & UART_BAUD_TOIF_Msk)) ||
((it & UART_IT_TX_THR) && (UARTx->BAUD & UART_BAUD_TXIF_Msk)) ||
((it & UART_IT_TX_DONE) && (UARTx->BAUD & UART_BAUD_TXDOIF_Msk)));
}

@ -0,0 +1,100 @@
#ifndef __SWM221_UART_H__
#define __SWM221_UART_H__
typedef struct {
uint32_t Baudrate;
uint8_t DataBits; //数据位位数可取值UART_DATA_8BIT、UART_DATA_9BIT
uint8_t Parity; //奇偶校验位可取值UART_PARITY_NONE、UART_PARITY_ODD、UART_PARITY_EVEN、UART_PARITY_ONE、UART_PARITY_ZERO
uint8_t StopBits; //停止位位数可取值UART_STOP_1BIT、UART_STOP_2BIT
uint8_t RXThreshold; //取值0--7
uint8_t RXThresholdIEn; //当RX FIFO中数据个数 > RXThreshold时触发中断
uint8_t TXThreshold; //取值0--7
uint8_t TXThresholdIEn; //当TX FIFO中数据个数 <= TXThreshold时触发中断
uint8_t TimeoutTime; //超时时长 = TimeoutTime/(Baudrate/10) 秒
uint8_t TimeoutIEn; //超时中断RX FIFO非空且超过 TimeoutTime/(Baudrate/10) 秒没有在RX线上接收到数据时触发中断
} UART_InitStructure;
#define UART_DATA_8BIT 0
#define UART_DATA_9BIT 1
#define UART_PARITY_NONE 0
#define UART_PARITY_ODD 1
#define UART_PARITY_EVEN 3
#define UART_PARITY_ONE 5
#define UART_PARITY_ZERO 7
#define UART_STOP_1BIT 0
#define UART_STOP_2BIT 1
#define UART_RTS_1BYTE 0
#define UART_RTS_2BYTE 1
#define UART_RTS_4BYTE 2
#define UART_RTS_6BYTE 3
#define UART_ABR_RES_OK 1
#define UART_ABR_RES_ERR 2
#define UART_ERR_FRAME 1
#define UART_ERR_PARITY 2
#define UART_ERR_NOISE 3
/* Interrupt Type */
#define UART_IT_RX_THR (1 << UART_CTRL_RXIE_Pos) //RX FIFO Threshold, RX FIFO中数据个数 > RXThreshold
#define UART_IT_RX_TOUT (1 << UART_CTRL_TOIE_Pos) //RX Timeout, 超过 TimeoutTime/(Baudrate/10) 秒没有在RX线上接收到数据
#define UART_IT_TX_THR (1 << UART_CTRL_TXIE_Pos) //TX FIFO Threshold, TX FIFO中数据个数 <= TXThreshold
#define UART_IT_TX_DONE (1 << UART_CTRL_TXDOIE_Pos) //TX Done, 发送FIFO空且发送发送移位寄存器已将最后一位发送出去
#define UART_IT_LIN_DET (1 << UART_LINCR_BRKDETIE_Pos)
#define UART_IT_LIN_GEN (1 << UART_LINCR_GENBRKIE_Pos)
void UART_Init(UART_TypeDef * UARTx, UART_InitStructure * initStruct); //UART串口初始化
void UART_Open(UART_TypeDef * UARTx);
void UART_Close(UART_TypeDef * UARTx);
void UART_WriteByte(UART_TypeDef * UARTx, uint8_t data); //发送一个字节数据
uint32_t UART_ReadByte(UART_TypeDef * UARTx, uint32_t * data); //读取一个字节数据并指出数据是否Valid
uint32_t UART_IsTXBusy(UART_TypeDef * UARTx);
uint32_t UART_IsRXFIFOEmpty(UART_TypeDef * UARTx); //接收FIFO是否空如果不空则可以继续UART_ReadByte()
uint32_t UART_IsTXFIFOFull(UART_TypeDef * UARTx); //发送FIFO是否满如果不满则可以继续UART_WriteByte()
void UART_SetBaudrate(UART_TypeDef * UARTx, uint32_t baudrate); //设置波特率
uint32_t UART_GetBaudrate(UART_TypeDef * UARTx); //获取当前使用的波特率
void UART_CTSConfig(UART_TypeDef * UARTx, uint32_t enable, uint32_t polarity);
uint32_t UART_CTSLineState(UART_TypeDef * UARTx);
void UART_RTSConfig(UART_TypeDef * UARTx, uint32_t enable, uint32_t polarity, uint32_t threshold);
uint32_t UART_RTSLineState(UART_TypeDef * UARTx);
void UART_LINConfig(UART_TypeDef * UARTx, uint32_t detectedLen, uint32_t detectedIEn, uint32_t generatedLen, uint32_t generatedIEn);
void UART_LINGenerate(UART_TypeDef * UARTx);
void UART_LININTEn(UART_TypeDef * UARTx, uint32_t it);
void UART_LININTDis(UART_TypeDef * UARTx, uint32_t it);
void UART_LININTClr(UART_TypeDef * UARTx, uint32_t it);
uint32_t UART_LININTStat(UART_TypeDef * UARTx, uint32_t it);
uint8_t UART_LIN_IDParity(uint8_t lin_id);
uint8_t UART_LIN_Checksum(uint8_t lin_id, uint8_t data[], uint32_t count, bool enhanced_checksum);
void UART_ABRStart(UART_TypeDef * UARTx, uint32_t detectChar);
uint32_t UART_ABRIsDone(UART_TypeDef * UARTx);
void UART_INTEn(UART_TypeDef * UARTx, uint32_t it);
void UART_INTDis(UART_TypeDef * UARTx, uint32_t it);
void UART_INTClr(UART_TypeDef * UARTx, uint32_t it);
uint32_t UART_INTStat(UART_TypeDef * UARTx, uint32_t it);
#endif //__SWM221_UART_H__

@ -0,0 +1,195 @@
/******************************************************************************************************************************************
* : SWM221_usart.c
* : SWM221USART
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.0.0 2016130
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM221.h"
#include "SWM221_usart.h"
/******************************************************************************************************************************************
* : USART_Init()
* : USART
* : USART_TypeDef * USARTx UARTUSART0
* USART_InitStructure * initStruct USART
* :
* :
******************************************************************************************************************************************/
void USART_Init(USART_TypeDef * USARTx, USART_InitStructure * initStruct)
{
switch((uint32_t)USARTx)
{
case ((uint32_t)USART0):
SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_USART0_Pos);
break;
}
USART_Close(USARTx); //一些关键寄存器只能在串口关闭时设置
USARTx->MR = (0 << USART_MR_MODE_Pos) |
(0 << USART_MR_CLKS_Pos) |
(1 << USART_MR_OVER8_Pos) |
(initStruct->DataBits << USART_MR_NBDATA_Pos) |
(initStruct->Parity << USART_MR_PARITY_Pos) |
(initStruct->StopBits << USART_MR_NBSTOP_Pos);
USARTx->BAUD = ((SystemCoreClock/initStruct->Baudrate / 8) << USART_BAUD_IDIV_Pos) |
((SystemCoreClock/initStruct->Baudrate % 8) << USART_BAUD_FDIV_Pos);
USARTx->RXTO = initStruct->TimeoutTime;
USARTx->IER = (initStruct->RXReadyIEn << USART_IER_RXRDY_Pos) |
(initStruct->TXReadyIEn << USART_IER_TXRDY_Pos) |
(initStruct->TimeoutIEn << USART_IER_RXTO_Pos);
if(initStruct->RXReadyIEn | initStruct->TXReadyIEn | initStruct->TimeoutIEn)
{
switch((uint32_t)USARTx)
{
case ((uint32_t)USART0): NVIC_EnableIRQ(USART0_IRQn); break;
}
}
}
/******************************************************************************************************************************************
* : USART_Open()
* : USART
* : USART_TypeDef * USARTx USARTUSART0
* :
* :
******************************************************************************************************************************************/
void USART_Open(USART_TypeDef * USARTx)
{
USARTx->CR = USART_CR_RXEN_Msk |
USART_CR_TXEN_Msk;
}
/******************************************************************************************************************************************
* : USART_Close()
* : USART
* : USART_TypeDef * USARTx USARTUSART0
* :
* :
******************************************************************************************************************************************/
void USART_Close(USART_TypeDef * USARTx)
{
USARTx->CR = USART_CR_RXDIS_Msk |
USART_CR_TXDIS_Msk |
USART_CR_RSTRX_Msk |
USART_CR_RSTTX_Msk |
USART_CR_RSTSTA_Msk;
}
/******************************************************************************************************************************************
* : USART_SetBaudrate()
* :
* : USART_TypeDef * USARTx USARTUSART0
* uint32_t baudrate
* :
* : 使USART_Close()
******************************************************************************************************************************************/
void USART_SetBaudrate(USART_TypeDef * USARTx, uint32_t baudrate)
{
USARTx->BAUD = ((SystemCoreClock/baudrate / 8) << USART_BAUD_IDIV_Pos) |
((SystemCoreClock/baudrate % 8) << USART_BAUD_FDIV_Pos);
}
/******************************************************************************************************************************************
* : USART_GetBaudrate()
* :
* : USART_TypeDef * USARTx USARTUSART0
* : uint32_t
* :
******************************************************************************************************************************************/
uint32_t USART_GetBaudrate(USART_TypeDef * USARTx)
{
return SystemCoreClock/(((USARTx->BAUD & USART_BAUD_IDIV_Msk) >> USART_BAUD_IDIV_Pos) * 8 +
((USARTx->BAUD & USART_BAUD_FDIV_Msk) >> USART_BAUD_FDIV_Pos));
}
/******************************************************************************************************************************************
* : USART_LINConfig()
* : USART LIN
* : USART_TypeDef * USARTx USARTUSART0
* uint32_t mode LIN USART_LIN_MASTERUSART_LIN_SLAVE
* uint32_t checksum USART_CHECKSUM_LIN13USART_CHECKSUM_LIN20
* uint32_t it interrupt type USART_IT_LIN_IDUSART_IT_LIN_DONE
* :
* :
******************************************************************************************************************************************/
void USART_LINConfig(USART_TypeDef * USARTx, uint32_t mode, uint32_t checksum, uint32_t it)
{
USARTx->MR &= ~USART_MR_MODE_Msk;
USARTx->MR |= (mode << USART_MR_MODE_Pos);
USARTx->LINMR = (USART_LIN_IGNORE << USART_LINMR_NACT_Pos) |
(0 << USART_LINMR_PARDIS_Pos) |
(0 << USART_LINMR_CHKDIS_Pos) |
(checksum << USART_LINMR_CHKTYP_Pos) |
(0 << USART_LINMR_RDLMOD_Pos) |
(0 << USART_LINMR_FSMDIS_Pos) |
(0 << USART_LINMR_SYNCDIS_Pos);
USART_INTEn(USARTx, it);
}
/******************************************************************************************************************************************
* : USART_LINStart()
* : USART LIN Master
* : USART_TypeDef * USARTx USARTUSART0
* uint32_t slave_id ID
* uint32_t action USART_LIN_PUBLISHUSART_LIN_SUBSCRIBEUSART_LIN_IGNORE
* uint32_t count
* uint32_t checksum USART_CHECKSUM_LIN13USART_CHECKSUM_LIN20
* :
* :
******************************************************************************************************************************************/
void USART_LINStart(USART_TypeDef * USARTx, uint32_t slave_id, uint32_t action, uint32_t count, uint32_t checksum)
{
USARTx->LINMR &= ~(USART_LINMR_NACT_Msk | USART_LINMR_DLC_Msk | USART_LINMR_CHKTYP_Msk);
USARTx->LINMR |= (action << USART_LINMR_NACT_Pos) |
((count - 1) << USART_LINMR_DLC_Pos) |
(checksum << USART_LINMR_CHKTYP_Pos);
USARTx->LINID = slave_id;
}
/******************************************************************************************************************************************
* : USART_LINResponse()
* : USART LIN Slave
* : USART_TypeDef * USARTx USARTUSART0
* uint32_t action USART_LIN_PUBLISHUSART_LIN_SUBSCRIBEUSART_LIN_IGNORE
* uint32_t count
* uint32_t checksum USART_CHECKSUM_LIN13USART_CHECKSUM_LIN20
* :
* :
******************************************************************************************************************************************/
void USART_LINResponse(USART_TypeDef * USARTx, uint32_t action, uint32_t count, uint32_t checksum)
{
USARTx->LINMR &= ~(USART_LINMR_NACT_Msk | USART_LINMR_DLC_Msk | USART_LINMR_CHKTYP_Msk);
USARTx->LINMR |= (action << USART_LINMR_NACT_Pos) |
((count - 1) << USART_LINMR_DLC_Pos) |
(checksum << USART_LINMR_CHKTYP_Pos);
}

@ -0,0 +1,134 @@
#ifndef __SWM221_USART_H__
#define __SWM221_USART_H__
typedef struct {
uint32_t Baudrate;
uint8_t DataBits; //数据位位数可取值USART_DATA_5BIT、USART_DATA_6BIT、USART_DATA_7BIT、USART_DATA_8BIT、USART_DATA_9BIT
uint8_t Parity; //奇偶校验位可取值USART_PARITY_NONE、USART_PARITY_EVEN、USART_PARITY_ODD、USART_PARITY_ZERO、USART_PARITY_ONE
uint8_t StopBits; //停止位位数可取值USART_STOP_1BIT、USART_STOP_1BIT_5、USART_STOP_2BIT
uint8_t RXReadyIEn; //RHR 非空,可以读取
uint8_t TXReadyIEn; //THR 空,可以写入
uint8_t TimeoutIEn; //超时中断,超过 TimeoutTime/Baudrate 秒没有在RX线上接收到数据时触发中断
uint16_t TimeoutTime; //超时时长 = TimeoutTime/Baudrate 秒
} USART_InitStructure;
#define USART_DATA_5BIT 0
#define USART_DATA_6BIT 1
#define USART_DATA_7BIT 2
#define USART_DATA_8BIT 3
#define USART_DATA_9BIT (1 << 11)
#define USART_PARITY_NONE 4
#define USART_PARITY_EVEN 0
#define USART_PARITY_ODD 1
#define USART_PARITY_ZERO 2
#define USART_PARITY_ONE 3
#define USART_STOP_1BIT 0
#define USART_STOP_1BIT_5 1 //1.5bit
#define USART_STOP_2BIT 2
#define USART_LIN_MASTER 10
#define USART_LIN_SLAVE 11
#define USART_LIN_PUBLISH 0
#define USART_LIN_SUBSCRIBE 1
#define USART_LIN_IGNORE 2
#define USART_CHECKSUM_LIN13 1
#define USART_CHECKSUM_LIN20 0
/* Interrupt Type */
#define USART_IT_RX_RDY USART_IER_RXRDY_Msk //RHR 非空,可以读取
#define USART_IT_TX_RDY USART_IER_TXRDY_Msk //THR 空,可以写入
#define USART_IT_RX_TO USART_IER_RXTO_Msk //接收超时
#define USART_IT_TX_EMPTY USART_IER_TXEMPTY_Msk //THR 和 发送移位寄存器皆空
#define USART_IT_ERR_OVR USART_IER_OVRERR_Msk //移除错误
#define USART_IT_ERR_FRAME USART_IER_FRAMERR_Msk //帧格式错误
#define USART_IT_ERR_PARITY USART_IER_PARITYERR_Msk //校验错误
#define USART_IT_LIN_BRK USART_IER_BRK_Msk //LIN Break Sent or Received
#define USART_IT_LIN_ID USART_IER_ID_Msk //LIN Identifier Sent or Received
#define USART_IT_LIN_DONE USART_IER_DONE_Msk
#define USART_IT_LIN_BITERR USART_ISR_BITERR_Msk
#define USART_IT_LIN_SYNCERR USART_ISR_SYNCERR_Msk
#define USART_IT_LIN_IDERR USART_ISR_IDERR_Msk
#define USART_IT_LIN_CHKERR USART_ISR_CHKERR_Msk
#define USART_IT_LIN_NAKERR USART_ISR_NAKERR_Msk
#define USART_IT_LIN_HDRTO USART_ISR_HDRTO_Msk
void USART_Init(USART_TypeDef * UARTx, USART_InitStructure * initStruct); //UART串口初始化
void USART_Open(USART_TypeDef * UARTx);
void USART_Close(USART_TypeDef * UARTx);
void USART_SetBaudrate(USART_TypeDef * UARTx, uint32_t baudrate); //设置波特率
uint32_t USART_GetBaudrate(USART_TypeDef * UARTx); //获取当前使用的波特率
void USART_LINConfig(USART_TypeDef * USARTx, uint32_t mode, uint32_t checksum, uint32_t it);
void USART_LINStart(USART_TypeDef * USARTx, uint32_t slave_id, uint32_t action, uint32_t count, uint32_t checksum);
void USART_LINResponse(USART_TypeDef * USARTx, uint32_t action, uint32_t count, uint32_t checksum);
static inline void USART_Write(USART_TypeDef * USARTx, uint32_t data)
{
USARTx->THR = data;
}
static inline uint32_t USART_Read(USART_TypeDef * USARTx)
{
return USARTx->RHR & USART_RHR_DATA_Msk;
}
static inline void USART_INTEn(USART_TypeDef * USARTx, uint32_t it)
{
USARTx->IER = it;
}
static inline void USART_INTDis(USART_TypeDef * USARTx, uint32_t it)
{
USARTx->IDR = it;
}
static inline void USART_INTClr(USART_TypeDef * USARTx, uint32_t it)
{
if(it & USART_IT_RX_TO)
{
USARTx->CR = USART_CR_STTTO_Msk;
}
if(it & (USART_IT_ERR_OVR |
USART_IT_ERR_FRAME |
USART_IT_ERR_PARITY |
USART_IT_LIN_BRK |
USART_IT_LIN_ID |
USART_IT_LIN_DONE |
USART_IT_LIN_BITERR |
USART_IT_LIN_SYNCERR |
USART_IT_LIN_IDERR |
USART_IT_LIN_CHKERR |
USART_IT_LIN_NAKERR |
USART_IT_LIN_HDRTO))
{
USARTx->CR = USART_CR_RSTSTA_Msk;
}
}
static inline uint32_t USART_INTStat(USART_TypeDef * USARTx, uint32_t it)
{
return USARTx->ISR & it;
}
#endif //__SWM221_USART_H__

@ -0,0 +1,153 @@
/******************************************************************************************************************************************
* : SWM221_wdt.c
* : SWM221WDT
* : http://www.synwit.com.cn/e/tool/gbook/?bid=1
* :
* : V1.0.0 2016130
* :
*
*
*******************************************************************************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
* -ECTION WITH THEIR PRODUCTS.
*
* COPYRIGHT 2012 Synwit Technology
*******************************************************************************************************************************************/
#include "SWM221.h"
#include "SWM221_wdt.h"
/******************************************************************************************************************************************
* : WDT_Init()
* : WDT
* : WDT_TypeDef * WDTx WDT
* uint32_t int_period 1--655341/10000WDT
* uint32_t rst_period 1--655341/10000WDT
* :
* : WDT WDT_ReInit()
******************************************************************************************************************************************/
void WDT_Init(WDT_TypeDef * WDTx, uint32_t int_period, uint32_t rst_period)
{
SYS->CLKEN0 |= (1 << SYS_CLKEN0_WDT_Pos);
WDTx->CR &= ~WDT_CR_CLKDIV_Msk;
WDTx->CR |= (4 << WDT_CR_CLKDIV_Pos); //时钟32分频
if(int_period == 0)
{
WDTx->CR &= ~(1 << WDT_CR_INTEN_Pos);
NVIC_DisableIRQ(WDT_IRQn);
}
else
{
WDTx->CR |= (1 << WDT_CR_INTEN_Pos);
WDTx->INTVAL = int_period;
WDTx->IF = 1;
NVIC_EnableIRQ(WDT_IRQn);
}
if(rst_period == 0)
{
WDTx->CR &= ~(1 << WDT_CR_RSTEN_Pos);
WDTx->RSTVAL = int_period + 1;
}
else
{
WDTx->CR |= (1 << WDT_CR_RSTEN_Pos);
WDTx->RSTVAL = rst_period;
}
}
/******************************************************************************************************************************************
* : WDT_ReInit()
* : WDT
* : WDT_Init()
* :
* : WDT_ReInit() WDT_Stop() WDT
******************************************************************************************************************************************/
void WDT_ReInit(WDT_TypeDef * WDTx, uint32_t int_period, uint32_t rst_period)
{
int i;
/* WDT 已经在运行中,若新设置的 rst_period 比当前计数器值还小WDT 需要计数到 2^16 溢出返回 0 才能触发中断和复位,
*/
WDT_Feed(WDTx);
/* 等待 WDT 内部完成喂狗操作,计数器清零 */
for(i = 0; i < CyclesPerUs * 300 / 4; i++) __NOP();
WDT_Stop(WDTx);
WDT_Init(WDTx, int_period, rst_period);
}
/******************************************************************************************************************************************
* : WDT_Start()
* : WDT
* : WDT_TypeDef * WDTx WDT
* :
* :
******************************************************************************************************************************************/
void WDT_Start(WDT_TypeDef * WDTx)
{
WDTx->CR |= (1 << WDT_CR_EN_Pos);
}
/******************************************************************************************************************************************
* : WDT_Stop()
* : WDT
* : WDT_TypeDef * WDTx WDT
* :
* :
******************************************************************************************************************************************/
void WDT_Stop(WDT_TypeDef * WDTx)
{
WDTx->CR &= ~(1 << WDT_CR_EN_Pos);
}
/******************************************************************************************************************************************
* : WDT_Feed()
* :
* : WDT_TypeDef * WDTx WDT
* :
* :
******************************************************************************************************************************************/
void WDT_Feed(WDT_TypeDef * WDTx)
{
if(WDTx->CR & WDT_CR_EN_Msk) // WDT 停止状态下,不执行喂狗
WDTx->FEED = 0x55;
}
/******************************************************************************************************************************************
* : WDT_INTClr()
* :
* : WDT_TypeDef * WDTx WDT
* :
* :
******************************************************************************************************************************************/
void WDT_INTClr(WDT_TypeDef * WDTx)
{
WDTx->IF = 1;
}
/******************************************************************************************************************************************
* : WDT_INTStat()
* :
* : WDT_TypeDef * WDTx WDT
* : int32_t 1 0
* :
******************************************************************************************************************************************/
uint32_t WDT_INTStat(WDT_TypeDef * WDTx)
{
return WDTx->IF;
}

@ -0,0 +1,16 @@
#ifndef __SWM221_WDT_H__
#define __SWM221_WDT_H__
void WDT_Init(WDT_TypeDef * WDTx, uint32_t int_period, uint32_t rst_period);
void WDT_ReInit(WDT_TypeDef * WDTx, uint32_t int_period, uint32_t rst_period);
void WDT_Start(WDT_TypeDef * WDTx); //启动指定WDT开始倒计时
void WDT_Stop(WDT_TypeDef * WDTx); //关闭指定WDT停止倒计时
void WDT_Feed(WDT_TypeDef * WDTx); //喂狗,重新从装载值开始倒计时
void WDT_INTClr(WDT_TypeDef * WDTx); //中断标志清除
uint32_t WDT_INTStat(WDT_TypeDef * WDTx); //中断状态查询
#endif //__SWM221_WDT_H__

@ -0,0 +1,8 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\SWM221_StdPeriph_Driver.ewp</path>
</project>
<batchBuild/>
</workspace>

@ -0,0 +1,538 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>SWM221</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\out\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>0</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>4</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U59400009 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0SWM221x8.FLM -FS00 -FL020000 -FP0($$Device:SWM221xB$Flash\SWM221xB.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name></Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<WatchWindow1>
<Ww>
<count>0</count>
<WinNumber>1</WinNumber>
<ItemText>SystemCoreClock,0x0A</ItemText>
</Ww>
<Ww>
<count>1</count>
<WinNumber>1</WinNumber>
<ItemText>((SYS_TypeDef *) (0x40000000 + 0x00000))</ItemText>
</Ww>
<Ww>
<count>2</count>
<WinNumber>1</WinNumber>
<ItemText>((PWM_TypeDef *) (0x40040000 + 0x6000))</ItemText>
</Ww>
<Ww>
<count>3</count>
<WinNumber>1</WinNumber>
<ItemText>((PORT_TypeDef *) (0x400A0000 + 0x0000))</ItemText>
</Ww>
<Ww>
<count>4</count>
<WinNumber>1</WinNumber>
<ItemText>((SYS_TypeDef *) (0x40000000 + 0x00000))</ItemText>
</Ww>
<Ww>
<count>5</count>
<WinNumber>1</WinNumber>
<ItemText>((PORT_TypeDef *) (0x400A0000 + 0x0010))</ItemText>
</Ww>
</WatchWindow1>
<MemoryWindow1>
<Mm>
<WinNumber>1</WinNumber>
<SubType>1</SubType>
<ItemText>0x400AA000</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow1>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<SystemViewers>
<Entry>
<Name>System Viewer\GPIOA</Name>
<WinId>35905</WinId>
</Entry>
</SystemViewers>
</TargetOption>
</Target>
<Group>
<GroupName>APP</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>.\app\main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>CSL\StdPD</GroupName>
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<PathWithFileName>.\CSL\SWM221_StdPeriph_Driver\SWM221_exti.c</PathWithFileName>
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<PathWithFileName>.\CSL\SWM221_StdPeriph_Driver\SWM221_timr.c</PathWithFileName>
<FilenameWithoutPath>SWM221_timr.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
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<File>
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<FilenameWithoutPath>SWM221_uart.c</FilenameWithoutPath>
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</File>
<File>
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<bDave2>0</bDave2>
<PathWithFileName>.\CSL\SWM221_StdPeriph_Driver\SWM221_adc.c</PathWithFileName>
<FilenameWithoutPath>SWM221_adc.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
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</File>
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<PathWithFileName>.\CSL\SWM221_StdPeriph_Driver\SWM221_div.c</PathWithFileName>
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</File>
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<FilePath>.\CSL\CMSIS\DeviceSupport\system_SWM221.c</FilePath>
</File>
<File>
<FileName>startup_SWM221.s</FileName>
<FileType>2</FileType>
<FilePath>.\CSL\CMSIS\DeviceSupport\startup\arm\startup_SWM221.s</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
</RTE>
<LayerInfo>
<Layers>
<Layer>
<LayName>SWM221_StdPeriph_Driver</LayName>
<LayPrjMark>1</LayPrjMark>
</Layer>
</Layers>
</LayerInfo>
</Project>

@ -0,0 +1,3 @@
功能说明:
1、使接在PA5上的LED闪烁
2、通过串口打印"Hello World!"

@ -0,0 +1,4 @@
1.串口可收发数据
2.CAN可收发数据
3.协议已完成,扩展帧
4.最新上传代码 V1.0
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