commit edd6abfb82ea34501723d695faddea7bf929bbd8 Author: masst Date: Sat May 17 11:45:08 2025 +0800 赛鸽项目CAN协议第一次提交，目前已实现串口和CAN数据收发，协议完成10个 diff --git a/SWM221_Lib/.gitignore b/SWM221_Lib/.gitignore new file mode 100644 index 0000000..3755da9 --- /dev/null +++ b/SWM221_Lib/.gitignore @@ -0,0 +1,63 @@ +out/ +*.uvguix.* +JLinkLog.txt +JLinkSettings.ini +EventRecorderStub.scvd + +settings/ +*.dep +*.ewd +*.ewt + +# Prerequisites +*.d + +# Object files +*.o +*.ko +*.obj +*.elf + +# Linker output +*.ilk +*.map +*.exp + +# Precompiled Headers +*.gch +*.pch + +# Libraries +*.lib +*.a +*.la +*.lo + +# Shared objects (inc. Windows DLLs) +*.dll +*.so +*.so.* +*.dylib + +# Executables +*.exe +*.out +*.app +*.i*86 +*.x86_64 +*.hex + +# Debug files +*.dSYM/ +*.su +*.idb +*.pdb + +# Kernel Module Compile Results +*.mod* +*.cmd +.tmp_versions/ +modules.order +Module.symvers +Mkfile.old +dkms.conf diff --git a/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/CircleBuffer.h b/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/CircleBuffer.h new file mode 100644 index 0000000..03c68f6 --- /dev/null +++ b/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/CircleBuffer.h @@ -0,0 +1,149 @@ +#include +#include + + +#define cb_item_t uint8_t // item type + +#define CB_ITEM_N 1024 // item number，实际可存入数据少一个，留一个空位表示满，以区别于空 + + +typedef struct +{ + cb_item_t buf[CB_ITEM_N]; + int wrptr; // 写指针 + int rdptr; // 读指针 +} CircleBuffer_t; + + +/* Element Count in buffer */ +static int CirBuf_Count(CircleBuffer_t *cirbuf) +{ + return (cirbuf->wrptr - cirbuf->rdptr) & (CB_ITEM_N - 1); +} + +/* Space available in buffer */ +static int CirBuf_Space(CircleBuffer_t *cirbuf) +{ + return (cirbuf->rdptr - cirbuf->wrptr - 1) & (CB_ITEM_N - 1); +} + +static int CirBuf_Empty(CircleBuffer_t *cirbuf) +{ + return CirBuf_Count(cirbuf) == 0; +} + +static int CirBuf_Full(CircleBuffer_t *cirbuf) +{ + return CirBuf_Space(cirbuf) == 0; +} + +static void CirBuf_Clear(CircleBuffer_t *cirbuf) +{ + cirbuf->rdptr = cirbuf->wrptr; +} + +/** + * @brief 向环形缓冲区中写入数据 + * @param cirbuf 环形缓冲区结构体指针 + * @param buf 源数据缓冲区指针 + * @param num 请求写入的数据项数量 + * @return int 实际写入的数据项数量 + */ +static int CirBuf_Write(CircleBuffer_t *cirbuf, cb_item_t *buf, int num) { + int n; // 临时变量，记录当前可写入的空间大小 + + // 情况1：写指针(wrptr)在读指针(rdptr)之后或相等（未绕环） + if (cirbuf->wrptr >= cirbuf->rdptr) { + // 计算从写指针到缓冲区末尾的剩余空间（CB_ITEM_N - wrptr） + n = CB_ITEM_N - cirbuf->wrptr; + + // 特殊情况：如果读指针在0位置，需保留一个空位以避免与读指针重合（判断缓冲区满的条件） + if (cirbuf->rdptr == 0) + n -= 1; // 减少一个可写入位置 + + // 取最小值：避免写入数量超过当前段剩余空间 + n = (n >= num) ? num : n; + + // 将数据从源缓冲区拷贝到环形缓冲区 + memcpy(&cirbuf->buf[cirbuf->wrptr], buf, n * sizeof(cb_item_t)); + + // 更新写指针（考虑绕环） + cirbuf->wrptr = (cirbuf->wrptr + n) % CB_ITEM_N; + + // 终止条件：已写入足够数量或缓冲区已满 + if ((n == num) || CirBuf_Full(cirbuf)) { + return n; + } + // 递归写入剩余数据（从缓冲区头部开始） + else { + return n + CirBuf_Write(cirbuf, &buf[n], num - n); + } + } + // 情况2：写指针(wrptr)在读指针(rdptr)之前（已绕环） + else { + // 计算剩余可写入空间（rdptr - wrptr - 1） + n = CirBuf_Space(cirbuf); + + // 取最小值：避免写入数量超过剩余空间 + n = (n >= num) ? num : n; + + // 拷贝数据到环形缓冲区 + memcpy(&cirbuf->buf[cirbuf->wrptr], buf, n * sizeof(cb_item_t)); + + // 更新写指针（线性增加，无需绕环） + cirbuf->wrptr += n; + + return n; // 返回实际写入数量 + } +} + +/** + * @brief 从环形缓冲区中读取数据 + * @param cirbuf 环形缓冲区结构体指针 + * @param buf 目标存储缓冲区指针 + * @param num 请求读取的数据项数量 + * @return int 实际读取的数据项数量 + */ +static int CirBuf_Read(CircleBuffer_t *cirbuf, cb_item_t *buf, int num) { + int n; // 临时变量，记录当前可读取的数据量 + + // 情况1：写指针(wrptr)在读指针(rdptr)之后或相等（未绕环） + if (cirbuf->wrptr >= cirbuf->rdptr) { + // 计算可读取的数据项数量（wrptr - rdptr） + n = CirBuf_Count(cirbuf); + + // 取最小值：避免请求数量超过实际可读数量 + n = (n >= num) ? num : n; + + // 从环形缓冲区拷贝数据到目标缓冲区 + memcpy(buf, &cirbuf->buf[cirbuf->rdptr], n * sizeof(cb_item_t)); + + // 更新读指针（线性增加） + cirbuf->rdptr += n; + + return n; // 返回实际读取数量 + } + // 情况2：写指针(wrptr)在读指针(rdptr)之前（已绕环） + else { + // 计算从读指针到缓冲区末尾的数据项数量（CB_ITEM_N - rdptr） + n = CB_ITEM_N - cirbuf->rdptr; + + // 取最小值：避免请求数量超过当前段可读数量 + n = (n >= num) ? num : n; + + // 拷贝当前段数据到目标缓冲区 + memcpy(buf, &cirbuf->buf[cirbuf->rdptr], n * sizeof(cb_item_t)); + + // 更新读指针（考虑绕环） + cirbuf->rdptr = (cirbuf->rdptr + n) % CB_ITEM_N; + + // 终止条件：已读取足够数量或缓冲区为空 + if ((n == num) || CirBuf_Empty(cirbuf)) { + return n; + } + // 递归读取剩余数据（从缓冲区头部开始） + else { + return n + CirBuf_Read(cirbuf, &buf[n], num - n); + } + } +} diff --git a/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/jw_bsp_init.c b/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/jw_bsp_init.c new file mode 100644 index 0000000..41c00f3 --- /dev/null +++ b/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/jw_bsp_init.c @@ -0,0 +1,114 @@ +#include "jw_bsp_init.h" +#include "SWM221.h" + +/* + * SerialInit + * ܣʼUART0ͨ + * + * ֵ + * עPA.0ΪUART0_RXPA.1ΪUART0_TX + * 576008λݣУ飬1λֹͣλ + * FIFOֵշ3ֽʱжδʹܣ + * ճʱʱ10λ嵥λοӲֲᣩʱжδʹ + */ +static void SerialInit(void) +{ + UART_InitStructure UART_initStruct; + + // PA0ΪUART0չܣ + PORT_Init(PORTA, PIN0, PORTA_PIN0_UART0_RX, 1); + // PA1ΪUART0͹ܣ + PORT_Init(PORTA, PIN1, PORTA_PIN1_UART0_TX, 0); + + // ʼUARTýṹ + UART_initStruct.Baudrate = 115200; // 115200bps + UART_initStruct.DataBits = UART_DATA_8BIT; // 8λλ + UART_initStruct.Parity = UART_PARITY_NONE; // У + UART_initStruct.StopBits = UART_STOP_1BIT; // 1λֹͣλ + UART_initStruct.RXThreshold = 3; // FIFOֵ3ֽ + UART_initStruct.RXThresholdIEn = 1; // ֵж + UART_initStruct.TXThreshold = 3; // FIFOֵ3ֽ + UART_initStruct.TXThresholdIEn = 0; // ÷ֵж + UART_initStruct.TimeoutTime = 10; // ճʱʱ䣨λӲ10ַʱδյµ򴥷ʱж + UART_initStruct.TimeoutIEn = 1; // óʱж + + // ӦòUART0 + UART_Init(UART0, &UART_initStruct); // ʼUART0 + UART_Open(UART0); // UART0ͨ +} + +/* CAN˿ڳʼ */ +static void CanInit(void) +{ + CAN_InitStructure CAN_initStruct; // CANʼṹ + + // ʼPORTB78ΪCAN0RX/TX + // ˿, ź, ù, /ʹܣ1-ʹܣ0-ã + PORT_Init(PORTB, PIN7, PORTB_PIN7_CAN0_RX, 1); // CAN0 + PORT_Init(PORTB, PIN8, PORTB_PIN8_CAN0_TX, 0); // CAN0 + + // CANʼ + CAN_initStruct.Mode = CAN_MODE_NORMAL; //ģʽ // Բģʽ̽TXRXCAN_MODE_SELFTEST;// + CAN_initStruct.CAN_bs1 = CAN_BS1_5tq; // λʱ1ռ5ʱ䵥λ + CAN_initStruct.CAN_bs2 = CAN_BS2_4tq; // λʱ2ռ4ʱ䵥λ + CAN_initStruct.CAN_sjw = CAN_SJW_2tq; // ͬת2ʱ䵥λ + CAN_initStruct.Baudrate = 500000; // 500kbps + CAN_initStruct.RXNotEmptyIEn = 1; // ýж + CAN_initStruct.ArbitrLostIEn = 0; // ٲöʧж + CAN_initStruct.ErrPassiveIEn = 1; // ô󱻶ж + CAN_Init(CAN0, &CAN_initStruct); // ӦóʼCAN0 + + /* CANж */ + CAN_INTEn(CAN0, CAN_IT_ERR_WARN | CAN_IT_RX_OVERFLOW); + +// /* 16λIDģʽ */ +// CAN_SetFilter16b(CAN0, CAN_FILTER_1, 0x200, 0x7FE, 0x101, 0x7F8); //ID1:0x200,0x201; ID2:0x101~0x104 +// CAN_SetFilter16b(CAN0, CAN_FILTER_2, 0x130, 0x7FF, 0x150, 0x7FF); //ID1:0x130; ID2:0x150 +// CAN_SetFilter16b(CAN0, CAN_FILTER_3, 0x500, 0x7FC, 0x600, 0x7FC); //ID1:0x500~0x503; ID2:0x600~0x602 +// CAN_SetFilter16b(CAN0, CAN_FILTER_4, 0x640, 0x7FF, 0x650, 0x7FF); //ID1:0x640; ID2:0x650 +// CAN_SetFilter16b(CAN0, CAN_FILTER_5, 0x630, 0x7FF, 0x631, 0x7FE); //ID1:0x630; ID2:0x631~0x632 +// +// /* 32λIDģʽ */ +// CAN_SetFilter32b(CAN0, CAN_FILTER_6, 0x1000FFA0, 0x1FF8FFFF); //չIDΪ0x1000FFAx~0x1004FFAx֡ +// CAN_SetFilter32b(CAN0, CAN_FILTER_7, 0x1011FFA7, 0x1FFEFFFF); //չIDΪ0x1011FFA7,0x1012FFA7֡ +// CAN_SetFilter32b(CAN0, CAN_FILTER_8, 0x1020FFA0, 0x1FF0FFFF); //չIDΪ0x1020FFAx~0x1028FFAx֡ +// CAN_SetFilter32b(CAN0, CAN_FILTER_9, 0x1030FFA0, 0x1FFCFFFF); //չIDΪ0x1030FFAx~0x1033FFAx֡ + + CAN_Open(CAN0); // CAN0 +} + +/** + * @brief SysTickʱΪ1msжһ + * @note ʼʧܣʱԴ쳣򽫽ѭ + */ +static void SysTick_Configuration(void) +{ + /* SysTick_Config1msжϣ + - SystemCoreClock/1000ʾCPUʱӷƵΪ1KHz + - ط0ֵʾʧܣʱԴδ */ + if (SysTick_Config(SystemCoreClock / 1000)) // 1ms tick + { + LOG("SysTick ERROR !!!\r\n"); + /* ʼʧʱ */ + while (1); + } + + /* SysTickжȼΪߣ0x00 + - SysTick_IRQnںжϵöٱʶ */ + NVIC_SetPriority(SysTick_IRQn, 0x00); +} + +void SysTick_Handler(void) +{ + //Timer_Task_1ms(); +} + +/********** ϵͳʼ ********/ +void bsp_init(void) +{ + SystemInit(); + GPIO_Init(GPIOA, PIN3, 1, 0, 1, 0); //MCUʹ + SerialInit(); //ڳʼ + CanInit(); + SysTick_Configuration(); // SysTickϵͳʱڲʱжϣ +} diff --git a/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/jw_bsp_init.h b/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/jw_bsp_init.h new file mode 100644 index 0000000..6b3d3e8 --- /dev/null +++ b/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/jw_bsp_init.h @@ -0,0 +1,12 @@ +#ifndef _JW_BSP_INIT_H__ +#define _JW_BSP_INIT_H__ + +#include "JW_RTT.h" + +#define LOG(format,...) jw_log(format, ##__VA_ARGS__) +#define LOG_ORG(format,...) print_log(format, ##__VA_ARGS__) + +extern void bsp_init(void); + +#endif + diff --git a/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/jw_can.c b/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/jw_can.c new file mode 100644 index 0000000..3f49a0c --- /dev/null +++ b/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/jw_can.c @@ -0,0 +1,2 @@ +#include "jw_can.h" +#include "SWM221.h" diff --git a/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/jw_can.h b/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/jw_can.h new file mode 100644 index 0000000..73d2131 --- /dev/null +++ b/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/jw_can.h @@ -0,0 +1,838 @@ +/********************************************************* +*** 6CANЭ飺general_cmd,MC,BMS,VCU,HIMI,ABS,ƿغУ״ ********** +*** V1.10 ********** +**********************************************************/ +#ifndef __JW_CAN_H__ +#define __JW_CAN_H__ + +#include +#include + +/******************* ͨ general_cmd *******************/ +typedef struct{ + struct{ + uint8_t main_sw_ver; //汾 + uint8_t sub_sw_ver; //Ӱ汾 + uint8_t min_sw_ver; //С汾 + uint8_t main_hw_ver; //Ӳ汾 + uint8_t sub_hw_ver; //ӲӰ汾 + uint8_t min_hw_ver; //ӲС汾 + uint16_t rsv; + }info_1_0x0101; + struct{ + uint8_t sn_pack_num; //SN(0SN0~5 1SN6~11 2SN12~17) + uint8_t sn_total_lenght;//SNܳ + uint8_t sn_data[6]; //SN + }info_2_0x0102; +}General_info_query; //ͨϢѯ + +typedef struct{ + uint8_t bus_control; //߿(0߼ 1߾Ĭ) +}General_set_0x0201; //ͨ + +typedef struct{ + struct{ + uint32_t file_leng; //ļ + uint32_t total_pack_num;//ܰ + }ota_star_0x01; //OTAʼ + struct{ + uint32_t pack_number; // + uint32_t pack_crc; //CRC + }pack_info_0x02; //ǰϢ + uint8_t data_0x03[8]; + struct{ + uint32_t pack_number; // + uint16_t pack_crc; //CRC + uint16_t rsv; + }verify_pack_0x04; //У鵱ǰ + uint8_t ota_end_0x05[8]; //OTA +}OTA_cmd_0x10; + +/******************* MC *******************/ +//ܿѡ +typedef enum { + Off = 0x00, // رչ + On = 0x01, // + Invalid = 0x03 // Ч +}Fun_State; + +/* ƹɫö٣ЭӦ */ +typedef enum { + COLOR_NO_REQUEST = 0x0, + COLOR_WHITE = 0x1, + COLOR_1 = 0x2, + COLOR_2 = 0x3, + COLOR_3 = 0x4, + COLOR_4 = 0x5, + COLOR_5 = 0x6, + COLOR_6 = 0x7, + COLOR_7 = 0x8, + COLOR_RANDOM = 0x9, + COLOR_RESERVED = 0xA // 0xA~0xFΪֵ +} color_set; + +/* ܿ״̬ */ +typedef enum { + FUNC_OFF = 0x00, + FUNC_ON = 0x01, + FUNC_INVALID= 0x03 +}Rq_sta; //״̬ + +typedef enum { + no_req = 0x0, + white_until = 0x1, + yellow_until = 0x2, + white_flash = 0x3, + yellow_flash = 0x4, + req_off = 0x5 +}upper_set; //ǰյԶ + +// ܿã0x20_0x01 +typedef struct { + struct { + uint8_t voltage_select : 4; // 0:48V, 1:60V, 2:72V, 0xF:Ч + uint8_t startup_mode : 4; // 0:, 1:׼, 2:˶, 0xF:Ч + } byte0; + struct { + uint8_t gear_select : 4; //λѡ 0-5, 0xF:Ч + uint8_t reserved : 4; + } byte1; + uint8_t OV_threshold; //ѹֵ byte2 + uint8_t UV_threshold; //Ƿѹֵ byte3 + uint8_t bus_current; //ĸߵ byte4 + uint8_t phase_current; //ߵ byte5 + struct { + uint8_t vehicle_type : 4; // 0:, 1:Ħ, 2:Ħ + uint8_t battery_mode : 1; // 0:Ǧ, 1:﮵ + uint8_t supported_voltages : 3; // bit5:48V, bit6:60V, bit7:72V + } byte6; + uint8_t reserved_byte7; // byte7 +}MC_fun_swit_0x2001; + +// ܿأ0x20_0x02 +typedef struct { + struct { + uint8_t speed_limit : 2; // bit0-1 + uint8_t cruise_control : 2; // bit2-3 Ѳ + uint8_t rsv1 : 2; // bit4-5 + uint8_t hill_holder : 2; // bit6-7 פ¹ + } byte0; + struct { + uint8_t hdc : 2; // bit0-1 » + uint8_t tcs : 2; // bit2-3 TCS + uint8_t push_assist : 2; // bit4-5 Ƴ + uint8_t energy_recovery : 2; // bit6-7 + } byte1; + struct { + uint8_t soft_start : 2; // bit0-1 Ӳ + uint8_t seat_detect : 2; // bit2-3 + uint8_t stand_detect : 2; // bit4-5 ߳ż + uint8_t rsv2 : 2; // bit6-7 + } byte2; +}MC_fun_swit_0x2002; + +// ܿƣ0x21_0x01 +typedef struct { + uint8_t power_output; // 0:ر, 1: +}MC_Fun_Control_0x2101; + +typedef struct { + struct { + uint8_t voltage_select : 4; // 0:48V, 1:60V, 2:72V, 0xF:Ч + uint8_t startup_mode : 4; // 0:, 1:׼, 2:˶, 0xF:Ч + } byte0; + struct { + uint8_t gear_select : 4; //λѡ 0-5, 0xF:Ч + uint8_t reserved : 4; + } byte1; + uint8_t OV_threshold; //ѹֵ byte2 + uint8_t UV_threshold; //Ƿѹֵ byte3 + uint8_t bus_current; //ĸߵ byte4 + uint8_t phase_current; //ߵ byte5 + struct { + uint8_t vehicle_type : 4; // 0:, 1:Ħ, 2:Ħ + uint8_t battery_mode : 1; // 0:Ǧ, 1:﮵ + uint8_t supported_voltages : 3; // bit5:48V, bit6:60V, bit7:72V + } byte6; + uint8_t rsv_byte7; // byte7 +}MC_Sys_Info_0x2201; //ϵͳϢ 200ms + +typedef struct { + struct { + uint8_t speed_limit : 2; // bit0-1 + uint8_t cruise_control : 2; // bit2-3 Ѳ + uint8_t rsv1 : 2; // bit4-5 + uint8_t hill_holder : 2; // bit6-7 פ¹ + } byte0; + struct { + uint8_t hdc : 2; // bit0-1 » + uint8_t tcs : 2; // bit2-3 TCS + uint8_t push_assist : 2; // bit4-5 Ƴ + uint8_t energy_recovery : 2; // bit6-7 + } byte1; + struct { + uint8_t soft_start : 2; // bit0-1 Ӳ + uint8_t seat_detect : 2; // bit2-3 + uint8_t stand_detect : 2; // bit4-5 ߳ż + uint8_t rsv2 : 2; // bit6-7 + } byte2; +}MC_Sys_Info_0x2202; //ϵͳϢ 200ms + +typedef struct { + struct { + uint32_t MOSFET:1; //MOSFET + uint32_t Drive:1; // + uint32_t OC:1; // + uint32_t OV:1; //ѹ + uint32_t OT:1; //¹ + uint32_t UV:1; //Ƿѹ + uint32_t Motor_phase_loss:1; //ȱ + uint32_t Motor_Hall:1; // + + uint32_t Motor_OT:1; //¹ + uint32_t Motor_block:1; //ת + uint32_t Throttle:1; //תѹ + uint32_t Brake_failure:1; //ɲ + uint32_t rsv:20; + }Fault; + struct { + uint32_t Gear:3; //λ + uint32_t Brake:1; //ɲ״̬ + uint32_t Anti_theft:1; //״̬ + uint32_t Speed_limit:1; //״̬ + uint32_t Cruising:1; //Ѳ״̬ + uint32_t Reverse:1; //״̬ + + uint32_t EBS:1; //EBS״̬ + uint32_t Hill_Holder:1; //פ״̬ + uint32_t HDC:1; //»״̬ + uint32_t Temple_prot:1; //ű״̬ + uint32_t READY:1; //READY״̬ + uint32_t Charge_prot:1; //籣״̬ + uint32_t TCS_fun_enable:1; //TCSʹ + uint32_t Pause_or_disable:1; //P/״̬ + + uint32_t Gravity_detect:1; // + uint32_t stand_detect : 1; //߳ż + uint32_t rsv:14; + }State; +}MC_RealTime_0x2301; //ʵʱ 200ms + +typedef struct{ + struct{ + uint8_t speed_G:4; //0x0ٿ;0x1D1;0x2D2 ;0x3D3 + uint8_t P_G:1; + uint8_t R_G:1; + uint8_t T_G:1; + uint8_t rsv:1; + }Gear_position; + uint16_t Motor_speed; //ת + uint8_t Motor_temp; //¶ + uint16_t speed; //ٶ +}MC_RealTime_0x2302; //ʵʱ 200ms + +typedef struct{ + uint16_t vol; //ʵʱѹ + uint16_t cur; //ʵʱ + uint8_t dump_energy; //ʣ + uint8_t control_temp; //¶ +}MC_RealTime_0x2303; //ʵʱ 2000ms + +typedef struct{ + uint16_t Tyre_speed; //̥ת + uint16_t Tyre_C; //̥ܳ + uint8_t Throttle_value; //תѿ + uint8_t Brake_value; //ɲ +}MC_RealTime_0x2304; //ʵʱ 500ms + +typedef struct{ + uint16_t total_miler; // + uint16_t once_miler; // + uint16_t endurance_miler; // +}MC_RealTime_0x2305; //ʵʱ 2000ms + +/******************* BMS *******************/ +typedef struct{ + struct{ + uint16_t normal_dischg:1; //ŵ + uint16_t normal_chg:1; // + uint16_t chg_OV_prot:1; //ѹ + uint16_t bat_LV_prot:1; //صѹ + uint16_t chg_OC_prot:1; // + uint16_t dischg_OC_prot:1; //ŵ + uint16_t bat_dischg_OT_prot:1; //طŵȱ + uint16_t bat_dischg_LT_prot:1; //طŵ± + + uint16_t bat_open_circuit:1; //鿪· + uint16_t dischg_SCP:1; //ŵ· + uint16_t bat_chg_OT_prot:1; //سȱ + uint16_t bat_chg_UT_prot:1; //س± + uint16_t MOS_OT_prot:1; //·MOSȱ + uint16_t temp_sensor_failure:1; //¶ȴϣ/· + uint16_t chg_MOS_on:1; //MOS + uint16_t dischgg_MOS_on:1; //ŵMOS + }failure; + uint16_t realtime_cur; //ʵʱ + uint16_t realtime_vol; //ʵʱѹ + uint8_t max_bat_temp; //¶ + uint8_t min_bat_temp; //¶ +}BMS_RealTime_status1_0x2301; //ʵʱ״̬1 500ms + +typedef struct{ + uint8_t state_of_charge; //ʣSOC + uint8_t state_of_health; //ؽSOH + uint16_t max_dischg_cur; //ŵ + uint16_t max_chg_cur; // + uint16_t max_chg_vol; //ѹ +}BMS_RealTime_status2_0x2302; //ʵʱ״̬2 1000ms + +typedef struct{ + uint16_t full_bat_capa; // + uint16_t remain_bat_capa; //ʣ + uint16_t time_of_chg; //ѳ + uint8_t External_signal_sta; //ⲿź״̬ + uint8_t chg_time_remain; //ʣʱ +}BMS_RealTime_status3_0x2303; //ʵʱ״̬3 1000ms + +//BMSչ֡ +typedef struct { + uint8_t main_hw_ver; // byte0: Ӳ汾 (0-99) + uint8_t sub_hw_ver; // byte1: Ӳ汾 (0-99) + uint8_t main_sw_ver; // byte2: 汾 (0-99) + uint8_t sub_sw_ver; // byte3: 汾 (0-99) + struct { + uint8_t boot1_main :4; // byte44λ: BOOT1汾 (0-15) + uint8_t boot1_sub :4; // byte44λ: BOOT1ΰ汾 (0-15) + } boot1; + struct { + uint8_t boot2_mai:4; // byte54λ: BOOT2汾 (0-15) + uint8_t boot2_sub :4; // byte54λ: BOOT2ΰ汾 (0-15) + } boot2; + uint8_t main_proto_ver; // byte6: ͨЭ汾 (0-99) + uint8_t sub_proto_ver; // byte7: ͨЭ汾 (0-99) +}BMS_ver_info_t; //汾Ϣ 2000ms + +typedef struct{ + uint8_t product_model; // byte0: Ʒͺ (0-99) + uint8_t hard_code; // byte1: Ӳ̴ (0-254) + uint16_t customer_code; // byte2-3: ͻ (˴洢) + uint16_t designer_code; // byte4-5: ƳҴ (˴洢) + uint8_t reserved[2]; // byte6-7: Ԥ +}BMS_mf_info; //Ϣ 2000ms + +typedef struct{ + uint8_t year; + uint8_t month; + uint8_t day; +}BMS_product_date; //Ϣ 2000ms + +typedef struct{ + uint8_t sn[4]; +}BMS_sn_num; //BMSк 2000ms + +typedef enum { + sanyuan = 0x00, //Ԫ + LiFePO = 0x01, // + LMO, // + LFMP, // + sealed, //Ǧ + NiH, // + LiCoO, // + LiTiO, // + Na, // + solid, //̬ + Multic_dop //Ԫ +}battery_type; + +typedef struct{ + uint16_t vol; //ѹ + uint8_t cap; // + uint8_t series_num; // + uint8_t parallel_num; // + battery_type bat_type; // +}BMS_Nominal_para; // 2000ms + +typedef enum { + Not = 0x00, //޸ð + Free, // + Discharge, //ŵ + Charge, // + Feedback, // + Off_line, // + Unincorporated, //δ + Heat // +}work_state; + +typedef enum { + Nott = 0x00, //޸ð + One_chg, // + One_dischg, //ŵ + Two_chg, //˫ + Two_dischg, //˫ŵ + three_chg, // + three_dischg, //ŵ + four_chg, //İ + four_dischg, //İŵ +}parallel_sta;//״̬ + +typedef struct{ + work_state sta0; + work_state sta1; + work_state sta2; + work_state sta3; + work_state sta4; + work_state sta5; + work_state sta6; + work_state sta7; + parallel_sta pll_sta; //״̬ +}BMS_work_state;//״̬ 100ms + +typedef struct{ + uint16_t total_vol; //ܵѹ + int16_t total_cur; //ܵ + uint16_t total_soc; //ܵصʣʱ + uint16_t average_soc; //ƽSOC +}BMS_vol_cur; //ѹ 100ms + +typedef struct{ + int16_t Instant_DC; //ܵ˲ʱŵ + int16_t ststain_DC; //ܵŵ + int16_t ststain_chg; + //ܵ + int16_t Feedback_cur; + //ܵ +}BMS_SOP; //SOP 100ms + +typedef enum { + mos_off = 0x00, + mos_on = 0x01, + rsv = 0x02, + Void = 0x03 +}mos_sta; + +typedef enum { + INvalid = 0x00, + valid = 0x01 +}effecf; //ЧЧ + +typedef struct{ + uint16_t vol; + int16_t cur; + struct{ + mos_sta DMOS:2; + mos_sta CMOS:2; + mos_sta pre_dmos:2; //ԤŵMOS + mos_sta heat_mos:2; //MOS + }mos_state; + uint8_t rsv; + struct{ + effecf ACC_signal:1; //ACCź + effecf ON_signal:1; //ONź + effecf CRG_signal:1; //CRGź + }sign_info; +}BMS_VOL_MOS; //ذѹMOSϢ 100ms + +typedef struct{ + uint16_t dischg; //ŵ + uint16_t chg; // +}BMS_instant_cur; //˲ʱ 100ms + +typedef struct{ + uint16_t plus; //˾Ե + uint16_t minus; //˾Ե +}BMS_insulate_test; //Ե 500ms + +typedef struct{ + uint16_t SOC; //ٷֱ + uint16_t SOH; //ϵ + uint16_t cycle; //ѭ +}BMS_SOX_info; //SOXϢ 500ms + +typedef struct{ + uint16_t full_cap; // + uint16_t surplus_cap; //ʣ + uint16_t SOE; //ʣ + uint16_t full_tome; //ʣʱ +}BMS_surplus_capa; //ʣϢ 500ms + +typedef struct{ + uint16_t min; + uint16_t max; +}BMS_vol_vaule; //ѹ 500ms + +typedef struct{ + uint16_t chg; // + uint16_t Feedback; // + uint16_t dischg; //ŵ +}BMS_cur_vaule; // 500ms + +typedef struct{ + uint8_t high; //ߵо + uint8_t low; //͵о + uint8_t mos_high; //MOS + uint8_t envir; // +}BMS_temp_vaule; //¶ֵ 500ms + +#pragma pack(push, 1) + +typedef struct { + struct { + // Byte 0 + uint8_t single_OV :2; // B0.0-1 ѹ + uint8_t single_UV :2; // B0.2-3 Ƿѹ + uint8_t total_OV :2; // B0.4-5 ѹѹ + uint8_t total_UV :2; // B0.6-7 ѹǷѹ + }b0; + + struct { + // Byte 1 + uint8_t DC_OT : 2; // B1.0-1,ŵ + uint8_t DC_LT : 2; // B1.2-3,ŵ + uint8_t C_OT : 2; // B1.4-5, + uint8_t C_LT : 2; // B1.6-7, + }b1; + + struct { + // Byte 2 + uint8_t temp_diff:2; // B2.0-1,² + uint8_t COC:2; // B2.2-3, + uint8_t feedback_OC:2; // B2.4-5, + uint8_t DOC:2; // B2.6-7,ŵ + }b2; + + struct { + // Byte 3 + uint8_t D_inst_OC : 2; // B3.0-1,ŵ˲ʱ + uint8_t insulation_low : 2; // B3.2-3,Ե + uint8_t soc_low : 2; // B3.4-5 + uint8_t bat_id_conflict: 2; // B3.6-7,idͻ + }b3; + + // Byte 4 (ر־λ) + struct { + uint8_t AFE_comm_fault : 1; // B4.0,AFEͨѶ쳣 + uint8_t vol_collect_f:1; // B4.1,زɼ쳣 + uint8_t temp_collect_f:1; // B4.2,¶Ȳɼ쳣 + uint8_t balance_OT:1; // B4.3, + uint8_t MOS_OT:1; // B4.4,MOS + uint8_t preC_R_HT:1; // B4.5,Ԥ + uint8_t pre_timeout :1; // B4.6,Ԥ䳬ʱ + uint8_t pre_OC:1; // B4.7,Ԥ + }b4; + + + // Byte 5 (ر־λ) + struct { + uint8_t AFE_OV :1; // B5.0 + uint8_t AFE_UV :1; // B5.1 + uint8_t AFE_DOC:1; // B5.2 + uint8_t AFE_COC :1; // B5.3 + uint8_t AFE_SC:1; // B5.4,AFE· + uint8_t AFE_COT :1; // B5.5 + uint8_t AFE_CLT :1; // B5.6 + uint8_t AFE_DOT:1; // B5.7 + }b5; + + + // Byte 6 (ر־λ) + struct { + uint8_t AFE_DLT:1; // B6.0 + uint8_t float_chg:1; // B6.1, + uint8_t OV_stop_chg:1; // B6.2,OV + uint8_t precast_mos:1; // B6.3,ԤMOS + uint8_t DMOS_stick:1; // B6.4,ŵMOSճ + uint8_t CMOS_stick :1; // B6.5,MOSճ + uint8_t precast_mos_f:1;// B6.6,ԤMOS쳣 + uint8_t DMOS_drv_f:1; // B6.7,ŵMOS쳣 + }b6; + + // Byte 7 (ر־λ) + struct { + uint8_t CMOS_drv_f:1; // B7.0,MOS쳣 + uint8_t EOL_state:1; // B7.1 + uint8_t over_OV:1; // B7.2,ѹعѹ + uint8_t rsv1:1; // B7.3 + uint8_t rsv2:1; // B7.4 + uint8_t rsv3:1; // B7.5 + uint8_t C_P:1; // B7.6,籣 + uint8_t DC_P:1; // B7.7,ŵ籣 + }b7; +}BMS_fault_info; //Ϣ 500ms + +#pragma pack(pop) + +typedef struct { + struct + { + uint8_t index : 5; //ı (B0.0-B0.4) + uint8_t num : 3; //ѹ (B0.5-B0.7) + }b0; // B0ֽ + uint8_t vol[7]; +}BMS_vol_info; //صѹϢ 500ms + +typedef struct { + struct + { + uint8_t index : 5; //ı (B0.0-B0.4) + uint8_t num : 3; // ¶ȸ (B0.5-B0.7) + }b0; // B0ֽ + int8_t temp[7]; // ¶ֵ (B1-B7) +} BMS_temp_info; //¶Ϣ 500ms + +typedef struct{ + uint8_t one_year; //ʵʱʱ- + uint8_t month; + uint8_t day; + uint8_t hour; + uint8_t min; + uint8_t sec; + uint16_t rsv; +}BMS_time_info; //ʵʱʱϢ 500ms + +typedef struct{ + uint8_t index; + uint8_t SN_num[7]; +}BMS_PACK_SN; //ذPack SN 100ms + +/******************* VCU *******************/ +typedef struct{ + struct{ + uint32_t ACC_enable:1; //0:ACC OFF1:ACC ON + uint32_t garrison:1; //0:1: + uint32_t network_connect:1; //1:ӳɹ + uint32_t GPS:1; //1:λɹ + uint32_t ble_connect:1; //1: + uint32_t temple:1; //1:߳λ״̬ + uint32_t Cushion_detecte:1; //1:/λ״̬ + uint32_t PKE:1; //1:PKEӦ״̬ + + uint32_t rotor_heat:1; //1:תѼ + uint32_t cushion_heat:1; //1: + uint32_t faucet_lock:1; //1:ͷ״̬ + uint32_t rsv1:5; + + uint32_t shake_alarm:1; //1:𶯱 + uint32_t rotation_alarm:1; //1:ֶ + uint32_t Vehicle_dump:1; //1:㵹 + uint32_t rsv2:13; + }state; + struct{ + uint32_t SIM_card:1; //1:SIM + uint32_t abnor_network_reg:1; //1:ע쳣 + uint32_t ble_abnormal:1; //1:쳣 + uint32_t gps_abnormal:1; //1:λ쳣 + uint32_t rsv1:4; + + uint32_t control_comm:1; //1:ͨŹ + uint32_t instrument_comm:1; //1:DZͨŹ + uint32_t BMS_comm:1; //1:BMSͨŹ + uint32_t ABS_comm:1; //1:ABSͨŹ + uint32_t charging_comm:1; //1:ͨŹ + uint32_t LED_comm:1; //1:ƿغͨŹ + uint32_t radar_comm:1; //1:״ͨŹ + uint32_t rsv2:17; + }fault; +}VCU_realtime_status_0x2301; //500ms + +typedef struct{ + uint32_t total_miler; // + uint16_t once_miler; // + uint16_t endurance_miler; // +}VCU_miler_0x2302; + +typedef struct{ + uint8_t hour; //Сʱ + uint8_t min; // +}VCU_time_0x2303; + +/******************* HIMI ******************/ +typedef struct{ + uint16_t speed_factor_set; //ٶϵ +}HIMI_fct_switch_set_0X2001; //ܿ + +typedef struct{ + uint32_t Total_distance; // + uint16_t Single_distance; // + uint8_t mode; //0ģʽ; 1ҹģʽ + uint8_t speed; // +}HIMI_realtime_status1_0X2301; //ʵʱ״̬1 + +/******************* ABS *******************/ +typedef struct{ + Fun_State fun_switch1; +}ABS_fun_swit_set_0x2001; //ܿ + +typedef struct{ + Fun_State fun_switch2; +}ABS_sys_info_0x2201; //ϵͳϢ 1000ms + +// ʵʱ״̬־λṹ壨ڴŻ +#pragma pack(push, 1) +typedef struct { + uint32_t fault_flag : 1; // bit0: ABSϣ0/1ϣ + uint32_t reserved : 31; // λ + uint32_t work_status : 1; // bit32: ABS״̬0/1У +}ABS_RealTime_Status1_0x2301; //ʵʱ״̬1 200ms +#pragma pack(pop) + +/******************* ƿغ *******************/ +typedef struct{ + struct { + uint8_t system_enable : 2; // bit0-1 + uint8_t reserved : 6; + } switch_status; // ƿϵͳ + color_set front_corridor:4; // ǰյʾ (bit0-3) + color_set front_LOGO:4; // ǰյLOGO (bit4-7) + color_set front_thick_wall:4; // ǰյƺڵ (bit0-3) + color_set back_corridor:4; // βʾ (bit4-7) + color_set back_LOGO:4; // βLOGO (bit0-3) +}LED_fun_swit_set_0x2001; + +/* ƹýṹ */ +typedef struct{ + struct{ + Rq_sta low_beam:4; //(bit0-3) + upper_set upper_beam:4; //Զ(bit4-7) + }front_t1; //byte0 ǰյ + struct{ + Rq_sta left_beam:2; //ǰյת(bit0-1) + Rq_sta left_side:2; //ǰյָʾ(bit2-3) + Rq_sta left_fill:2; //ǰյಹ(bit4-5) + Rq_sta right_beam:2; //ǰյת(bit6-7) + }front_t2; //byte1 + struct{ + Rq_sta right_side:2; //ǰյҲָʾ(bit0-1) + Rq_sta right_fill:2; //ǰյҲಹ(bit2-3) + Rq_sta both_side:2; //ǰյʾ(bit4-5) + Rq_sta LOGO_beam:2; //ǰյLOGO(bit6-7) + }front_t3; //byte2 + struct{ + Rq_sta thick_wall:2; //ǰյƺڵ(bit0-1) + Rq_sta drive_lamp:2; //βг(bit2-3) + Rq_sta stop_lamp:2; //βƶ(bit4-5) + Rq_sta left_t:2; //βת(bit6-7) + }back_t1; + struct{ + Rq_sta right_t:2; //βת(bit0-1) + Rq_sta corridor_t:2; //βʾ(bit2-3) + Rq_sta logo_t:2; //βLOGO(bit4-5) + }back_t2; +}LED_fun_cotrol_0x2101; + +typedef struct{ + Fun_State light_ctrl_box;//ƿغ +}LED_sys_info_t; //ϵͳϢ 1000ms + +typedef struct{ + struct{ + uint16_t light_t:1; //ƹܿ/βƿ + uint16_t high_beam:1; //Զƿ + uint16_t left_turn:1; //ת + uint16_t right_turn:1; //ת + uint16_t warn_light:1; //ʾƿ + uint16_t overtake_light:1; //ƿ + uint16_t rsv:10; + }switch_input; + struct{ + uint16_t tail_on:1; //βƿ + uint16_t high_beam_on:1; //Զƿ + uint16_t left_turn_on:1; //ת + uint16_t right_turn_on:1; //ת + uint16_t low_beam_on:1; //ƿ + uint16_t rsv:11; + }output_state; +}LED_realtime_status1_0x2301; //50ms + +/******************* ״rado *******************/ +typedef struct{ + struct{ + Fun_State radar_sys:2; //״ϵͳ + Fun_State warn_light:2; //Ԥƿ + Fun_State buzzer:2; // + Fun_State video:2; //¼񿪹 + }switch1; + struct{ + Fun_State behind_vehicle:2; //Ԥ + Fun_State left_vehicle:2; //෽Ԥ + Fun_State right_vehicle:2; //Ҳ෽Ԥ + }switch2; +}RADO_fun_switch_set_0x2001; //ܿ + +typedef struct{ + struct{ + Fun_State radar_sys:2; //״ϵͳ + Fun_State warn_light:2; //Ԥƿ + Fun_State buzzer:2; // + Fun_State video:2; //¼񿪹 + }switch1; + struct{ + Fun_State behind_vehicle:2; //Ԥ + Fun_State left_vehicle:2; //෽Ԥ + Fun_State right_vehicle:2; //Ҳ෽Ԥ + }switch2; +}RADO_sys_info_0x2201; //ϵͳϢ 1000ms + +typedef struct { + uint32_t faile; + struct{ + uint32_t left_level_1:1; //෽һԤ + uint32_t left_level_2:1; //෽Ԥ + uint32_t right_level_1:1; //Ҳ෽һԤ + uint32_t right_level_2:1; //Ҳ෽Ԥ + uint32_t behind_level_1:1; //һԤ + uint32_t behind_level_2:1; //Ԥ + }state; +}RADO_RealTime_status1_0x2301; //ʵʱ״̬1 100ms + +/******************* chargerչ *******************/ +typedef struct{ + uint8_t main_ver; //Э汾 + uint8_t sub_ver; //Эΰ汾 + uint32_t roll_code; // + uint16_t crc; +}charger_hs_ver_info; //ְ汾Ϣ 200ms + +typedef struct{ + uint16_t low_vol; //ѹ + uint16_t high_vol; //ѹ + uint16_t low_cur; // + uint16_t high_cur; // +}charger_output; // 200ms + +typedef struct{ + uint16_t rsv; + uint16_t vol; + uint16_t cur; +}charger_realtime_status;//ʵʱ״̬ 200ms + +typedef enum{ + Idle = 0, + precharge = 1, + charging = 2, + fail = 3, + full_of = 4 +}chg_sta; + +typedef struct{ + chg_sta state; //״̬ + chg_sta comm_fail; //ͨѶ + chg_sta chg_overtime; //糬ʱ +}charger_state; +/***************************************************************/ +#define CAN_SIZE_MAX 100U //CANidôС41 +#define QUEUE_BUFF_SIZE 36U + +//can +typedef struct +{ + uint32_t can_id; + uint8_t data[8]; +}can_data_t; + + + +/****************************** ⲿ ***********************************/ + + + +#endif diff --git a/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/jw_sys_timer.c b/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/jw_sys_timer.c new file mode 100644 index 0000000..f47fe53 --- /dev/null +++ b/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/jw_sys_timer.c @@ -0,0 +1,124 @@ +#include "jw_sys_timer.h" +#include "SWM221.h" +#include "jw_bsp_init.h" + +// ȫֱڼ¼ϵͳеtick뼶 +uint32_t m_getTick; + +extern void Timer_TASK_50msFunc(void); +extern void Timer_TASK_100msFunc(void); +extern void Timer_TASK_200msFunc(void); +extern void Timer_TASK_500msFunc(void); +extern void Timer_TASK_1000msFunc(void); +extern void Timer_TASK_2000msFunc(void); + +/* ָָͣ޲޷ֵĺ */ +typedef void (*TaskFunType)(void); + +/* ָ飬洢ĵַ */ +static TaskFunType TaskFunPtr[TASKFUNNUMBER] = +{ + &Timer_TASK_50msFunc, /* 1: 50ms */ + &Timer_TASK_100msFunc, /* 2: 100ms */ + &Timer_TASK_200msFunc, /* 3: 200ms */ + &Timer_TASK_500msFunc, /* 4: 500ms */ + &Timer_TASK_1000msFunc, /* 5: 1000ms */ + &Timer_TASK_2000msFunc /* 6: 2000ms */ +}; + +/** + * @brief 1msʱжϻص + * @note úÿ1msһΣڸ񴥷־ + */ +void Timer_Task_1ms(void) +{ + // ̬¼ϵͳʼĺ + static uint16_t Counterms = 0; + uint8_t i = 0; + + // ȫtick32λ + // ﵽ32λֵʱ㣬 + if (m_getTick == 0xFFFFFFFF) + { + m_getTick = 0; + } + else + { + m_getTick++; + } + + // Ƿ񳬹ֵ + if(Counterms > TASKMAXCOUNTER) + { + Counterms = 0; // ֵ + } + else + { + Counterms++; // + + // 񣬼ǷҪ + for(i = 0; i < TASKFUNNUMBER; i++) + { + // 鵱ǰֵǷĴ + if((Counterms % TimeArr[i].Period) == TimeArr[i].Remainder) + { + TaskFlag[i] = TRUE; // 񴥷־ + } + } + } +} + +/* ʱȺ */ +void Timer_MainFun(void) +{ + uint8_t i = 0; + + /* */ + for(i = 0; i < TASKFUNNUMBER; i++) + { + /* ־ǷΪTRUEҪִУ */ + if(TaskFlag[i] == TRUE) + { + /* ָǷЧ */ + if(TaskFunPtr[i] != NULL) + { + /* ִжӦ */ + TaskFunPtr[i](); + + /* ִɺ־ */ + TaskFlag[i] = FALSE; + } + } + } +} + +void Timer_TASK_50msFunc(void) +{ + +} + + +void Timer_TASK_100msFunc(void) +{ + +} + +void Timer_TASK_200msFunc(void) +{ + +} + +void Timer_TASK_500msFunc(void) +{ + +} + +void Timer_TASK_1000msFunc(void) +{ +// LOG("tiimer 1000ms...\r\n"); +} + +void Timer_TASK_2000msFunc(void) +{ + +} diff --git a/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/jw_sys_timer.h b/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/jw_sys_timer.h new file mode 100644 index 0000000..98237b9 --- /dev/null +++ b/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/jw_sys_timer.h @@ -0,0 +1,52 @@ +#ifndef __JW_SYS_TIMER_H__ +#define __JW_SYS_TIMER_H__ + +#include "SWM221.h" + +/* 岼ֵ */ +#define TRUE 1 +#define FALSE 0 + +/* Ϊ6 */ +#define TASKFUNNUMBER 6 +// ֵΪ6000޷ͣ +#define TASKMAXCOUNTER (6000U) + +typedef struct +{ + uint16_t Period; // ִڣms + uint16_t Remainder; // ļֵ +}TaskTimeType; + +/* ־飬ڱǸǷҪִ */ +/* ʼΪȫ0FALSEʾʼ״̬񶼲Ҫִ */ +static uint8_t TaskFlag[TASKFUNNUMBER] = {0, 0, 0, 0, 0,0}; +// ÿںھʱ +static TaskTimeType TimeArr[TASKFUNNUMBER] = +{ + {50,49}, // 1ÿ50msִУCounterms%50==49ʱ + {100, 97}, // 2ÿ100msִУCounterms%100==97ʱ + {200, 197}, // 3ÿ200msִУCounterms%200==197ʱ + {500, 497}, // 4ÿ500msִУCounterms%500==497ʱ + {1000, 999},// 5ÿ1000msִУCounterms%1000==999ʱ + {2000, 1999}// 6ÿ2000msִУCounterms%2000==1999ʱ +}; + +void Timer_MainFun(void); + + + + + + + + + + + + + + + +#endif + diff --git a/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/main.c b/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/main.c new file mode 100644 index 0000000..91f1457 --- /dev/null +++ b/SWM221_Lib/CAN/SimplCAN_RX_Int/APP/main.c @@ -0,0 +1,368 @@ +#include "SWM221.h" +#include "CircleBuffer.h" +#include "jw_can.h" +#include "jw_bsp_init.h" +#include "jw_sys_timer.h" + +/* 测试条件：SWM221 <==CAN_RX/TX==> CAN 收发器（如 TJA1050）<==CAN_H/L==> CAN 分析仪 + * 错误处理演示： + * 1、将 CAN 收发器与 CAN 分析仪断开，触发 ACK 错误，CAN->TXERR 从 0 递增到 128，然后保持不变 + * 2、将 SWM221 与 CAN 收发器断开，触发位错误，CAN->TXERR 继续递增到 255，触发 Bus Off，CAN->CR.RST 自动置 1，CAN 模块处于复位状态 + * 3、ISR 中在检测到 Bus Off 后执行 CAN_Open(CAN0) 使 CAN 模块退出复位状态，此时将上面断开的连接恢复，CAN->TXERR 将逐渐递减到0，CAN 模块恢复正常工作 +*/ +static can_data_t can_buff[CAN_SIZE_MAX] = { + /* MCU ID值, cnt-->11 */ + {.can_id = 0x101,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //参数设置 + {.can_id = 0x102,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //功能开关设置 + {.can_id = 0x103,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //功能控制 + {.can_id = 0x104,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //信息获取 + {.can_id = 0x500,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //版本信息 + {.can_id = 0x501,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //序列号 + {.can_id = 0x502,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //系统信息1 /*周期：1000ms*/ + {.can_id = 0x503,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //系统信息2 /*周期：1000ms*/ + {.can_id = 0x600,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //故障状态 /*周期：500ms*/ + {.can_id = 0x601,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //运行信息1 /*周期：200ms*/ + {.can_id = 0x602,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //功率输出状态 /*周期：500ms*/ + /* BMS ID值, cnt-->21 */ + {.can_id = 0x1000FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //版本信息 /*周期：2000ms*/ + {.can_id = 0x1001FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //厂商信息 /*周期：2000ms*/ + {.can_id = 0x1002FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包生产日期 /*周期：2000ms*/ + {.can_id = 0x1003FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包BMS序列号 /*周期：2000ms*/ + {.can_id = 0x1004FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包额定参数 /*周期：2000ms*/ + {.can_id = 0x1010FFA7,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包工作状态--汇总信息 /*周期：100ms*/ + {.can_id = 0x1011FFA7,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包电压电流--汇总信息 /*周期：100ms*/ + {.can_id = 0x1012FFA7,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包SOP--汇总信息 /*周期：100ms*/ + {.can_id = 0x1020FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包电压及MOS信息 /*周期：100ms*/ + {.can_id = 0x1021FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包瞬时充放电电流 /*周期：100ms*/ + {.can_id = 0x1022FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包绝缘检测信息 /*周期：500ms*/ + {.can_id = 0x1023FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包SOX估算信息 /*周期：500ms*/ + {.can_id = 0x1024FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包剩余容量信息 /*周期：500ms*/ + {.can_id = 0x1025FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包单体电压信息 /*周期：500ms*/ + {.can_id = 0x1026FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包持续电流信息 /*周期：500ms*/ + {.can_id = 0x1027FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包温度信息 /*周期：500ms*/ + {.can_id = 0x1028FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包故障信息 /*周期：500ms*/ + {.can_id = 0x1030FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包单体电压信息 /*周期：500ms*/ + {.can_id = 0x1031FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包温度信息 /*周期：500ms*/ + {.can_id = 0x1032FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包实时时间信息 /*周期：500ms*/ + {.can_id = 0x1033FFA0,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //电池包Pack SN码 /*周期：100ms*/ + /* VCU ID值, cnt-->4 */ + {.can_id = 0x630,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //系统状态 /*周期：200ms*/ + {.can_id = 0x631,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //辅助功能状态 /*周期：500ms*/ + {.can_id = 0x632,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //防盗 /*周期：500ms*/ + {.can_id = 0x130,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //控制指令 + /* HIMI ID值, cnt-->2 */ + {.can_id = 0x650,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //状态信息 /*周期：500ms*/ + {.can_id = 0x150,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //参数设置 + /* TBOX ID值, cnt-->1 */ + {.can_id = 0x640,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //状态信息 /*周期：500ms*/ + /* LED ID值, cnt-->2 */ + {.can_id = 0x200,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} }, //beam_control /*周期：100ms*/ + {.can_id = 0x201,.data = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF} } //beam_set /*周期：100ms*/ +}; + +volatile bool msg_rcvd = false; + +CircleBuffer_t CirBuf; +CircleBuffer_t TX_CirBuf; + +void SerialInit(void); +void UART_send(void); +void CAN_send_id(int id,uint8_t *pdat); + +//#define LOG printf +static uint8_t m_buf[1024]; + +/** + * @brief 在CAN数据库中查找指定ID的数据地址 + * @param id : 要查找的CAN消息ID + * @retval 成功返回对应数据的地址指针，失败返回NULL + */ +static __inline uint8_t *find_can_db(int id) +{ + int i = 0, idx = 0; // 循环计数器i，匹配索引idx + can_data_t *p_arry = can_buff; // 获取CAN数据库首地址 + + // 遍历整个CAN数据库 + for (; i < CAN_SIZE_MAX; i++) + { + // 比对当前项的CAN ID + if (p_arry[i].can_id == id) { + idx = i; // 记录匹配项的索引 + break; // 找到后立即退出循环 + } + } + + // 返回结果：如果遍历完未找到返回NULL，否则返回对应数据的地址 + return (i == CAN_SIZE_MAX) ? NULL : p_arry[idx].data; +} + +int main(void) +{ + int len=0,i; + uint8_t *pcan_dat = NULL; // 定义指向CAN数据的指针 + can_data_t can_dat = {0}; // 定义CAN数据结构体并初始化为0 + + bsp_init(); + segger_rtt_init(" [JW LOG]:---->>>> SG01 app start ! <<<----\r\n"); // 初始化SEGGER RTT调试日志 + + while(1) // 嵌入式系统典型的主循环（Super Loop）结构 + { +// //原CAN发送代码（已注释，保留供调试参考） +// uint8_t tx_data[8] = {1, 2, 3, 4, 5, 6, 7, 8},i; +// CAN_Transmit(CAN0, CAN_FRAME_STD, 0x104, tx_data, 8, 1); +// while(CAN_TXComplete(CAN0) == 0) __NOP(); // 阻塞等待CAN发送完成 +// printf("\r\nCAN->TXERR: %d\r\n", CAN0->TXERR); // 调试用：打印CAN发送错误计数 +// for(i=0;i<9;i++) +// { +// UART_WriteByte(UART0, tx_data[i]); // 写入UART发送寄存器 +// LOG(">>>>>>send data :%d <<<<<<\r\n",tx_data[i]); +// } + + /* 核心逻辑：UART消息处理与转发 */ + if(msg_rcvd) // 检测UART接收完成标志（由UART中断置位） + { + msg_rcvd = false; // 立即清除标志，避免重复处理 + + // 检查环形缓冲区数据有效性 + if(!CirBuf_Empty(&CirBuf)) + { + len = CirBuf_Count(&CirBuf); // 获取缓冲区数据长度 + + // 数据长度校验（12~1023字节为合法范围） + if( (len < 12) || (len > (1024-1)) ) + { + CirBuf_Clear(&CirBuf); // 非法数据清空缓冲区 + LOG(">>>>>>CAN data len:%d ERR! <<<<<<\r\n",len); // 记录错误日志 + } + else + { + /*错：此处串口发送的数据不对，需要修改*/ + // 有效数据处理流程： + CirBuf_Read(&CirBuf, (uint8_t *)m_buf, len); // 读取数据到m_buf + CAN_send_id((int)m_buf, &m_buf[4]); // 解析并发送CAN帧（假设前4字节为ID，后续为数据） + } + } + + // 启用UART发送中断（准备后续数据发送） + UART_INTEn(UART0, UART_IT_TX_THR); + } + +// /*--- CAN数据处理部分 ---*/ +// for(i = 0; i < CAN_SIZE_MAX; i++) // 遍历CAN数据库 +// { +// /*--- 常规CAN数据处理 ---*/ +// pcan_dat = find_can_db(can_dat.can_id); // 在CAN数据库查找对应ID +// if( pcan_dat == NULL ) +// { +// //LOG(">>>>>>>>>>>>> Not Find CAN id %08X <<<<<<<<<<<<<\n",can_dat.can_id); +// break; +// } +// memcpy(pcan_dat,can_dat.data,sizeof(can_dat.data)); // 拷贝数据到数据库 +// } + + // 主动触发UART发送（非中断驱动部分） + UART_send(); + + /*--- 定时任务处理 ---*/ + //Timer_MainFun(); + + // 延时控制（基于系统时钟的精确空操作延时） + for(int i = 0; i < SystemCoreClock / 16; i++) __NOP(); // 约62.5ms延时（SystemCoreClock=8MHz） + } +} + + +void CAN0_Handler(void) +{ + uint32_t can_if = CAN_INTStat(CAN0); + uint32_t id_p = 0; //id位置互换 + + // 处理接收数据可用中断 + if(can_if & CAN_IF_RXDA_Msk) + { + CAN_RXMessage msg; + + CAN_Receive(CAN0, &msg); + + if(msg.size > 0) + { + LOG_ORG(" Receive %s: %08X", msg.format == CAN_FRAME_STD ? "STD" : "EXT", msg.id); + for(int i = 0; i < msg.size; i++) + LOG_ORG(" %02X", msg.data[i]); + LOG("\n"); + if(msg.format == CAN_FRAME_STD) + { + id_p = (msg.id <<24)&0xff000000; + id_p |= (msg.id <<8)&0x00ff0000; + CirBuf_Write(&TX_CirBuf, (uint8_t *)&id_p, 4); + CirBuf_Write(&TX_CirBuf, (uint8_t *)msg.data, 8); + } + else + { + id_p = (msg.id <<24)&0xff000000; + id_p |= (msg.id <<8)&0x00ff0000; + id_p |= (msg.id >>24)&0x000000ff; + id_p |= (msg.id >>8)&0x0000ff00; + CirBuf_Write(&TX_CirBuf, (uint8_t *)&id_p, 4); + CirBuf_Write(&TX_CirBuf, (uint8_t *)msg.data, 8); + } + } + else if(msg.remote == 1) //远程帧 + { + LOG_ORG(" Receive %s Remote Request\r\n", msg.format == CAN_FRAME_STD ? "STD" : "EXT"); + } + } + + // 处理接收溢出中断 + if(can_if & CAN_IF_RXOV_Msk) + { + LOG_ORG(" CAN RX Overflow\r\n"); + + // 关闭CAN0模块以清除溢出状态 + CAN_Close(CAN0); + //延时确保CAN完全关闭 + for(int i = 0; i < CyclesPerUs; i++) __NOP(); + // 重新打开CAN0模块以恢复通信 + CAN_Open(CAN0); + } + + // 处理错误警告中断 + if(can_if & CAN_IF_ERRWARN_Msk) + { + // 检查是否发生总线关闭错误 + if(CAN0->SR & CAN_SR_BUSOFF_Msk) + { + LOG(" CAN Bus Off\r\n"); + LOG_ORG(" CAN->CR.RST = %d\r\n", CAN0->CR & CAN_CR_RST_Msk ? 1 : 0); + + // 尝试恢复总线连接 + CAN_Open(CAN0); //Bus Off recovery + } + else if(CAN0->SR & CAN_SR_ERRWARN_Msk) + { + LOG(" CAN Error Warning\r\n"); + } + } + + // 处理错误被动中断 + if(can_if & CAN_IF_ERRPASS_Msk) + { + LOG(" CAN Error Passive\r\n"); + } +} + + void CAN_send_id(int id,uint8_t *pdat) + { + int can_id = id; + uint8_t data[8] = {0}; + memcpy(data,pdat,8); + + CAN_Transmit(CAN0, CAN_FRAME_STD, can_id, data, 8, 1); + while(CAN_TXComplete(CAN0) == 0) __NOP(); + if( CAN0->TXERR ) + { + LOG(">>>>>>>>>>>>>>>>>>CAN Error CAN->TXERR: %d<<<<<<<<<<<<<<<<<<<<<\r\n", CAN0->TXERR); + } + } + +/** + * @brief UART0中断服务函数 + * 处理UART0的接收和发送中断，包括数据缓冲和状态管理 + */ +void UART0_Handler(void) +{ + uint32_t chr; // 临时存储读取/发送的字符 + + /* 接收中断处理（RX FIFO阈值中断或接收超时中断）*/ + if(UART_INTStat(UART0, UART_IT_RX_THR | UART_IT_RX_TOUT)) + { + // 循环读取RX FIFO直到为空 + while(UART_IsRXFIFOEmpty(UART0) == 0) + { + // 成功读取字节时写入环形缓冲区 + if(UART_ReadByte(UART0, &chr) == 0) + { + CirBuf_Write(&CirBuf, (uint8_t *)&chr, 1); // 写入接收缓冲区 + LOG(" uart RX... \r"); + } + } + + /* 特殊处理接收超时中断（数据流间隔触发）*/ + if(UART_INTStat(UART0, UART_IT_RX_TOUT)) + { + UART_INTClr(UART0, UART_IT_RX_TOUT); // 清除中断标志 + msg_rcvd = true; // 设置消息接收完成标志（可能用于主程序轮询） + LOG(" uart RX TOUT... \r"); + } + } + + /* 发送中断处理（TX FIFO阈值中断）*/ + if(UART_INTStat(UART0, UART_IT_TX_THR)) + { + // 当TX FIFO未满时持续发送数据 + while(!UART_IsTXFIFOFull(UART0)) + { + // 如果发送缓冲区有数据则取出并发送 + if(!CirBuf_Empty(&TX_CirBuf)) + { + CirBuf_Read(&TX_CirBuf, (uint8_t *)&chr, 1); // 从发送缓冲区读取 + UART_WriteByte(UART0, chr); // 写入UART发送寄存器 + LOG(" uart TX... \r"); + } + else + { + // 发送缓冲区为空时禁用TX中断（避免空转） + UART_INTDis(UART0, UART_IT_TX_THR); + LOG(" uart ERR... \r"); + break; // 退出发送循环 + } + } + } +} + +void UART_send(void) +{ + uint32_t chr = 0; + // if(UART_INTStat(UART1, UART_IT_TX_THR))//not chk TX_THR + { + while(!UART_IsTXFIFOFull(UART0)) + { + if(!CirBuf_Empty(&TX_CirBuf)) + { + CirBuf_Read(&TX_CirBuf, (uint8_t *)&chr, 1); + UART_WriteByte(UART0, chr); + while(UART_IsTXBusy(UART0)); //发送空闲跳出 + // while(UART_IsTXBusy(UART1))__NOP(); + // LOG("[ UART_send ] TX ->: %02X\n", chr&0xFF); + //LOG("handle TX msg_rcvd->: %d cnt:%d \r\n", msg_rcvd,CirBuf_Count(&CirBuf)); + } + else + { + UART_INTDis(UART0, UART_IT_TX_THR); + //LOG("~~~~~~~~Cycle TX buffer Empty~~~~~~~\n"); + break; + } + } + } +} + + +/********************************************************************************************* +* 函数名称: fputc() +* 功能说明: printf()使用此函数完成实际的串口打印动作 +* 输 入: int ch 要打印的字符 +* FILE *f 文件句柄 +* 输 出: 无 +* 注意事项: 无 +**********************************************************************************************/ +int fputc(int ch, FILE *f) +{ +#if 0 + UART_WriteByte(UART0, ch); + + while(UART_IsTXBusy(UART0)); +#endif + + + return ch; +} diff --git a/SWM221_Lib/CAN/SimplCAN_RX_Int/RTT/JW_Howto.txt b/SWM221_Lib/CAN/SimplCAN_RX_Int/RTT/JW_Howto.txt new file mode 100644 index 0000000..5778c8f --- /dev/null +++ b/SWM221_Lib/CAN/SimplCAN_RX_Int/RTT/JW_Howto.txt @@ -0,0 +1,17 @@ + + + +howto: + +JW invok： + +//#include "JW_RTT.h" +//segger_rtt_init("JW_RTT DBG start !"); +//print_log("print a log\n"); + + +for orignal invok + +//#include "SEGGER_RTT.h" +//SEGGER_RTT_Init(); +//SEGGER_RTT_printf(0, "Hi, World!\r\n"); \ No newline at end of file diff --git a/SWM221_Lib/CAN/SimplCAN_RX_Int/RTT/JW_RTT.c b/SWM221_Lib/CAN/SimplCAN_RX_Int/RTT/JW_RTT.c new file mode 100644 index 0000000..afff811 --- /dev/null +++ b/SWM221_Lib/CAN/SimplCAN_RX_Int/RTT/JW_RTT.c @@ -0,0 +1,50 @@ +/* SEGGER RTT ͷļ */ +#include +#include +#include "SEGGER_RTT.h" +#include "SEGGER_RTT_Conf.h" +#include "JW_RTT.h" + +#define BUFFER_INDEX 0 // ĬʹRTT0 +extern int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList); + +/** + * @brief ͨ־ӡ + * @param sFormat: ʽַ + * @param ...: ɱб + * @retval + */ +void print_log(const char * sFormat, ...) +{ + va_list ParamList; // ɱб + va_start(ParamList, sFormat); // ʼɱ + SEGGER_RTT_vprintf(BUFFER_INDEX, sFormat, &ParamList); // RTTӡ + va_end(ParamList); // ɱ +} + +/** + * @brief ʼSEGGER RTTӡʼϢ + * @param string: Ҫӡijʼַ + * @retval + */ +void segger_rtt_init(char * string) +{ + SEGGER_RTT_Init(); // ʼRTTģ + print_log(string); // ӡʼϢ +} + +/** + * @brief ǰ׺־ӡ(JWרøʽ) + * @param sFormat: ʽַ + * @param ...: ɱб + * @retval + */ +void jw_rtt_print_log(const char * sFormat, ...) +{ + va_list ParamList; + print_log("[JW_LOG]: --------->"); // ӡ̶ǰ׺ + + va_start(ParamList, sFormat); // ʼɱ + SEGGER_RTT_vprintf(BUFFER_INDEX, sFormat, &ParamList); // ӡʵ־ + va_end(ParamList); // ɱ +} \ No newline at end of file diff --git a/SWM221_Lib/CAN/SimplCAN_RX_Int/RTT/JW_RTT.h b/SWM221_Lib/CAN/SimplCAN_RX_Int/RTT/JW_RTT.h new file mode 100644 index 0000000..aedd271 --- /dev/null +++ b/SWM221_Lib/CAN/SimplCAN_RX_Int/RTT/JW_RTT.h @@ -0,0 +1,10 @@ +#ifndef __JW_RTT_H__ +#define __JW_RTT_H__ + +#define jw_log(format,...) print_log("[JW_LOG]: ---->");print_log(format, ##__VA_ARGS__) +#define jw_dbg(format,...) print_log("[JW_DBG]: ---->");print_log(format, ##__VA_ARGS__) +void print_log(const char * sFormat, ...); +void segger_rtt_init(char * str); +void jw_rtt_print_log(const char * sFormat, ...); + +#endif //JW_RTT_H diff --git a/SWM221_Lib/CAN/SimplCAN_RX_Int/RTT/SEGGER_RTT.c b/SWM221_Lib/CAN/SimplCAN_RX_Int/RTT/SEGGER_RTT.c new file mode 100644 index 0000000..6cc9ee4 --- /dev/null +++ b/SWM221_Lib/CAN/SimplCAN_RX_Int/RTT/SEGGER_RTT.c @@ -0,0 +1,1211 @@ +/********************************************************************* +* SEGGER MICROCONTROLLER GmbH & Co. KG * +* Solutions for real time microcontroller applications * +********************************************************************** +* * +* (c) 2014 - 2015 SEGGER Microcontroller GmbH & Co. KG * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* * This software may in its unmodified form be freely redistributed * +* in source form. * +* * The source code may be modified, provided the source code * +* retains the above copyright notice, this list of conditions and * +* the following disclaimer. * +* * Modified versions of this software in source or linkable form * +* may not be distributed without prior consent of SEGGER. * +* * This software may only be used for communication with SEGGER * +* J-Link debug probes. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* RTT version: 5.02k * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT.c +Purpose : Implementation of SEGGER real-time transfer (RTT) which + allows real-time communication on targets which support + debugger memory accesses while the CPU is running. + +Additional information: + Type "int" is assumed to be 32-bits in size + H->T Host to target communication + T->H Target to host communication + + RTT channel 0 is always present and reserved for Terminal usage. + Name is fixed to "Terminal" + +---------------------------------------------------------------------- +*/ + +#include "SEGGER_RTT.h" + +#include // for memcpy + +/********************************************************************* +* +* Configuration, default values +* +********************************************************************** +*/ + +#ifndef BUFFER_SIZE_UP + #define BUFFER_SIZE_UP 1024 // Size of the buffer for terminal output of target, up to host +#endif + +#ifndef BUFFER_SIZE_DOWN + #define BUFFER_SIZE_DOWN 16 // Size of the buffer for terminal input to target from host (Usually keyboard input) +#endif + +#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS + #define SEGGER_RTT_MAX_NUM_UP_BUFFERS 2 // Number of up-buffers (T->H) available on this target +#endif + +#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS + #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS 2 // Number of down-buffers (H->T) available on this target +#endif + +#ifndef SEGGER_RTT_MODE_DEFAULT + #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP +#endif + +#ifndef SEGGER_RTT_LOCK + #define SEGGER_RTT_LOCK(SavedState) +#endif + +#ifndef SEGGER_RTT_UNLOCK + #define SEGGER_RTT_UNLOCK(SavedState) +#endif + +#ifndef STRLEN + #define STRLEN(a) strlen((a)) +#endif + +#ifndef MEMCPY + #define MEMCPY(pDest, pSrc, NumBytes) memcpy((pDest), (pSrc), (NumBytes)) +#endif + +#ifndef MIN + #define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef MAX + #define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +// +// For some environments, NULL may not be defined until certain headers are included +// +#ifndef NULL + #define NULL 0 +#endif + +/********************************************************************* +* +* Static const data +* +********************************************************************** +*/ + +static unsigned char _aTerminalId[16] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' }; + +/********************************************************************* +* +* Static data +* +********************************************************************** +*/ +// +// Allocate buffers for channel 0 +// +static char _acUpBuffer [BUFFER_SIZE_UP]; +static char _acDownBuffer[BUFFER_SIZE_DOWN]; +// +// Initialize SEGGER Real-time-Terminal control block (CB) +// +SEGGER_RTT_CB _SEGGER_RTT; + +static char _ActiveTerminal; + +/********************************************************************* +* +* Static functions +* +********************************************************************** +*/ + +/********************************************************************* +* +* _DoInit() +* +* Function description +* Initializes the control block an buffers. +* May only be called via INIT() to avoid overriding settings. +* +*/ +#define INIT() do { \ + if (_SEGGER_RTT.acID[0] == '\0') { _DoInit(); } \ + } while (0) +static void _DoInit(void) { + SEGGER_RTT_CB* p; + // + // Initialize control block + // + p = &_SEGGER_RTT; + p->MaxNumUpBuffers = SEGGER_RTT_MAX_NUM_UP_BUFFERS; + p->MaxNumDownBuffers = SEGGER_RTT_MAX_NUM_DOWN_BUFFERS; + // + // Initialize up buffer 0 + // + p->aUp[0].sName = "Terminal"; + p->aUp[0].pBuffer = _acUpBuffer; + p->aUp[0].SizeOfBuffer = sizeof(_acUpBuffer); + p->aUp[0].RdOff = 0u; + p->aUp[0].WrOff = 0u; + p->aUp[0].Flags = SEGGER_RTT_MODE_DEFAULT; + // + // Initialize down buffer 0 + // + p->aDown[0].sName = "Terminal"; + p->aDown[0].pBuffer = _acDownBuffer; + p->aDown[0].SizeOfBuffer = sizeof(_acDownBuffer); + p->aDown[0].RdOff = 0u; + p->aDown[0].WrOff = 0u; + p->aDown[0].Flags = SEGGER_RTT_MODE_DEFAULT; + // + // Finish initialization of the control block. + // Copy Id string in three steps to make sure "SEGGER RTT" is not found + // in initializer memory (usually flash) by J-Link + // + strcpy(&p->acID[7], "RTT"); + strcpy(&p->acID[0], "SEGGER"); + p->acID[6] = ' '; +} + +/********************************************************************* +* +* _WriteBlocking() +* +* Function description +* Stores a specified number of characters in SEGGER RTT ring buffer +* and updates the associated write pointer which is periodically +* read by the host. +* The caller is responsible for managing the write chunk sizes as +* _WriteBlocking() will block until all data has been posted successfully. +* +* Parameters +* pRing Ring buffer to post to. +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* >= 0 - Number of bytes written into buffer. +*/ +static unsigned _WriteBlocking(SEGGER_RTT_BUFFER_UP* pRing, const char* pBuffer, unsigned NumBytes) { + unsigned NumBytesToWrite; + unsigned NumBytesWritten; + unsigned RdOff; + unsigned WrOff; + // + // Write data to buffer and handle wrap-around if necessary + // + NumBytesWritten = 0u; + WrOff = pRing->WrOff; + do { + RdOff = pRing->RdOff; // May be changed by host (debug probe) in the meantime + if (RdOff > WrOff) { + NumBytesToWrite = RdOff - WrOff - 1u; + } else { + NumBytesToWrite = pRing->SizeOfBuffer - (WrOff - RdOff + 1u); + } + NumBytesToWrite = MIN(NumBytesToWrite, (pRing->SizeOfBuffer - WrOff)); // Number of bytes that can be written until buffer wrap-around + NumBytesToWrite = MIN(NumBytesToWrite, NumBytes); + memcpy(pRing->pBuffer + WrOff, pBuffer, NumBytesToWrite); + NumBytesWritten += NumBytesToWrite; + pBuffer += NumBytesToWrite; + NumBytes -= NumBytesToWrite; + WrOff += NumBytesToWrite; + if (WrOff == pRing->SizeOfBuffer) { + WrOff = 0u; + } + pRing->WrOff = WrOff; + } while (NumBytes); + // + return NumBytesWritten; +} + +/********************************************************************* +* +* _WriteNoCheck() +* +* Function description +* Stores a specified number of characters in SEGGER RTT ring buffer +* and updates the associated write pointer which is periodically +* read by the host. +* It is callers responsibility to make sure data actually fits in buffer. +* +* Parameters +* pRing Ring buffer to post to. +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Notes +* (1) If there might not be enough space in the "Up"-buffer, call _WriteBlocking +*/ +static void _WriteNoCheck(SEGGER_RTT_BUFFER_UP* pRing, const char* pData, unsigned NumBytes) { + unsigned NumBytesAtOnce; + unsigned WrOff; + unsigned Rem; + + WrOff = pRing->WrOff; + Rem = pRing->SizeOfBuffer - WrOff; + if (Rem > NumBytes) { + // + // All data fits before wrap around + // + memcpy(pRing->pBuffer + WrOff, pData, NumBytes); + pRing->WrOff = WrOff + NumBytes; + } else { + // + // We reach the end of the buffer, so need to wrap around + // + NumBytesAtOnce = Rem; + memcpy(pRing->pBuffer + WrOff, pData, NumBytesAtOnce); + NumBytesAtOnce = NumBytes - Rem; + memcpy(pRing->pBuffer, pData + Rem, NumBytesAtOnce); + pRing->WrOff = NumBytesAtOnce; + } +} + +/********************************************************************* +* +* _PostTerminalSwitch() +* +* Function description +* Switch terminal to the given terminal ID. It is the caller's +* responsibility to ensure the terminal ID is correct and there is +* enough space in the buffer for this to complete successfully. +* +* Parameters +* pRing Ring buffer to post to. +* TerminalId Terminal ID to switch to. +*/ +static void _PostTerminalSwitch(SEGGER_RTT_BUFFER_UP* pRing, unsigned char TerminalId) { + char ac[2]; + + ac[0] = 0xFFu; + ac[1] = _aTerminalId[TerminalId]; // Caller made already sure that TerminalId does not exceed our terminal limit + _WriteBlocking(pRing, ac, 2u); +} + +/********************************************************************* +* +* _GetAvailWriteSpace() +* +* Function description +* Returns the number of bytes that can be written to the ring +* buffer without blocking. +* +* Parameters +* pRing Ring buffer to check. +* +* Return value +* Number of bytes that are free in the buffer. +*/ +static unsigned _GetAvailWriteSpace(SEGGER_RTT_BUFFER_UP* pRing) { + unsigned RdOff; + unsigned WrOff; + unsigned r; + // + // Avoid warnings regarding volatile access order. It's not a problem + // in this case, but dampen compiler enthusiasm. + // + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + if (RdOff <= WrOff) { + r = pRing->SizeOfBuffer - 1u - WrOff + RdOff; + } else { + r = RdOff - WrOff - 1u; + } + return r; +} + +/********************************************************************* +* +* Public code +* +********************************************************************** +*/ +/********************************************************************* +* +* SEGGER_RTT_ReadNoLock() +* +* Function description +* Reads characters from SEGGER real-time-terminal control block +* which have been previously stored by the host. +* Do not lock against interrupts and multiple access. +* +* Parameters +* BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. +* BufferSize Size of the target application buffer. +* +* Return value +* Number of bytes that have been read. +*/ +unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned BufferSize) { + unsigned NumBytesRem; + unsigned NumBytesRead; + unsigned RdOff; + unsigned WrOff; + unsigned char* pBuffer; + SEGGER_RTT_BUFFER_DOWN* pRing; + // + INIT(); + pRing = &_SEGGER_RTT.aDown[BufferIndex]; + pBuffer = (unsigned char*)pData; + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + NumBytesRead = 0u; + // + // Read from current read position to wrap-around of buffer, first + // + if (RdOff > WrOff) { + NumBytesRem = pRing->SizeOfBuffer - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); + memcpy(pBuffer, pRing->pBuffer + RdOff, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + // + // Handle wrap-around of buffer + // + if (RdOff == pRing->SizeOfBuffer) { + RdOff = 0u; + } + } + // + // Read remaining items of buffer + // + NumBytesRem = WrOff - RdOff; + NumBytesRem = MIN(NumBytesRem, BufferSize); + if (NumBytesRem > 0u) { + memcpy(pBuffer, pRing->pBuffer + RdOff, NumBytesRem); + NumBytesRead += NumBytesRem; + pBuffer += NumBytesRem; + BufferSize -= NumBytesRem; + RdOff += NumBytesRem; + } + if (NumBytesRead) { + pRing->RdOff = RdOff; + } + // + return NumBytesRead; +} + +/********************************************************************* +* +* SEGGER_RTT_Read +* +* Function description +* Reads characters from SEGGER real-time-terminal control block +* which have been previously stored by the host. +* +* Parameters +* BufferIndex Index of Down-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to buffer provided by target application, to copy characters from RTT-down-buffer to. +* BufferSize Size of the target application buffer. +* +* Return value +* Number of bytes that have been read. +*/ +unsigned SEGGER_RTT_Read(unsigned BufferIndex, void* pBuffer, unsigned BufferSize) { + unsigned NumBytesRead; + volatile unsigned SavedState; + // + SEGGER_RTT_LOCK(SavedState); + // + // Call the non-locking read function + // + NumBytesRead = SEGGER_RTT_ReadNoLock(BufferIndex, pBuffer, BufferSize); + // + // Finish up. + // + SEGGER_RTT_UNLOCK(SavedState); + // + return NumBytesRead; +} + +/********************************************************************* +* +* SEGGER_RTT_WriteSkipNoLock +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block which is then read by the host. +* SEGGER_RTT_WriteSkipNoLock does not lock the application and +* skips all data, if the data does not fit into the buffer. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, all data is dropped. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +*/ +unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + const char* pData; + SEGGER_RTT_BUFFER_UP* pRing; + unsigned Avail; + unsigned RdOff; + unsigned WrOff; + unsigned Rem; + + pData = (const char *)pBuffer; + // + // Get "to-host" ring buffer and copy some elements into local variables. + // + pRing = &_SEGGER_RTT.aUp[BufferIndex]; + RdOff = pRing->RdOff; + WrOff = pRing->WrOff; + // + // Handle the most common cases fastest. + // Which is: + // RdOff <= WrOff -> Space until wrap around is free. + // AND + // WrOff + NumBytes < SizeOfBuffer -> No Wrap around necessary. + // + // OR + // + // RdOff > WrOff -> Space until RdOff - 1 is free. + // AND + // WrOff + NumBytes < RdOff -> Data fits into buffer + // + if (RdOff <= WrOff) { + // + // Get space until WrOff will be at wrap around. + // + Avail = pRing->SizeOfBuffer - 1u - WrOff ; + if (Avail >= NumBytes) { +#if 1 // memcpy() is good for large amounts of data, but the overhead is too big for small amounts. Use a simple byte loop instead. + char* pDst; + pDst = pRing->pBuffer + WrOff; + WrOff += NumBytes; + do { + *pDst++ = *pData++; + } while (--NumBytes); + pRing->WrOff = WrOff + NumBytes; +#else + memcpy(pRing->pBuffer + WrOff, pData, NumBytes); + pRing->WrOff = WrOff + NumBytes; +#endif + return 1; + } + // + // If data did not fit into space until wrap around calculate complete space in buffer. + // + Avail += RdOff; + // + // If there is still no space for the whole of this output, don't bother. + // + if (Avail >= NumBytes) { + // + // OK, we have enough space in buffer. Copy in one or 2 chunks + // + Rem = pRing->SizeOfBuffer - WrOff; // Space until end of buffer + if (Rem > NumBytes) { + memcpy(pRing->pBuffer + WrOff, pData, NumBytes); + pRing->WrOff = WrOff + NumBytes; + } else { + // + // We reach the end of the buffer, so need to wrap around + // + memcpy(pRing->pBuffer + WrOff, pData, Rem); + memcpy(pRing->pBuffer, pData + Rem, NumBytes - Rem); + pRing->WrOff = NumBytes - Rem; + } + return 1; + } + } else { + Avail = RdOff - WrOff - 1u; + if (Avail >= NumBytes) { + memcpy(pRing->pBuffer + WrOff, pData, NumBytes); + pRing->WrOff = WrOff + NumBytes; + return 1; + } + } + // + // If we reach this point no data has been written + // + return 0; +} + +/********************************************************************* +* +* SEGGER_RTT_WriteNoLock +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block which is then read by the host. +* SEGGER_RTT_WriteNoLock does not lock the application. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, remaining characters of pBuffer are dropped. +* (2) For performance reasons this function does not call Init() +* and may only be called after RTT has been initialized. +* Either by calling SEGGER_RTT_Init() or calling another RTT API function first. +*/ +unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + unsigned Status; + unsigned Avail; + const char* pData; + SEGGER_RTT_BUFFER_UP* pRing; + + pData = (const char *)pBuffer; + // + // Get "to-host" ring buffer. + // + pRing = &_SEGGER_RTT.aUp[BufferIndex]; + // + // How we output depends upon the mode... + // + switch (pRing->Flags) { + case SEGGER_RTT_MODE_NO_BLOCK_SKIP: + // + // If we are in skip mode and there is no space for the whole + // of this output, don't bother. + // + Avail = _GetAvailWriteSpace(pRing); + if (Avail < NumBytes) { + Status = 0u; + } else { + Status = NumBytes; + _WriteNoCheck(pRing, pData, NumBytes); + } + break; + case SEGGER_RTT_MODE_NO_BLOCK_TRIM: + // + // If we are in trim mode, trim to what we can output without blocking. + // + Avail = _GetAvailWriteSpace(pRing); + Status = Avail < NumBytes ? Avail : NumBytes; + _WriteNoCheck(pRing, pData, Status); + break; + case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: + // + // If we are in blocking mode, output everything. + // + Status = _WriteBlocking(pRing, pData, NumBytes); + break; + default: + Status = 0u; + break; + } + // + // Finish up. + // + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_Write +* +* Function description +* Stores a specified number of characters in SEGGER RTT +* control block which is then read by the host. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* pBuffer Pointer to character array. Does not need to point to a \0 terminated string. +* NumBytes Number of bytes to be stored in the SEGGER RTT control block. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, remaining characters of pBuffer are dropped. +*/ +unsigned SEGGER_RTT_Write(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes) { + unsigned Status; + volatile unsigned SavedState; + // + INIT(); + SEGGER_RTT_LOCK(SavedState); + // + // Call the non-locking write function + // + Status = SEGGER_RTT_WriteNoLock(BufferIndex, pBuffer, NumBytes); + // + // Finish up. + // + SEGGER_RTT_UNLOCK(SavedState); + // + return Status; +} + +/********************************************************************* +* +* SEGGER_RTT_WriteString +* +* Function description +* Stores string in SEGGER RTT control block. +* This data is read by the host. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used (e.g. 0 for "Terminal"). +* s Pointer to string. +* +* Return value +* Number of bytes which have been stored in the "Up"-buffer. +* +* Notes +* (1) If there is not enough space in the "Up"-buffer, depending on configuration, +* remaining characters may be dropped or RTT module waits until there is more space in the buffer. +* (2) String passed to this function has to be \0 terminated +* (3) \0 termination character is *not* stored in RTT buffer +*/ +unsigned SEGGER_RTT_WriteString(unsigned BufferIndex, const char* s) { + unsigned Len; + + Len = STRLEN(s); + return SEGGER_RTT_Write(BufferIndex, s, Len); +} + +/********************************************************************* +* +* SEGGER_RTT_GetKey +* +* Function description +* Reads one character from the SEGGER RTT buffer. +* Host has previously stored data there. +* +* Return value +* < 0 - No character available (buffer empty). +* >= 0 - Character which has been read. (Possible values: 0 - 255) +* +* Notes +* (1) This function is only specified for accesses to RTT buffer 0. +*/ +int SEGGER_RTT_GetKey(void) { + char c; + int r; + + r = (int)SEGGER_RTT_Read(0u, &c, 1u); + if (r == 1) { + r = (int)(unsigned char)c; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_WaitKey +* +* Function description +* Waits until at least one character is avaible in the SEGGER RTT buffer. +* Once a character is available, it is read and this function returns. +* +* Return value +* >=0 - Character which has been read. +* +* Notes +* (1) This function is only specified for accesses to RTT buffer 0 +* (2) This function is blocking if no character is present in RTT buffer +*/ +int SEGGER_RTT_WaitKey(void) { + int r; + + do { + r = SEGGER_RTT_GetKey(); + } while (r < 0); + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_HasKey +* +* Function description +* Checks if at least one character for reading is available in the SEGGER RTT buffer. +* +* Return value +* == 0 - No characters are available to read. +* == 1 - At least one character is available. +* +* Notes +* (1) This function is only specified for accesses to RTT buffer 0 +*/ +int SEGGER_RTT_HasKey(void) { + unsigned RdOff; + int r; + + INIT(); + RdOff = _SEGGER_RTT.aDown[0].RdOff; + if (RdOff != _SEGGER_RTT.aDown[0].WrOff) { + r = 1; + } else { + r = 0; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_HasData +* +* Function description +* Check if there is data from the host in the given buffer. +* +* Return value: +* ==0: No data +* !=0: Data in buffer +* +*/ +unsigned SEGGER_RTT_HasData(unsigned BufferIndex) { + SEGGER_RTT_BUFFER_DOWN* pRing; + unsigned v; + + pRing = &_SEGGER_RTT.aDown[BufferIndex]; + v = pRing->WrOff; + return v - pRing->RdOff; +} + +/********************************************************************* +* +* SEGGER_RTT_AllocDownBuffer +* +* Function description +* Run-time configuration of the next down-buffer (H->T). +* The next buffer, which is not used yet is configured. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* +* Return value +* >= 0 - O.K. Buffer Index +* < 0 - Error +*/ +int SEGGER_RTT_AllocDownBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int BufferIndex; + volatile unsigned SavedState; + + INIT(); + SEGGER_RTT_LOCK(SavedState); + BufferIndex = 0; + do { + if (_SEGGER_RTT.aDown[BufferIndex].pBuffer == NULL) { + break; + } + BufferIndex++; + } while (BufferIndex < _SEGGER_RTT.MaxNumDownBuffers); + if (BufferIndex < _SEGGER_RTT.MaxNumDownBuffers) { + _SEGGER_RTT.aDown[BufferIndex].sName = sName; + _SEGGER_RTT.aDown[BufferIndex].pBuffer = pBuffer; + _SEGGER_RTT.aDown[BufferIndex].SizeOfBuffer = BufferSize; + _SEGGER_RTT.aDown[BufferIndex].RdOff = 0u; + _SEGGER_RTT.aDown[BufferIndex].WrOff = 0u; + _SEGGER_RTT.aDown[BufferIndex].Flags = Flags; + } else { + BufferIndex = -1; + } + SEGGER_RTT_UNLOCK(SavedState); + return BufferIndex; +} + +/********************************************************************* +* +* SEGGER_RTT_AllocUpBuffer +* +* Function description +* Run-time configuration of the next up-buffer (T->H). +* The next buffer, which is not used yet is configured. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* +* Return value +* >= 0 - O.K. Buffer Index +* < 0 - Error +*/ +int SEGGER_RTT_AllocUpBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int BufferIndex; + volatile unsigned SavedState; + + INIT(); + SEGGER_RTT_LOCK(SavedState); + BufferIndex = 0; + do { + if (_SEGGER_RTT.aUp[BufferIndex].pBuffer == NULL) { + break; + } + BufferIndex++; + } while (BufferIndex < _SEGGER_RTT.MaxNumUpBuffers); + if (BufferIndex < _SEGGER_RTT.MaxNumUpBuffers) { + _SEGGER_RTT.aUp[BufferIndex].sName = sName; + _SEGGER_RTT.aUp[BufferIndex].pBuffer = pBuffer; + _SEGGER_RTT.aUp[BufferIndex].SizeOfBuffer = BufferSize; + _SEGGER_RTT.aUp[BufferIndex].RdOff = 0u; + _SEGGER_RTT.aUp[BufferIndex].WrOff = 0u; + _SEGGER_RTT.aUp[BufferIndex].Flags = Flags; + } else { + BufferIndex = -1; + } + SEGGER_RTT_UNLOCK(SavedState); + return BufferIndex; +} + +/********************************************************************* +* +* SEGGER_RTT_ConfigUpBuffer +* +* Function description +* Run-time configuration of a specific up-buffer (T->H). +* Buffer to be configured is specified by index. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* BufferIndex Index of the buffer to configure. +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* +* Return value +* >= 0 - O.K. +* < 0 - Error +*/ +int SEGGER_RTT_ConfigUpBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int r; + volatile unsigned SavedState; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumUpBuffers) { + SEGGER_RTT_LOCK(SavedState); + if (BufferIndex > 0u) { + _SEGGER_RTT.aUp[BufferIndex].sName = sName; + _SEGGER_RTT.aUp[BufferIndex].pBuffer = pBuffer; + _SEGGER_RTT.aUp[BufferIndex].SizeOfBuffer = BufferSize; + _SEGGER_RTT.aUp[BufferIndex].RdOff = 0u; + _SEGGER_RTT.aUp[BufferIndex].WrOff = 0u; + } + _SEGGER_RTT.aUp[BufferIndex].Flags = Flags; + SEGGER_RTT_UNLOCK(SavedState); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_ConfigDownBuffer +* +* Function description +* Run-time configuration of a specific down-buffer (H->T). +* Buffer to be configured is specified by index. +* This includes: Buffer address, size, name, flags, ... +* +* Parameters +* BufferIndex Index of the buffer to configure. +* sName Pointer to a constant name string. +* pBuffer Pointer to a buffer to be used. +* BufferSize Size of the buffer. +* Flags Operating modes. Define behavior if buffer is full (not enough space for entire message). +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_ConfigDownBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags) { + int r; + volatile unsigned SavedState; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumDownBuffers) { + SEGGER_RTT_LOCK(SavedState); + if (BufferIndex > 0u) { + _SEGGER_RTT.aDown[BufferIndex].sName = sName; + _SEGGER_RTT.aDown[BufferIndex].pBuffer = pBuffer; + _SEGGER_RTT.aDown[BufferIndex].SizeOfBuffer = BufferSize; + _SEGGER_RTT.aDown[BufferIndex].RdOff = 0u; + _SEGGER_RTT.aDown[BufferIndex].WrOff = 0u; + } + _SEGGER_RTT.aDown[BufferIndex].Flags = Flags; + SEGGER_RTT_UNLOCK(SavedState); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetNameUpBuffer +* +* Function description +* Run-time configuration of a specific up-buffer name (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer to renamed. +* sName Pointer to a constant name string. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetNameUpBuffer(unsigned BufferIndex, const char* sName) { + int r; + volatile unsigned SavedState; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumUpBuffers) { + SEGGER_RTT_LOCK(SavedState); + _SEGGER_RTT.aUp[BufferIndex].sName = sName; + SEGGER_RTT_UNLOCK(SavedState); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_SetNameDownBuffer +* +* Function description +* Run-time configuration of a specific Down-buffer name (T->H). +* Buffer to be configured is specified by index. +* +* Parameters +* BufferIndex Index of the buffer to renamed. +* sName Pointer to a constant name string. +* +* Return value +* >= 0 O.K. +* < 0 Error +*/ +int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName) { + int r; + volatile unsigned SavedState; + + INIT(); + if (BufferIndex < (unsigned)_SEGGER_RTT.MaxNumDownBuffers) { + SEGGER_RTT_LOCK(SavedState); + _SEGGER_RTT.aDown[BufferIndex].sName = sName; + SEGGER_RTT_UNLOCK(SavedState); + r = 0; + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_Init +* +* Function description +* Initializes the RTT Control Block. +* Should be used in RAM targets, at start of the application. +* +*/ +void SEGGER_RTT_Init (void) { + INIT(); +} + +/********************************************************************* +* +* SEGGER_RTT_SetTerminal +* +* Function description +* Sets the terminal to be used for output on channel 0. +* +* Parameters +* TerminalId Index of the terminal. +* +* Return value +* >= 0 O.K. +* < 0 Error (e.g. if RTT is configured for non-blocking mode and there was no space in the buffer to set the new terminal Id) +*/ +int SEGGER_RTT_SetTerminal (char TerminalId) { + char ac[2]; + SEGGER_RTT_BUFFER_UP* pRing; + volatile unsigned SavedState; + unsigned Avail; + int r; + // + INIT(); + // + r = 0; + ac[0] = 0xFFU; + if ((unsigned char)TerminalId < (unsigned char)sizeof(_aTerminalId)) { // We only support a certain number of channels + ac[1] = _aTerminalId[(unsigned char)TerminalId]; + pRing = &_SEGGER_RTT.aUp[0]; // Buffer 0 is always reserved for terminal I/O, so we can use index 0 here, fixed + SEGGER_RTT_LOCK(SavedState); // Lock to make sure that no other task is writing into buffer, while we are and number of free bytes in buffer does not change downwards after checking and before writing + if ((pRing->Flags & SEGGER_RTT_MODE_MASK) == SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) { + _ActiveTerminal = TerminalId; + _WriteBlocking(pRing, ac, 2u); + } else { // Skipping mode or trim mode? => We cannot trim this command so handling is the same for both modes + Avail = _GetAvailWriteSpace(pRing); + if (Avail >= 2) { + _ActiveTerminal = TerminalId; // Only change active terminal in case of success + _WriteNoCheck(pRing, ac, 2u); + } else { + r = -1; + } + } + SEGGER_RTT_UNLOCK(SavedState); + } else { + r = -1; + } + return r; +} + +/********************************************************************* +* +* SEGGER_RTT_TerminalOut +* +* Function description +* Writes a string to the given terminal +* without changing the terminal for channel 0. +* +* Parameters +* TerminalId Index of the terminal. +* s String to be printed on the terminal. +* +* Return value +* >= 0 - Number of bytes written. +* < 0 - Error. +* +*/ +int SEGGER_RTT_TerminalOut (char TerminalId, const char* s) { + int Status; + unsigned FragLen; + unsigned Avail; + SEGGER_RTT_BUFFER_UP* pRing; + volatile unsigned SavedState; + // + INIT(); + // + // Validate terminal ID. + // + if (TerminalId < (char)sizeof(_aTerminalId)) { // We only support a certain number of channels + // + // Get "to-host" ring buffer. + // + pRing = &_SEGGER_RTT.aUp[0]; + // + // Need to be able to change terminal, write data, change back. + // Compute the fixed and variable sizes. + // + FragLen = strlen(s); + // + // How we output depends upon the mode... + // + SEGGER_RTT_LOCK(SavedState); + Avail = _GetAvailWriteSpace(pRing); + switch (pRing->Flags & SEGGER_RTT_MODE_MASK) { + case SEGGER_RTT_MODE_NO_BLOCK_SKIP: + // + // If we are in skip mode and there is no space for the whole + // of this output, don't bother switching terminals at all. + // + if (Avail < (FragLen + 4u)) { + Status = 0; + } else { + _PostTerminalSwitch(pRing, TerminalId); + Status = (int)_WriteBlocking(pRing, s, FragLen); + _PostTerminalSwitch(pRing, _ActiveTerminal); + } + break; + case SEGGER_RTT_MODE_NO_BLOCK_TRIM: + // + // If we are in trim mode and there is not enough space for everything, + // trim the output but always include the terminal switch. If no room + // for terminal switch, skip that totally. + // + if (Avail < 4u) { + Status = -1; + } else { + _PostTerminalSwitch(pRing, TerminalId); + Status = (int)_WriteBlocking(pRing, s, (FragLen < (Avail - 4u)) ? FragLen : (Avail - 4u)); + _PostTerminalSwitch(pRing, _ActiveTerminal); + } + break; + case SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL: + // + // If we are in blocking mode, output everything. + // + _PostTerminalSwitch(pRing, TerminalId); + Status = (int)_WriteBlocking(pRing, s, FragLen); + _PostTerminalSwitch(pRing, _ActiveTerminal); + break; + default: + Status = -1; + break; + } + // + // Finish up. + // + SEGGER_RTT_UNLOCK(SavedState); + } else { + Status = -1; + } + return Status; +} + + +/*************************** End of file ****************************/ diff --git a/SWM221_Lib/CAN/SimplCAN_RX_Int/RTT/SEGGER_RTT.h b/SWM221_Lib/CAN/SimplCAN_RX_Int/RTT/SEGGER_RTT.h new file mode 100644 index 0000000..1412da1 --- /dev/null +++ b/SWM221_Lib/CAN/SimplCAN_RX_Int/RTT/SEGGER_RTT.h @@ -0,0 +1,227 @@ +/********************************************************************* +* SEGGER MICROCONTROLLER GmbH & Co. KG * +* Solutions for real time microcontroller applications * +********************************************************************** +* * +* (c) 2014 - 2015 SEGGER Microcontroller GmbH & Co. KG * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* * This software may in its unmodified form be freely redistributed * +* in source form. * +* * The source code may be modified, provided the source code * +* retains the above copyright notice, this list of conditions and * +* the following disclaimer. * +* * Modified versions of this software in source or linkable form * +* may not be distributed without prior consent of SEGGER. * +* * This software may only be used for communication with SEGGER * +* J-Link debug probes. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* RTT version: 5.02k * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT.h +Purpose : Implementation of SEGGER real-time transfer which allows + real-time communication on targets which support debugger + memory accesses while the CPU is running. +---------------------------------------------------------------------- +*/ + +#ifndef SEGGER_RTT_H +#define SEGGER_RTT_H + +#include "SEGGER_RTT_Conf.h" + +/********************************************************************* +* +* Defines, fixed +* +********************************************************************** +*/ + +/********************************************************************* +* +* Types +* +********************************************************************** +*/ + +// +// Description for a circular buffer (also called "ring buffer") +// which is used as up-buffer (T->H) +// +typedef struct { + const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" + char* pBuffer; // Pointer to start of buffer + unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. + unsigned WrOff; // Position of next item to be written by either target. + volatile unsigned RdOff; // Position of next item to be read by host. Must be volatile since it may be modified by host. + unsigned Flags; // Contains configuration flags +} SEGGER_RTT_BUFFER_UP; + +// +// Description for a circular buffer (also called "ring buffer") +// which is used as down-buffer (H->T) +// +typedef struct { + const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" + char* pBuffer; // Pointer to start of buffer + unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. + volatile unsigned WrOff; // Position of next item to be written by host. Must be volatile since it may be modified by host. + unsigned RdOff; // Position of next item to be read by target (down-buffer). + unsigned Flags; // Contains configuration flags +} SEGGER_RTT_BUFFER_DOWN; + +// +// RTT control block which describes the number of buffers available +// as well as the configuration for each buffer +// +// +typedef struct { + char acID[16]; // Initialized to "SEGGER RTT" + int MaxNumUpBuffers; // Initialized to SEGGER_RTT_MAX_NUM_UP_BUFFERS (type. 2) + int MaxNumDownBuffers; // Initialized to SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (type. 2) + SEGGER_RTT_BUFFER_UP aUp[SEGGER_RTT_MAX_NUM_UP_BUFFERS]; // Up buffers, transferring information up from target via debug probe to host + SEGGER_RTT_BUFFER_DOWN aDown[SEGGER_RTT_MAX_NUM_DOWN_BUFFERS]; // Down buffers, transferring information down from host via debug probe to target +} SEGGER_RTT_CB; + +/********************************************************************* +* +* Global data +* +********************************************************************** +*/ +extern SEGGER_RTT_CB _SEGGER_RTT; + +/********************************************************************* +* +* RTT API functions +* +********************************************************************** +*/ +int SEGGER_RTT_AllocDownBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_AllocUpBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_ConfigUpBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_ConfigDownBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_GetKey (void); +unsigned SEGGER_RTT_HasData (unsigned BufferIndex); +int SEGGER_RTT_HasKey (void); +void SEGGER_RTT_Init (void); +unsigned SEGGER_RTT_Read (unsigned BufferIndex, void* pBuffer, unsigned BufferSize); +unsigned SEGGER_RTT_ReadNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize); +int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName); +int SEGGER_RTT_SetNameUpBuffer (unsigned BufferIndex, const char* sName); +int SEGGER_RTT_WaitKey (void); +unsigned SEGGER_RTT_Write (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteString (unsigned BufferIndex, const char* s); +// +// Function macro for performance optimization +// +#define SEGGER_RTT_HASDATA(n) (_SEGGER_RTT.aDown[n].WrOff - _SEGGER_RTT.aDown[n].RdOff) + +/********************************************************************* +* +* RTT "Terminal" API functions +* +********************************************************************** +*/ +int SEGGER_RTT_SetTerminal (char TerminalId); +int SEGGER_RTT_TerminalOut (char TerminalId, const char* s); + +/********************************************************************* +* +* RTT printf functions (require SEGGER_RTT_printf.c) +* +********************************************************************** +*/ +int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...); + +/********************************************************************* +* +* Defines +* +********************************************************************** +*/ + +// +// Operating modes. Define behavior if buffer is full (not enough space for entire message) +// +#define SEGGER_RTT_MODE_NO_BLOCK_SKIP (0U) // Skip. Do not block, output nothing. (Default) +#define SEGGER_RTT_MODE_NO_BLOCK_TRIM (1U) // Trim: Do not block, output as much as fits. +#define SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL (2U) // Block: Wait until there is space in the buffer. +#define SEGGER_RTT_MODE_MASK (3U) + +// +// Control sequences, based on ANSI. +// Can be used to control color, and clear the screen +// +#define RTT_CTRL_RESET "\e[0m" // Reset to default colors +#define RTT_CTRL_CLEAR "\e[2J" // Clear screen, reposition cursor to top left + +#define RTT_CTRL_TEXT_BLACK "\e[2;30m" +#define RTT_CTRL_TEXT_RED "\e[2;31m" +#define RTT_CTRL_TEXT_GREEN "\e[2;32m" +#define RTT_CTRL_TEXT_YELLOW "\e[2;33m" +#define RTT_CTRL_TEXT_BLUE "\e[2;34m" +#define RTT_CTRL_TEXT_MAGENTA "\e[2;35m" +#define RTT_CTRL_TEXT_CYAN "\e[2;36m" +#define RTT_CTRL_TEXT_WHITE "\e[2;37m" + +#define RTT_CTRL_TEXT_BRIGHT_BLACK "\e[1;30m" +#define RTT_CTRL_TEXT_BRIGHT_RED "\e[1;31m" +#define RTT_CTRL_TEXT_BRIGHT_GREEN "\e[1;32m" +#define RTT_CTRL_TEXT_BRIGHT_YELLOW "\e[1;33m" +#define RTT_CTRL_TEXT_BRIGHT_BLUE "\e[1;34m" +#define RTT_CTRL_TEXT_BRIGHT_MAGENTA "\e[1;35m" +#define RTT_CTRL_TEXT_BRIGHT_CYAN "\e[1;36m" +#define RTT_CTRL_TEXT_BRIGHT_WHITE "\e[1;37m" + +#define RTT_CTRL_BG_BLACK "\e[24;40m" +#define RTT_CTRL_BG_RED "\e[24;41m" +#define RTT_CTRL_BG_GREEN "\e[24;42m" +#define RTT_CTRL_BG_YELLOW "\e[24;43m" +#define RTT_CTRL_BG_BLUE "\e[24;44m" +#define RTT_CTRL_BG_MAGENTA "\e[24;45m" +#define RTT_CTRL_BG_CYAN "\e[24;46m" +#define RTT_CTRL_BG_WHITE "\e[24;47m" + +#define RTT_CTRL_BG_BRIGHT_BLACK "\e[4;40m" +#define RTT_CTRL_BG_BRIGHT_RED "\e[4;41m" +#define RTT_CTRL_BG_BRIGHT_GREEN "\e[4;42m" +#define RTT_CTRL_BG_BRIGHT_YELLOW "\e[4;43m" +#define RTT_CTRL_BG_BRIGHT_BLUE "\e[4;44m" +#define RTT_CTRL_BG_BRIGHT_MAGENTA "\e[4;45m" +#define RTT_CTRL_BG_BRIGHT_CYAN "\e[4;46m" +#define RTT_CTRL_BG_BRIGHT_WHITE "\e[4;47m" + + +#endif + +/*************************** End of file ****************************/ diff --git a/SWM221_Lib/CAN/SimplCAN_RX_Int/RTT/SEGGER_RTT_Conf.h b/SWM221_Lib/CAN/SimplCAN_RX_Int/RTT/SEGGER_RTT_Conf.h new file mode 100644 index 0000000..693e546 --- /dev/null +++ b/SWM221_Lib/CAN/SimplCAN_RX_Int/RTT/SEGGER_RTT_Conf.h @@ -0,0 +1,171 @@ +/********************************************************************* +* SEGGER MICROCONTROLLER GmbH & Co. KG * +* Solutions for real time microcontroller applications * +********************************************************************** +* * +* (c) 2014 - 2015 SEGGER Microcontroller GmbH & Co. KG * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* * This software may in its unmodified form be freely redistributed * +* in source form. * +* * The source code may be modified, provided the source code * +* retains the above copyright notice, this list of conditions and * +* the following disclaimer. * +* * Modified versions of this software in source or linkable form * +* may not be distributed without prior consent of SEGGER. * +* * This software may only be used for communication with SEGGER * +* J-Link debug probes. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* RTT version: 5.02k * +* * +********************************************************************** +---------------------------------------------------------------------- +File : SEGGER_RTT_Conf.h +Purpose : Implementation of SEGGER real-time transfer (RTT) which + allows real-time communication on targets which support + debugger memory accesses while the CPU is running. +---------------------------END-OF-HEADER------------------------------ +*/ + +#ifndef SEGGER_RTT_CONF_H +#define SEGGER_RTT_CONF_H + +#ifdef __ICCARM__ + #include +#endif + +/********************************************************************* +* +* Defines, configurable +* +********************************************************************** +*/ + +#define SEGGER_RTT_MAX_NUM_UP_BUFFERS (2) // Max. number of up-buffers (T->H) available on this target (Default: 2) +#define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (2) // Max. number of down-buffers (H->T) available on this target (Default: 2) + +#define BUFFER_SIZE_UP (128) //1024--->512--->384 256 Size of the buffer for terminal output of target, up to host (Default: 1k) +#define BUFFER_SIZE_DOWN (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) + +#define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) + +#define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0) + +// +// Target is not allowed to perform other RTT operations while string still has not been stored completely. +// Otherwise we would probably end up with a mixed string in the buffer. +// If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here. +// +/********************************************************************* +* +* RTT lock configuration for SEGGER Embedded Studio, +* Rowley CrossStudio and GCC +*/ +#if (defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__) + #ifdef __ARM_ARCH_6M__ + #define SEGGER_RTT_LOCK(SavedState) { \ + asm volatile ("mrs %0, primask \n\t" \ + "mov r1, $1 \n\t" \ + "msr primask, r1 \n\t" \ + : "=r" (SavedState) \ + : \ + : "r1" \ + ); \ + } + + #define SEGGER_RTT_UNLOCK(SavedState) { \ + asm volatile ("msr primask, %0 \n\t" \ + : \ + : "r" (SavedState) \ + : \ + ); \ + } + + #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)) + #define SEGGER_RTT_LOCK(SavedState) { \ + asm volatile ("mrs %0, basepri \n\t" \ + "mov r1, $128 \n\t" \ + "msr basepri, r1 \n\t" \ + : "=r" (SavedState) \ + : \ + : "r1" \ + ); \ + } + #define SEGGER_RTT_UNLOCK(SavedState) { \ + asm volatile ("msr basepri, %0 \n\t" \ + : \ + : "r" (SavedState) \ + : \ + ); \ + } + #else + #define SEGGER_RTT_LOCK(SavedState) (void)(SavedState) + #define SEGGER_RTT_UNLOCK(SavedState) (void)(SavedState) + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration for IAR EWARM +*/ +#ifdef __ICCARM__ + #if (defined (__ARM7M__) && (__CORE__ == __ARM7M__)) + #define SEGGER_RTT_LOCK(SavedState) { \ + SavedState = __get_PRIMASK(); \ + __set_PRIMASK(1); \ + } + + #define SEGGER_RTT_UNLOCK(SavedState) { \ + __set_PRIMASK(SavedState); \ + } + #elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) + #define SEGGER_RTT_LOCK(SavedState) { \ + SavedState = __get_BASEPRI(); \ + __set_BASEPRI(128); \ + } + + #define SEGGER_RTT_UNLOCK(SavedState) { \ + __set_BASEPRI(SavedState); \ + } + #endif +#endif + +/********************************************************************* +* +* RTT lock configuration fallback +*/ +#ifndef SEGGER_RTT_LOCK + #define SEGGER_RTT_LOCK(SavedState) (void)(SavedState) +#endif + +#ifndef SEGGER_RTT_UNLOCK + #define SEGGER_RTT_UNLOCK(SavedState) (void)(SavedState) +#endif + +#endif +/*************************** End of file ****************************/ diff --git a/SWM221_Lib/CAN/SimplCAN_RX_Int/RTT/SEGGER_RTT_printf.c b/SWM221_Lib/CAN/SimplCAN_RX_Int/RTT/SEGGER_RTT_printf.c new file mode 100644 index 0000000..4965ba6 --- /dev/null +++ b/SWM221_Lib/CAN/SimplCAN_RX_Int/RTT/SEGGER_RTT_printf.c @@ -0,0 +1,500 @@ +/********************************************************************* +* SEGGER MICROCONTROLLER GmbH & Co. KG * +* Solutions for real time microcontroller applications * +********************************************************************** +* * +* (c) 2014 - 2015 SEGGER Microcontroller GmbH & Co. KG * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* SEGGER RTT * Real Time Transfer for embedded targets * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* * This software may in its unmodified form be freely redistributed * +* in source form. * +* * The source code may be modified, provided the source code * +* retains the above copyright notice, this list of conditions and * +* the following disclaimer. * +* * Modified versions of this software in source or linkable form * +* may not be distributed without prior consent of SEGGER. * +* * This software may only be used for communication with SEGGER * +* J-Link debug probes. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +* * +* RTT version: 5.02k * +* * +********************************************************************** +---------------------------END-OF-HEADER------------------------------ +File : SEGGER_RTT_printf.c +Purpose : Replacement for printf to write formatted data via RTT +---------------------------------------------------------------------- +*/ +#include "SEGGER_RTT.h" +#include "SEGGER_RTT_Conf.h" + +/********************************************************************* +* +* Defines, configurable +* +********************************************************************** +*/ + +#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE + #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64) +#endif + +#include +#include + + +#define FORMAT_FLAG_LEFT_JUSTIFY (1u << 0) +#define FORMAT_FLAG_PAD_ZERO (1u << 1) +#define FORMAT_FLAG_PRINT_SIGN (1u << 2) +#define FORMAT_FLAG_ALTERNATE (1u << 3) + +/********************************************************************* +* +* Types +* +********************************************************************** +*/ + +typedef struct { + char* pBuffer; + unsigned BufferSize; + unsigned Cnt; + + int ReturnValue; + + unsigned RTTBufferIndex; +} SEGGER_RTT_PRINTF_DESC; + +/********************************************************************* +* +* Function prototypes +* +********************************************************************** +*/ +int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList); + +/********************************************************************* +* +* Static code +* +********************************************************************** +*/ +/********************************************************************* +* +* _StoreChar +*/ +static void _StoreChar(SEGGER_RTT_PRINTF_DESC * p, char c) { + unsigned Cnt; + + Cnt = p->Cnt; + if ((Cnt + 1u) <= p->BufferSize) { + *(p->pBuffer + Cnt) = c; + p->Cnt = Cnt + 1u; + p->ReturnValue++; + } + // + // Write part of string, when the buffer is full + // + if (p->Cnt == p->BufferSize) { + if (SEGGER_RTT_Write(p->RTTBufferIndex, p->pBuffer, p->Cnt) != p->Cnt) { + p->ReturnValue = -1; + } else { + p->Cnt = 0u; + } + } +} + +/********************************************************************* +* +* _PrintUnsigned +*/ +static void _PrintUnsigned(SEGGER_RTT_PRINTF_DESC * pBufferDesc, unsigned v, unsigned Base, unsigned NumDigits, unsigned FieldWidth, unsigned FormatFlags) { + static const char _aV2C[16] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' }; + unsigned Div; + unsigned Digit; + unsigned Number; + unsigned Width; + char c; + + Number = v; + Digit = 1u; + // + // Get actual field width + // + Width = 1u; + while (Number >= Base) { + Number = (Number / Base); + Width++; + } + if (NumDigits > Width) { + Width = NumDigits; + } + // + // Print leading chars if necessary + // + if ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u) { + if (FieldWidth != 0u) { + if (((FormatFlags & FORMAT_FLAG_PAD_ZERO) == FORMAT_FLAG_PAD_ZERO) && (NumDigits == 0u)) { + c = '0'; + } else { + c = ' '; + } + while ((FieldWidth != 0u) && (Width < FieldWidth)) { + FieldWidth--; + _StoreChar(pBufferDesc, c); + if (pBufferDesc->ReturnValue < 0) { + break; + } + } + } + } + if (pBufferDesc->ReturnValue >= 0) { + // + // Compute Digit. + // Loop until Digit has the value of the highest digit required. + // Example: If the output is 345 (Base 10), loop 2 times until Digit is 100. + // + while (1) { + if (NumDigits > 1u) { // User specified a min number of digits to print? => Make sure we loop at least that often, before checking anything else (> 1 check avoids problems with NumDigits being signed / unsigned) + NumDigits--; + } else { + Div = v / Digit; + if (Div < Base) { // Is our divider big enough to extract the highest digit from value? => Done + break; + } + } + Digit *= Base; + } + // + // Output digits + // + do { + Div = v / Digit; + v -= Div * Digit; + _StoreChar(pBufferDesc, _aV2C[Div]); + if (pBufferDesc->ReturnValue < 0) { + break; + } + Digit /= Base; + } while (Digit); + // + // Print trailing spaces if necessary + // + if ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == FORMAT_FLAG_LEFT_JUSTIFY) { + if (FieldWidth != 0u) { + while ((FieldWidth != 0u) && (Width < FieldWidth)) { + FieldWidth--; + _StoreChar(pBufferDesc, ' '); + if (pBufferDesc->ReturnValue < 0) { + break; + } + } + } + } + } +} + +/********************************************************************* +* +* _PrintInt +*/ +static void _PrintInt(SEGGER_RTT_PRINTF_DESC * pBufferDesc, int v, unsigned Base, unsigned NumDigits, unsigned FieldWidth, unsigned FormatFlags) { + unsigned Width; + int Number; + + Number = (v < 0) ? -v : v; + + // + // Get actual field width + // + Width = 1u; + while (Number >= (int)Base) { + Number = (Number / (int)Base); + Width++; + } + if (NumDigits > Width) { + Width = NumDigits; + } + if ((FieldWidth > 0u) && ((v < 0) || ((FormatFlags & FORMAT_FLAG_PRINT_SIGN) == FORMAT_FLAG_PRINT_SIGN))) { + FieldWidth--; + } + + // + // Print leading spaces if necessary + // + if ((((FormatFlags & FORMAT_FLAG_PAD_ZERO) == 0u) || (NumDigits != 0u)) && ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u)) { + if (FieldWidth != 0u) { + while ((FieldWidth != 0u) && (Width < FieldWidth)) { + FieldWidth--; + _StoreChar(pBufferDesc, ' '); + if (pBufferDesc->ReturnValue < 0) { + break; + } + } + } + } + // + // Print sign if necessary + // + if (pBufferDesc->ReturnValue >= 0) { + if (v < 0) { + v = -v; + _StoreChar(pBufferDesc, '-'); + } else if ((FormatFlags & FORMAT_FLAG_PRINT_SIGN) == FORMAT_FLAG_PRINT_SIGN) { + _StoreChar(pBufferDesc, '+'); + } else { + + } + if (pBufferDesc->ReturnValue >= 0) { + // + // Print leading zeros if necessary + // + if (((FormatFlags & FORMAT_FLAG_PAD_ZERO) == FORMAT_FLAG_PAD_ZERO) && ((FormatFlags & FORMAT_FLAG_LEFT_JUSTIFY) == 0u) && (NumDigits == 0u)) { + if (FieldWidth != 0u) { + while ((FieldWidth != 0u) && (Width < FieldWidth)) { + FieldWidth--; + _StoreChar(pBufferDesc, '0'); + if (pBufferDesc->ReturnValue < 0) { + break; + } + } + } + } + if (pBufferDesc->ReturnValue >= 0) { + // + // Print number without sign + // + _PrintUnsigned(pBufferDesc, (unsigned)v, Base, NumDigits, FieldWidth, FormatFlags); + } + } + } +} + +/********************************************************************* +* +* Public code +* +********************************************************************** +*/ +/********************************************************************* +* +* SEGGER_RTT_vprintf +* +* Function description +* Stores a formatted string in SEGGER RTT control block. +* This data is read by the host. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used. (e.g. 0 for "Terminal") +* sFormat Pointer to format string +* pParamList Pointer to the list of arguments for the format string +* +* Return values +* >= 0: Number of bytes which have been stored in the "Up"-buffer. +* < 0: Error +*/ +int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList) { + char c; + SEGGER_RTT_PRINTF_DESC BufferDesc; + int v; + unsigned NumDigits; + unsigned FormatFlags; + unsigned FieldWidth; + char acBuffer[SEGGER_RTT_PRINTF_BUFFER_SIZE]; + + BufferDesc.pBuffer = acBuffer; + BufferDesc.BufferSize = SEGGER_RTT_PRINTF_BUFFER_SIZE; + BufferDesc.Cnt = 0u; + BufferDesc.RTTBufferIndex = BufferIndex; + BufferDesc.ReturnValue = 0; + + do { + c = *sFormat; + sFormat++; + if (c == 0u) { + break; + } + if (c == '%') { + // + // Filter out flags + // + FormatFlags = 0u; + v = 1; + do { + c = *sFormat; + switch (c) { + case '-': FormatFlags |= FORMAT_FLAG_LEFT_JUSTIFY; sFormat++; break; + case '0': FormatFlags |= FORMAT_FLAG_PAD_ZERO; sFormat++; break; + case '+': FormatFlags |= FORMAT_FLAG_PRINT_SIGN; sFormat++; break; + case '#': FormatFlags |= FORMAT_FLAG_ALTERNATE; sFormat++; break; + default: v = 0; break; + } + } while (v); + // + // filter out field with + // + FieldWidth = 0u; + do { + c = *sFormat; + if ((c < '0') || (c > '9')) { + break; + } + sFormat++; + FieldWidth = (FieldWidth * 10u) + ((unsigned)c - '0'); + } while (1); + + // + // Filter out precision (number of digits to display) + // + NumDigits = 0u; + c = *sFormat; + if (c == '.') { + sFormat++; + do { + c = *sFormat; + if ((c < '0') || (c > '9')) { + break; + } + sFormat++; + NumDigits = NumDigits * 10u + ((unsigned)c - '0'); + } while (1); + } + // + // Filter out length modifier + // + c = *sFormat; + do { + if ((c == 'l') || (c == 'h')) { + c = *sFormat; + sFormat++; + } else { + break; + } + } while (1); + // + // Handle specifiers + // + switch (c) { + case 'c': { + char c0; + v = va_arg(*pParamList, int); + c0 = (char)v; + _StoreChar(&BufferDesc, c0); + break; + } + case 'd': + v = va_arg(*pParamList, int); + _PrintInt(&BufferDesc, v, 10u, NumDigits, FieldWidth, FormatFlags); + break; + case 'u': + v = va_arg(*pParamList, int); + _PrintUnsigned(&BufferDesc, (unsigned)v, 10u, NumDigits, FieldWidth, FormatFlags); + break; + case 'x': + case 'X': + v = va_arg(*pParamList, int); + _PrintUnsigned(&BufferDesc, (unsigned)v, 16u, NumDigits, FieldWidth, FormatFlags); + break; + case 's': + { + const char * s = va_arg(*pParamList, const char *); + do { + c = *s; + s++; + if (c == '\0') { + break; + } + _StoreChar(&BufferDesc, c); + } while (BufferDesc.ReturnValue >= 0); + } + break; + case 'p': + v = va_arg(*pParamList, int); + _PrintUnsigned(&BufferDesc, (unsigned)v, 16u, 8u, 8u, 0u); + break; + case '%': + _StoreChar(&BufferDesc, '%'); + break; + default: + break; + } + sFormat++; + } else { + _StoreChar(&BufferDesc, c); + } + } while (BufferDesc.ReturnValue >= 0); + + if (BufferDesc.ReturnValue > 0) { + // + // Write remaining data, if any + // + if (BufferDesc.Cnt != 0u) { + SEGGER_RTT_Write(BufferIndex, acBuffer, BufferDesc.Cnt); + } + BufferDesc.ReturnValue += (int)BufferDesc.Cnt; + } + return BufferDesc.ReturnValue; +} + +/********************************************************************* +* +* SEGGER_RTT_printf +* +* Function description +* Stores a formatted string in SEGGER RTT control block. +* This data is read by the host. +* +* Parameters +* BufferIndex Index of "Up"-buffer to be used. (e.g. 0 for "Terminal") +* sFormat Pointer to format string, followed by the arguments for conversion +* +* Return values +* >= 0: Number of bytes which have been stored in the "Up"-buffer. +* < 0: Error +* +* Notes +* (1) Conversion specifications have following syntax: +* %[flags][FieldWidth][.Precision]ConversionSpecifier +* (2) Supported flags: +* -: Left justify within the field width +* +: Always print sign extension for signed conversions +* 0: Pad with 0 instead of spaces. Ignored when using '-'-flag or precision +* Supported conversion specifiers: +* c: Print the argument as one char +* d: Print the argument as a signed integer +* u: Print the argument as an unsigned integer +* x: Print the argument as an hexadecimal integer +* s: Print the string pointed to by the argument +* p: Print the argument as an 8-digit hexadecimal integer. (Argument shall be a pointer to void.) +*/ +int SEGGER_RTT_printf(unsigned BufferIndex, const char * sFormat, ...) { + va_list ParamList; + + va_start(ParamList, sFormat); + return SEGGER_RTT_vprintf(BufferIndex, sFormat, &ParamList); +} +/*************************** End of file ****************************/ diff --git a/SWM221_Lib/CAN/SimplCAN_RX_Int/SimplCAN_RX_Int.ewp b/SWM221_Lib/CAN/SimplCAN_RX_Int/SimplCAN_RX_Int.ewp new file mode 100644 index 0000000..4d7817b --- /dev/null +++ b/SWM221_Lib/CAN/SimplCAN_RX_Int/SimplCAN_RX_Int.ewp @@ -0,0 +1,1126 @@ + + + 3 + + SWM221 + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 36 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 23 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + APP + + $PROJ_DIR$\APP\main.c + + + + CSL\CMSIS + + $PROJ_DIR$\..\..\SWM221_StdPeriph_Driver\CSL\CMSIS\DeviceSupport\startup\iar\startup_SWM221.s + + + $PROJ_DIR$\..\..\SWM221_StdPeriph_Driver\CSL\CMSIS\DeviceSupport\system_SWM221.c + + + + CSL\StdPD + + $PROJ_DIR$\..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_adc.c + + + $PROJ_DIR$\..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_can.c + + + $PROJ_DIR$\..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_div.c + + + $PROJ_DIR$\..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_dma.c + + + $PROJ_DIR$\..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_exti.c + + + $PROJ_DIR$\..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_flash.c + + + $PROJ_DIR$\..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_gpio.c + + + $PROJ_DIR$\..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_i2c.c + + + $PROJ_DIR$\..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_port.c + + + $PROJ_DIR$\..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_pwm.c + + + $PROJ_DIR$\..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_qei.c + + + $PROJ_DIR$\..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_spi.c + + + $PROJ_DIR$\..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_timr.c + + + $PROJ_DIR$\..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_uart.c + + + $PROJ_DIR$\..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_wdt.c + + + diff --git a/SWM221_Lib/CAN/SimplCAN_RX_Int/SimplCAN_RX_Int.eww b/SWM221_Lib/CAN/SimplCAN_RX_Int/SimplCAN_RX_Int.eww new file mode 100644 index 0000000..ce0674e --- /dev/null +++ b/SWM221_Lib/CAN/SimplCAN_RX_Int/SimplCAN_RX_Int.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\SimplCAN_RX_Int.ewp + + + diff --git a/SWM221_Lib/CAN/SimplCAN_RX_Int/SimplCAN_RX_Int.uvoptx b/SWM221_Lib/CAN/SimplCAN_RX_Int/SimplCAN_RX_Int.uvoptx new file mode 100644 index 0000000..b8b2034 --- /dev/null +++ b/SWM221_Lib/CAN/SimplCAN_RX_Int/SimplCAN_RX_Int.uvoptx @@ -0,0 +1,560 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + SWM221 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\out\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + DLGUARM + ?1w桴~ + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + UL2CM3 + -UV0010M9E -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0SW-M1000S -FS00 -FL04000 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U59400009 -O78 -S4 -ZTIFSpeedSel2000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0SWM221xB.FLM -FS00 -FL020000 -FP0($$Device:SWM221xB$Flash\SWM221xB.FLM) + + + + + + 0 + 1 + ((UART_TypeDef *) (0x40040000 + 0x2000)) + + + 1 + 1 + ((CAN_TypeDef *) (0x40040000 + 0x2800)) + + + 2 + 1 + ((GPIO_TypeDef *) (0x40000000 + 0x04800)) + + + 3 + 1 + TX_CirBuf + + + 4 + 1 + m_buf + + + 5 + 1 + CirBuf + + + 6 + 1 + len + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\UART0 + 35905 + + + + + + + APP + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\app\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + .\APP\jw_can.c + jw_can.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + .\APP\jw_bsp_init.c + jw_bsp_init.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + .\APP\jw_sys_timer.c + jw_sys_timer.c + 0 + 0 + + + + + CSL\StdPD + 0 + 0 + 0 + 0 + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_adc.c + SWM221_adc.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_exti.c + SWM221_exti.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_gpio.c + SWM221_gpio.c + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_i2c.c + SWM221_i2c.c + 0 + 0 + + + 2 + 9 + 1 + 0 + 0 + 0 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_pwm.c + SWM221_pwm.c + 0 + 0 + + + 2 + 10 + 1 + 0 + 0 + 0 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_timr.c + SWM221_timr.c + 0 + 0 + + + 2 + 11 + 1 + 0 + 0 + 0 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_uart.c + SWM221_uart.c + 0 + 0 + + + 2 + 12 + 1 + 0 + 0 + 0 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_wdt.c + SWM221_wdt.c + 0 + 0 + + + 2 + 13 + 1 + 0 + 0 + 0 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_port.c + SWM221_port.c + 0 + 0 + + + 2 + 14 + 1 + 0 + 0 + 0 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_can.c + SWM221_can.c + 0 + 0 + + + 2 + 15 + 1 + 0 + 0 + 0 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_div.c + SWM221_div.c + 0 + 0 + + + 2 + 16 + 1 + 0 + 0 + 0 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_dma.c + SWM221_dma.c + 0 + 0 + + + 2 + 17 + 1 + 0 + 0 + 0 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_qei.c + SWM221_qei.c + 0 + 0 + + + 2 + 18 + 1 + 0 + 0 + 0 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_spi.c + SWM221_spi.c + 0 + 0 + + + 2 + 19 + 1 + 0 + 0 + 0 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_flash.c + SWM221_flash.c + 0 + 0 + + + + + CSL\CMSIS + 0 + 0 + 0 + 0 + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\SWM221_StdPeriph_Driver\CSL\CMSIS\DeviceSupport\system_SWM221.c + system_SWM221.c + 0 + 0 + + + 3 + 21 + 2 + 0 + 0 + 0 + ..\..\SWM221_StdPeriph_Driver\CSL\CMSIS\DeviceSupport\startup\arm\startup_SWM221.s + startup_SWM221.s + 0 + 0 + + + + + RTT + 0 + 0 + 0 + 0 + + 4 + 22 + 1 + 0 + 0 + 0 + .\RTT\JW_RTT.c + JW_RTT.c + 0 + 0 + + + 4 + 23 + 1 + 0 + 0 + 0 + .\RTT\SEGGER_RTT.c + SEGGER_RTT.c + 0 + 0 + + + 4 + 24 + 1 + 0 + 0 + 0 + .\RTT\SEGGER_RTT_printf.c + SEGGER_RTT_printf.c + 0 + 0 + + + + diff --git a/SWM221_Lib/CAN/SimplCAN_RX_Int/SimplCAN_RX_Int.uvprojx b/SWM221_Lib/CAN/SimplCAN_RX_Int/SimplCAN_RX_Int.uvprojx new file mode 100644 index 0000000..4dee5d2 --- /dev/null +++ b/SWM221_Lib/CAN/SimplCAN_RX_Int/SimplCAN_RX_Int.uvprojx @@ -0,0 +1,542 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + SWM221 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + SWM221xB + Synwit + Synwit.SWM32_DFP.2.1.4 + http://www.synwit.com/pack + CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE + + + + 4803 + + + + + + + + + + + $$Device:SWM221x8$SVD\SWM221.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\out\ + SimplCAN_RX_Int + 1 + 0 + 1 + 1 + 1 + .\out\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 1 + fromelf --bin -o "$L@L.bin" "#L" + fromelf --text -a -c -o "$L@L.asm" "#L" + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4099 + + 1 + Segger\JL2CM3.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 3 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + CHIP_SWM221 + + ..\..\SWM221_StdPeriph_Driver\CSL\CMSIS\CoreSupport;..\..\SWM221_StdPeriph_Driver\CSL\CMSIS\DeviceSupport;..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver;.\APP;.\RTT + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + CHIP_SWM221 + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x00000000 + + + + + + + + + + + + + APP + + + main.c + 1 + .\app\main.c + + + jw_can.c + 1 + .\APP\jw_can.c + + + jw_bsp_init.c + 1 + .\APP\jw_bsp_init.c + + + jw_sys_timer.c + 1 + .\APP\jw_sys_timer.c + + + + + CSL\StdPD + + + SWM221_adc.c + 1 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_adc.c + + + SWM221_exti.c + 1 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_exti.c + + + SWM221_gpio.c + 1 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_gpio.c + + + SWM221_i2c.c + 1 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_i2c.c + + + SWM221_pwm.c + 1 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_pwm.c + + + SWM221_timr.c + 1 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_timr.c + + + SWM221_uart.c + 1 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_uart.c + + + SWM221_wdt.c + 1 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_wdt.c + + + SWM221_port.c + 1 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_port.c + + + SWM221_can.c + 1 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_can.c + + + SWM221_div.c + 1 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_div.c + + + SWM221_dma.c + 1 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_dma.c + + + SWM221_qei.c + 1 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_qei.c + + + SWM221_spi.c + 1 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_spi.c + + + SWM221_flash.c + 1 + ..\..\SWM221_StdPeriph_Driver\CSL\SWM221_StdPeriph_Driver\SWM221_flash.c + + + + + CSL\CMSIS + + + system_SWM221.c + 1 + ..\..\SWM221_StdPeriph_Driver\CSL\CMSIS\DeviceSupport\system_SWM221.c + + + startup_SWM221.s + 2 + ..\..\SWM221_StdPeriph_Driver\CSL\CMSIS\DeviceSupport\startup\arm\startup_SWM221.s + + + + + RTT + + + JW_RTT.c + 1 + .\RTT\JW_RTT.c + + + SEGGER_RTT.c + 1 + .\RTT\SEGGER_RTT.c + + + SEGGER_RTT_printf.c + 1 + .\RTT\SEGGER_RTT_printf.c + + + + + + + + + + + + + + + + + SimplCAN_RX_Int + 1 + + + + + diff --git a/SWM221_Lib/CAN/SimplCAN_RX_Int/功能说明.txt b/SWM221_Lib/CAN/SimplCAN_RX_Int/功能说明.txt new file mode 100644 index 0000000..8990e03 --- /dev/null +++ b/SWM221_Lib/CAN/SimplCAN_RX_Int/功能说明.txt @@ -0,0 +1 @@ +˵CAṆʹж \ No newline at end of file diff --git a/SWM221_Lib/LICENSE b/SWM221_Lib/LICENSE new file mode 100644 index 0000000..261eeb9 --- /dev/null +++ b/SWM221_Lib/LICENSE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. Definitions. + + "License" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + "Licensor" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + "Legal Entity" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. For the purposes of this definition, + "control" means (i) the power, direct or indirect, to cause the + direction or management of such entity, whether by contract or + otherwise, or (ii) ownership of fifty percent (50%) or more of the + outstanding shares, or (iii) beneficial ownership of such entity. + + "You" (or "Your") shall mean an individual or Legal Entity + exercising permissions granted by this License. + + "Source" form shall mean the preferred form for making modifications, + including but not limited to software source code, documentation + source, and configuration files. + + "Object" form shall mean any form resulting from mechanical + transformation or translation of a Source form, including but + not limited to compiled object code, generated documentation, + and conversions to other media types. + + "Work" shall mean the work of authorship, whether in Source or + Object form, made available under the License, as indicated by a + copyright notice that is included in or attached to the work + (an example is provided in the Appendix below). + + "Derivative Works" shall mean any work, whether in Source or Object + form, that is based on (or derived from) the Work and for which the + editorial revisions, annotations, elaborations, or other modifications + represent, as a whole, an original work of authorship. For the purposes + of this License, Derivative Works shall not include works that remain + separable from, or merely link (or bind by name) to the interfaces of, + the Work and Derivative Works thereof. + + "Contribution" shall mean any work of authorship, including + the original version of the Work and any modifications or additions + to that Work or Derivative Works thereof, that is intentionally + submitted to Licensor for inclusion in the Work by the copyright owner + or by an individual or Legal Entity authorized to submit on behalf of + the copyright owner. For the purposes of this definition, "submitted" + means any form of electronic, verbal, or written communication sent + to the Licensor or its representatives, including but not limited to + communication on electronic mailing lists, source code control systems, + and issue tracking systems that are managed by, or on behalf of, the + Licensor for the purpose of discussing and improving the Work, but + excluding communication that is conspicuously marked or otherwise + designated in writing by the copyright owner as "Not a Contribution." + + "Contributor" shall mean Licensor and any individual or Legal Entity + on behalf of whom a Contribution has been received by Licensor and + subsequently incorporated within the Work. + + 2. Grant of Copyright License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + copyright license to reproduce, prepare Derivative Works of, + publicly display, publicly perform, sublicense, and distribute the + Work and such Derivative Works in Source or Object form. + + 3. Grant of Patent License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + (except as stated in this section) patent license to make, have made, + use, offer to sell, sell, import, and otherwise transfer the Work, + where such license applies only to those patent claims licensable + by such Contributor that are necessarily infringed by their + Contribution(s) alone or by combination of their Contribution(s) + with the Work to which such Contribution(s) was submitted. If You + institute patent litigation against any entity (including a + cross-claim or counterclaim in a lawsuit) alleging that the Work + or a Contribution incorporated within the Work constitutes direct + or contributory patent infringement, then any patent licenses + granted to You under this License for that Work shall terminate + as of the date such litigation is filed. + + 4. Redistribution. You may reproduce and distribute copies of the + Work or Derivative Works thereof in any medium, with or without + modifications, and in Source or Object form, provided that You + meet the following conditions: + + (a) You must give any other recipients of the Work or + Derivative Works a copy of this License; and + + (b) You must cause any modified files to carry prominent notices + stating that You changed the files; and + + (c) You must retain, in the Source form of any Derivative Works + that You distribute, all copyright, patent, trademark, and + attribution notices from the Source form of the Work, + excluding those notices that do not pertain to any part of + the Derivative Works; and + + (d) If the Work includes a "NOTICE" text file as part of its + distribution, then any Derivative Works that You distribute must + include a readable copy of the attribution notices contained + within such NOTICE file, excluding those notices that do not + pertain to any part of the Derivative Works, in at least one + of the following places: within a NOTICE text file distributed + as part of the Derivative Works; within the Source form or + documentation, if provided along with the Derivative Works; or, + within a display generated by the Derivative Works, if and + wherever such third-party notices normally appear. The contents + of the NOTICE file are for informational purposes only and + do not modify the License. You may add Your own attribution + notices within Derivative Works that You distribute, alongside + or as an addendum to the NOTICE text from the Work, provided + that such additional attribution notices cannot be construed + as modifying the License. + + You may add Your own copyright statement to Your modifications and + may provide additional or different license terms and conditions + for use, reproduction, or distribution of Your modifications, or + for any such Derivative Works as a whole, provided Your use, + reproduction, and distribution of the Work otherwise complies with + the conditions stated in this License. + + 5. Submission of Contributions. Unless You explicitly state otherwise, + any Contribution intentionally submitted for inclusion in the Work + by You to the Licensor shall be under the terms and conditions of + this License, without any additional terms or conditions. + Notwithstanding the above, nothing herein shall supersede or modify + the terms of any separate license agreement you may have executed + with Licensor regarding such Contributions. + + 6. Trademarks. This License does not grant permission to use the trade + names, trademarks, service marks, or product names of the Licensor, + except as required for reasonable and customary use in describing the + origin of the Work and reproducing the content of the NOTICE file. + + 7. Disclaimer of Warranty. Unless required by applicable law or + agreed to in writing, Licensor provides the Work (and each + Contributor provides its Contributions) on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied, including, without limitation, any warranties or conditions + of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A + PARTICULAR PURPOSE. You are solely responsible for determining the + appropriateness of using or redistributing the Work and assume any + risks associated with Your exercise of permissions under this License. + + 8. Limitation of Liability. In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + + APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "[]" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/SWM221_Lib/README.md b/SWM221_Lib/README.md new file mode 100644 index 0000000..9657a34 --- /dev/null +++ b/SWM221_Lib/README.md @@ -0,0 +1,2 @@ +# SWM221_Lib +SWM221 Chip Support Library and Sample Code diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/APP/main.c b/SWM221_Lib/SWM221_StdPeriph_Driver/APP/main.c new file mode 100644 index 0000000..815ae32 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/APP/main.c @@ -0,0 +1,63 @@ +#include "SWM221.h" + +void SerialInit(void); + + +int main(void) +{ + SystemInit(); + + SerialInit(); + + GPIO_Init(GPIOA, PIN5, 1, 0, 0, 0); //GPIOA.5LED + + GPIO_INIT(GPIOA, PIN5, GPIO_OUTPUT); //ͬϣһֿɶԸõд + + while(1==1) + { + GPIO_InvBit(GPIOA, PIN5); + + printf("Hi, World!\r\n"); + + for(int i=0; iLib folder. + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 4.60. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvproj + * + * + * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2014 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" +#define ARM_MATH_CM0_FAMILY + #elif defined (ARM_MATH_CM0PLUS) +#include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __ICCARM__ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t __packed +#elif defined __GNUC__ +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __CSMC__ /* Cosmic */ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t +#else +#error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) + +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) + +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) + + static __INLINE uint32_t __CLZ( + q31_t data); + + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & + 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) + + clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) + + clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) - + ((q15_t) (x >> 16) * (q15_t) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) + + ((q15_t) (x >> 16) * (q15_t) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + + ((q15_t) x * (q15_t) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) + + ((q15_t) x * (q15_t) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) + + ((q15_t) x * (q15_t) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + + ((q15_t) x * (q15_t) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + + ((q15_t) x * (q15_t) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE q31_t __SXTB16( + q31_t x) + { + + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); + } + + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t) *vstate, acc); + +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in > 0) + { + +// #if __FPU_USED +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + +//SMMLAR +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMLSR +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMULR +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +//SMMLA +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +//SMMLS +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) //Keil + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) //IAR + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + + #define LOW_OPTIMIZATION_EXIT + + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) // Cosmic + +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cm0.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cm0.h new file mode 100644 index 0000000..5186cb4 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cm0.h @@ -0,0 +1,711 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cm0plus.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cm0plus.h new file mode 100644 index 0000000..17e4398 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cm0plus.h @@ -0,0 +1,822 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000 + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0 + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cm3.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cm3.h new file mode 100644 index 0000000..e1357c6 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cm3.h @@ -0,0 +1,1650 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cm4.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cm4.h new file mode 100644 index 0000000..bb6be13 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cm4.h @@ -0,0 +1,1802 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cm7.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cm7.h new file mode 100644 index 0000000..242540f --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cm7.h @@ -0,0 +1,2221 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 01. September 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000 + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0 + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0 + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0 + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x07) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x07) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1]; + __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93]; + __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15]; + __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1]; + __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1]; + __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6]; + __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1]; + __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/* Cache Level ID register */ +#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* Cache Type register */ +#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */ + +/* Cache Size ID Register */ +#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */ + +/* Cache Size Selection Register */ +#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register */ +#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */ + +/* Instruction Tightly-Coupled Memory Control Register*/ +#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Registers */ +#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register */ +#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register */ +#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */ + +/* AHBS control register */ +#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register */ +#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## Cache functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) +#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos ) + + +/** \brief Enable I-Cache + + The function turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; // invalidate I-Cache + SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache + __DSB(); + __ISB(); + #endif +} + + +/** \brief Disable I-Cache + + The function turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache + SCB->ICIALLU = 0; // invalidate I-Cache + __DSB(); + __ISB(); + #endif +} + + +/** \brief Invalidate I-Cache + + The function invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; + __DSB(); + __ISB(); + #endif +} + + +/** \brief Enable D-Cache + + The function turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while(tmpways--); + } while(sets--); + __DSB(); + + SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Disable D-Cache + + The function turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache + + do { // clean & invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while(tmpways--); + } while(sets--); + + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Invalidate D-Cache + + The function invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Clean D-Cache + + The function cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // clean D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCSW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Clean & Invalidate D-Cache + + The function cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // clean & invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cmFunc.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cmFunc.h new file mode 100644 index 0000000..01089f1 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cmFunc.h @@ -0,0 +1,637 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cmInstr.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cmInstr.h new file mode 100644 index 0000000..d14110b --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cmInstr.h @@ -0,0 +1,880 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cmSimd.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cmSimd.h new file mode 100644 index 0000000..ee58eee --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/CoreSupport/core_cmSimd.h @@ -0,0 +1,697 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* not yet supported */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/DeviceSupport/SWM221.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/DeviceSupport/SWM221.h new file mode 100644 index 0000000..539154a --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/DeviceSupport/SWM221.h @@ -0,0 +1,2702 @@ +#ifndef __SWM221_H__ +#define __SWM221_H__ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers **********************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/****** Cortex-M0 specific Interrupt Numbers ************************************************/ + UART0_IRQn = 0, + TIMR0_IRQn = 1, + CAN0_IRQn = 2, + UART1_IRQn = 3, + PWM1_IRQn = 4, + TIMR1_IRQn = 5, + HALL_IRQn = 6, + PWM0_IRQn = 7, + QSPI0_IRQn = 8, + PWMBRK_IRQn = 9, + USART0_IRQn = 10, + WDT_IRQn = 11, + I2C0_IRQn = 12, + XTALSTOP_IRQn = 13, + ADC_IRQn = 14, + ACMP_IRQn = 15, + BTIMR0_IRQn = 16, + BTIMR1_IRQn = 17, + BTIMR2_IRQn = 18, + BTIMR3_IRQn = 19, + GPIOA_IRQn = 20, + GPIOB_IRQn = 21, + GPIOC_IRQn = 22, + GPIOA0_GPIOC0_IRQn = 23, + GPIOA1_GPIOC1_IRQn = 24, + GPIOA2_GPIOC2_MPU_IRQn = 25, + GPIOA3_GPIOC3_PVD_IRQn = 26, + GPIOB0_GPIOA8_TIMR2_IRQn = 27, + GPIOB1_GPIOA9_DMA_IRQn = 28, + GPIOB2_GPIOA10_DIV_IRQn = 29, + GPIOB3_GPIOA11_SPI0_IRQn = 30, + GPIOB4_GPIOB10_QEI_IRQn = 31, +} IRQn_Type; + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M0 Processor and Core Peripherals */ +#define __MPU_PRESENT 0 /*!< UART does not provide a MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< UART Supports 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +#include +#include +#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ +#include "system_SWM221.h" + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ +typedef struct { + __IO uint32_t CLKSEL; //Clock Select + + __IO uint32_t CLKDIVx_ON; //[0] CLK_DIVxʱԴ + + __IO uint32_t CLKEN0; //Clock Enable + + uint32_t RESERVED; + + __IO uint32_t SLEEP; + + uint32_t RESERVED2[4]; + + __IO uint32_t RSTSR; //Reset Status + + uint32_t RESERVED3[22]; + + __I uint32_t CHIPID[4]; + + __IO uint32_t BACKUP[4]; //Data Backup Register + + uint32_t RESERVED4[24]; + + __IO uint32_t PAWKEN; //PORTA Wakeup Enable + __IO uint32_t PBWKEN; + __IO uint32_t PCWKEN; + + uint32_t RESERVED5[9]; + + __IO uint32_t PAWKSR; //PORTA Wakeup Statusд1 + __IO uint32_t PBWKSR; + __IO uint32_t PCWKSR; + + uint32_t RESERVED6[(0x400-0x138)/4-1]; + + __IO uint32_t IOFILT0; //IO Filter 0 + __IO uint32_t IOFILT1; + + uint32_t RESERVED7[(0x720-0x404)/4-1]; + + __IO uint32_t PRSTEN; //踴λʹܣֻеPRSTENֵΪ0x55ʱдPRSTR0PRSTR1 + __IO uint32_t PRSTR0; + + //Analog Control: 0x40045800 + uint32_t RESERVED8[(0x40045800-0x40000724)/4-1]; + + __IO uint32_t PMUCR; + + __IO uint32_t VRFCR; //Vref Control Register + + __IO uint32_t RCCR; //RC Control Register + + uint32_t RESERVED9; + + __IO uint32_t XTALCR; + __IO uint32_t XTALSR; + + __IO uint32_t PLLCR; + __IO uint32_t PLLSR; + + __IO uint32_t PVDCR; + __IO uint32_t PVDSR; + + __IO uint32_t LVRCR; + + __IO uint32_t ACMP0CR; //Analog Comparator 0 Control Register + __IO uint32_t ACMP1CR; + __IO uint32_t ACMPCR; + __IO uint32_t ACMPSR; //Analog Comparator Status Register + + __IO uint32_t PGA0CR; //PGA0 Control Register + __IO uint32_t PGA1CR; + __IO uint32_t PGA2CR; + __IO uint32_t PGAREF; //PGA Vref Control Register + + __IO uint32_t TEMPCR; //Temperature Sensor Control Register + + __IO uint32_t ADCREF; //ADC Vref select +} SYS_TypeDef; + + +#define SYS_CLKSEL_SYS_Pos 0 //ϵͳʱѡ 1 HRC 0 CLK_DIVx +#define SYS_CLKSEL_SYS_Msk (0x01 << SYS_CLKSEL_SYS_Pos) +#define SYS_CLKSEL_CLK_DIVx_Pos 1 //ѡCLK_DIVx 0 CLK_DIV1 1 CLK_DIV2 2 CLK_DIV4 3 CLK_DIV8 +#define SYS_CLKSEL_CLK_DIVx_Msk (0x03 << SYS_CLKSEL_CLK_DIVx_Pos) +#define SYS_CLKSEL_CLK_Pos 3 //Clock Source 0 LRC 1 PLL 2 XTAL 3 HRC +#define SYS_CLKSEL_CLK_Msk (0x03 << SYS_CLKSEL_CLK_Pos) +#define SYS_CLKSEL_IOFILT_Pos 5 //IO Filterʱѡ0 HRC 2 XTAL 3 LRC +#define SYS_CLKSEL_IOFILT_Msk (0x03 << SYS_CLKSEL_IOFILT_Pos) +#define SYS_CLKSEL_WDT_Pos 7 //Źʱѡ 0 HRC 1 XTAL 2 LRC +#define SYS_CLKSEL_WDT_Msk (0x03 << SYS_CLKSEL_WDT_Pos) + +#define SYS_CLKDIV_ON_Pos 0 +#define SYS_CLKDIV_ON_Msk (0x01 << SYS_CLKDIV_ON_Pos) + +#define SYS_CLKEN0_GPIOA_Pos 0 +#define SYS_CLKEN0_GPIOA_Msk (0x01 << SYS_CLKEN0_GPIOA_Pos) +#define SYS_CLKEN0_GPIOB_Pos 1 +#define SYS_CLKEN0_GPIOB_Msk (0x01 << SYS_CLKEN0_GPIOB_Pos) +#define SYS_CLKEN0_GPIOC_Pos 2 +#define SYS_CLKEN0_GPIOC_Msk (0x01 << SYS_CLKEN0_GPIOC_Pos) +#define SYS_CLKEN0_UART0_Pos 3 +#define SYS_CLKEN0_UART0_Msk (0x01 << SYS_CLKEN0_UART0_Pos) +#define SYS_CLKEN0_UART1_Pos 4 +#define SYS_CLKEN0_UART1_Msk (0x01 << SYS_CLKEN0_UART1_Pos) +#define SYS_CLKEN0_USART0_Pos 5 +#define SYS_CLKEN0_USART0_Msk (0x01 << SYS_CLKEN0_USART0_Pos) +#define SYS_CLKEN0_SPI0_Pos 6 +#define SYS_CLKEN0_SPI0_Msk (0x01 << SYS_CLKEN0_SPI0_Pos) +#define SYS_CLKEN0_I2C0_Pos 7 +#define SYS_CLKEN0_I2C0_Msk (0x01 << SYS_CLKEN0_I2C0_Pos) +#define SYS_CLKEN0_QSPI0_Pos 8 +#define SYS_CLKEN0_QSPI0_Msk (0x01 << SYS_CLKEN0_QSPI0_Pos) +#define SYS_CLKEN0_TIMR_Pos 9 +#define SYS_CLKEN0_TIMR_Msk (0x01 << SYS_CLKEN0_TIMR_Pos) +#define SYS_CLKEN0_BTIMR_Pos 10 +#define SYS_CLKEN0_BTIMR_Msk (0x01 << SYS_CLKEN0_BTIMR_Pos) +#define SYS_CLKEN0_PWM_Pos 11 +#define SYS_CLKEN0_PWM_Msk (0x01 << SYS_CLKEN0_PWM_Pos) +#define SYS_CLKEN0_CRC_Pos 12 +#define SYS_CLKEN0_CRC_Msk (0x01 << SYS_CLKEN0_CRC_Pos) +#define SYS_CLKEN0_DIV_Pos 13 +#define SYS_CLKEN0_DIV_Msk (0x01 << SYS_CLKEN0_DIV_Pos) +#define SYS_CLKEN0_ANAC_Pos 14 //ģƵԪʱʹ +#define SYS_CLKEN0_ANAC_Msk (0x01 << SYS_CLKEN0_ANAC_Pos) +#define SYS_CLKEN0_ADC0_Pos 15 +#define SYS_CLKEN0_ADC0_Msk (0x01 << SYS_CLKEN0_ADC0_Pos) +#define SYS_CLKEN0_CAN0_Pos 16 +#define SYS_CLKEN0_CAN0_Msk (0x01 << SYS_CLKEN0_CAN0_Pos) +#define SYS_CLKEN0_IOFILT_Pos 17 +#define SYS_CLKEN0_IOFILT_Msk (0x01 << SYS_CLKEN0_IOFILT_Pos) +#define SYS_CLKEN0_WDT_Pos 18 +#define SYS_CLKEN0_WDT_Msk (0x01 << SYS_CLKEN0_WDT_Pos) +#define SYS_CLKEN0_MPU_Pos 19 +#define SYS_CLKEN0_MPU_Msk (0x01 << SYS_CLKEN0_MPU_Pos) +#define SYS_CLKEN0_QEI_Pos 20 +#define SYS_CLKEN0_QEI_Msk (0x01 << SYS_CLKEN0_QEI_Pos) + +#define SYS_SLEEP_SLEEP_Pos 0 //λ1ϵͳSLEEPģʽ +#define SYS_SLEEP_SLEEP_Msk (0x01 << SYS_SLEEP_SLEEP_Pos) + +#define SYS_RSTSR_POR_Pos 0 //1 ֹPORλд1 +#define SYS_RSTSR_POR_Msk (0x01 << SYS_RSTSR_POR_Pos) +#define SYS_RSTSR_WDT_Pos 1 //1 ֹWDTλд1 +#define SYS_RSTSR_WDT_Msk (0x01 << SYS_RSTSR_WDT_Pos) + +#define SYS_IOFILT_TIM_Pos 0 //˲ʱ = Tfilter_clk * ʱӷƵ * 2^TIM +#define SYS_IOFILT_TIM_Msk (0x0F << SYS_IOFILT_TIM_Pos) +#define SYS_IOFILT_CLKDIV_Pos 4 //0 ʱӲƵ 1 ʱ32Ƶ +#define SYS_IOFILT_CLKDIV_Msk (0x01 << SYS_IOFILT_CLKDIV_Pos) +#define SYS_IOFILT_IO0EN_Pos 5 //IO0 ˲ʹ +#define SYS_IOFILT_IO0EN_Msk (0x01 << SYS_IOFILT_IO0EN_Pos) +#define SYS_IOFILT_IO1EN_Pos 6 +#define SYS_IOFILT_IO1EN_Msk (0x01 << SYS_IOFILT_IO1EN_Pos) +#define SYS_IOFILT_IO2EN_Pos 7 +#define SYS_IOFILT_IO2EN_Msk (0x01 << SYS_IOFILT_IO2EN_Pos) +#define SYS_IOFILT_IO3EN_Pos 8 +#define SYS_IOFILT_IO3EN_Msk (0x01 << SYS_IOFILT_IO3EN_Pos) + +#define SYS_PRSTR0_GPIOA_Pos 0 //1 λGPIOA 0 λ +#define SYS_PRSTR0_GPIOA_Msk (0x01 < P 1 P > N +#define SYS_ACMPSR_CMP0OUT_Msk (0x01 << SYS_ACMPSR_CMP0OUT_Pos) +#define SYS_ACMPSR_CMP1OUT_Pos 9 +#define SYS_ACMPSR_CMP1OUT_Msk (0x01 << SYS_ACMPSR_CMP1OUT_Pos) + +#define SYS_PGA0CR_EN_Pos 0 +#define SYS_PGA0CR_EN_Msk (0x01 << SYS_PGA0CR_EN_Pos) +#define SYS_PGA0CR_MODE_Pos 1 //0 OPA 1 PGA +#define SYS_PGA0CR_MODE_Msk (0x01 << SYS_PGA0CR_MODE_Pos) +#define SYS_PGA0CR_ROUT_Pos 2 //ѡ0 open 1 100 2 1k 3 10k +#define SYS_PGA0CR_ROUT_Msk (0x03 << SYS_PGA0CR_ROUT_Pos) +#define SYS_PGA0CR_GAIN_Pos 4 //PGA ѡ0 x1 1 x5 2 x10 3 x20 +#define SYS_PGA0CR_GAIN_Msk (0x03 << SYS_PGA0CR_GAIN_Pos) +#define SYS_PGA0CR_BUFEN_Pos 6 // BUF ʹ +#define SYS_PGA0CR_BUFEN_Msk (0x01 << SYS_PGA0CR_BUFEN_Pos) +#define SYS_PGA0CR_BYPASS_Pos 7 // BUF · +#define SYS_PGA0CR_BYPASS_Msk (0x01 << SYS_PGA0CR_BYPASS_Pos) + +#define SYS_PGA1CR_EN_Pos 0 +#define SYS_PGA1CR_EN_Msk (0x01 << SYS_PGA1CR_EN_Pos) +#define SYS_PGA1CR_MODE_Pos 1 +#define SYS_PGA1CR_MODE_Msk (0x01 << SYS_PGA1CR_MODE_Pos) +#define SYS_PGA1CR_ROUT_Pos 2 +#define SYS_PGA1CR_ROUT_Msk (0x03 << SYS_PGA1CR_ROUT_Pos) +#define SYS_PGA1CR_GAIN_Pos 4 +#define SYS_PGA1CR_GAIN_Msk (0x03 << SYS_PGA1CR_GAIN_Pos) +#define SYS_PGA1CR_BUFEN_Pos 6 +#define SYS_PGA1CR_BUFEN_Msk (0x01 << SYS_PGA1CR_BUFEN_Pos) +#define SYS_PGA1CR_BYPASS_Pos 7 +#define SYS_PGA1CR_BYPASS_Msk (0x01 << SYS_PGA1CR_BYPASS_Pos) + +#define SYS_PGA2CR_EN_Pos 0 +#define SYS_PGA2CR_EN_Msk (0x01 << SYS_PGA2CR_EN_Pos) +#define SYS_PGA2CR_MODE_Pos 1 +#define SYS_PGA2CR_MODE_Msk (0x01 << SYS_PGA2CR_MODE_Pos) +#define SYS_PGA2CR_ROUT_Pos 2 +#define SYS_PGA2CR_ROUT_Msk (0x03 << SYS_PGA2CR_ROUT_Pos) +#define SYS_PGA2CR_GAIN_Pos 4 +#define SYS_PGA2CR_GAIN_Msk (0x03 << SYS_PGA2CR_GAIN_Pos) +#define SYS_PGA2CR_BUFEN_Pos 6 +#define SYS_PGA2CR_BUFEN_Msk (0x01 << SYS_PGA2CR_BUFEN_Pos) +#define SYS_PGA2CR_BYPASS_Pos 7 +#define SYS_PGA2CR_BYPASS_Msk (0x01 << SYS_PGA2CR_BYPASS_Pos) + +#define SYS_PGAREF_REFSEL_Pos 0 //PGA οѹѡ0 1.2v 1 1.8v 2 2.25v 3 ADCVREF/2 +#define SYS_PGAREF_REFSEL_Msk (0x03 << SYS_PGAREF_REFSEL_Pos) + +#define SYS_TEMPCR_EN_Pos 0 +#define SYS_TEMPCR_EN_Msk (0x03 << SYS_TEMPCR_EN_Pos) + +#define SYS_ADCREF_REFSEL_Pos 0 //ADC οѹѡ0 VDD 1 VREF +#define SYS_ADCREF_REFSEL_Msk (0x01 << SYS_ADCREF_REFSEL_Pos) + + + + +typedef struct { + __IO uint32_t FUNC0; //Źѡ + + __IO uint32_t FUNC1; + + uint32_t RESERVED[62]; + + __IO uint32_t PULLU; //ʹ + + uint32_t RESERVED2[63]; + + __IO uint32_t PULLD; //ʹ + + uint32_t RESERVED3[63]; + + __IO uint32_t INEN; //ʹ + + uint32_t RESERVED4[63]; + + __IO uint32_t OPEND; //©ʹ +} PORT_TypeDef; + + + + +typedef struct { + __IO uint32_t ODR; +#define PIN0 0 +#define PIN1 1 +#define PIN2 2 +#define PIN3 3 +#define PIN4 4 +#define PIN5 5 +#define PIN6 6 +#define PIN7 7 +#define PIN8 8 +#define PIN9 9 +#define PIN10 10 +#define PIN11 11 +#define PIN12 12 +#define PIN13 13 +#define PIN14 14 +#define PIN15 15 + + __IO uint32_t DIR; //0 1 + + __IO uint32_t INTLVLTRG; //Interrupt Level Trigger 1 ƽж 0 شж + + __IO uint32_t INTBE; //Both EdgeINTLVLTRGΪشжʱλ1ʾغ½ضжϣ0ʱINTRISEENѡ + + __IO uint32_t INTRISEEN; //Interrupt Rise Edge Enable 1 /ߵƽж 0 ½/͵ƽж + + __IO uint32_t INTEN; //1 жʹ 0 жϽֹ + + __I uint32_t INTRAWSTAT; //жϼⵥԪǷ⵽˴жϵ 1 ⵽жϴ 0 ûм⵽жϴ + + __I uint32_t INTSTAT; //INTSTAT.PIN0 = INTRAWSTAT.PIN0 & INTEN.PIN0 + + __O uint32_t INTCLR; //д1жϱ־ֻԱشж + + uint32_t RESERVED[3]; + + __I uint32_t IDR; + + uint32_t RESERVED2[3]; + + __IO uint32_t DATAPIN0; //PIN0ŵDATAĴŶӦ32λĴʵԭд + __IO uint32_t DATAPIN1; + __IO uint32_t DATAPIN2; + __IO uint32_t DATAPIN3; + __IO uint32_t DATAPIN4; + __IO uint32_t DATAPIN5; + __IO uint32_t DATAPIN6; + __IO uint32_t DATAPIN7; + __IO uint32_t DATAPIN8; + __IO uint32_t DATAPIN9; + __IO uint32_t DATAPIN10; + __IO uint32_t DATAPIN11; + __IO uint32_t DATAPIN12; + __IO uint32_t DATAPIN13; + __IO uint32_t DATAPIN14; + __IO uint32_t DATAPIN15; +} GPIO_TypeDef; + + + + +typedef struct { + __IO uint32_t LOAD; //ʱֵʹܺʱӴֵʼµݼ + + __I uint32_t VALUE; //ʱǰֵLDVAL-CVAL ɼʱʱ + + __IO uint32_t CR; + + uint32_t RESERVED; + + __IO uint32_t IE; + + __IO uint32_t IF; + + __IO uint32_t HALT; //[0] 1 ͣ 0 ָ + + __IO uint32_t OCCR; + + __IO uint32_t OCMAT; + __IO uint32_t RESERVED2; + + __IO uint32_t ICLOW; + __IO uint32_t ICHIGH; + + __IO uint32_t PREDIV; //ԤƵ8λ +} TIMR_TypeDef; + + +#define TIMR_LOAD_VALUE_Pos 0 +#define TIMR_LOAD_VALUE_Msk (0xFFFFFF << TIMR_LOAD_VALUE_Pos) +#define TIMR_LOAD_RELOAD_Pos 24 //1 дLOADֵʼֻBTIMRд˹ +#define TIMR_LOAD_RELOAD_Msk (0x01 << TIMR_LOAD_RELOAD_Pos) + +#define TIMR_CR_CLKSRC_Pos 0 //ʱԴ 0 ڲϵͳʱ 2 ⲿ +#define TIMR_CR_CLKSRC_Msk (0x03 << TIMR_CR_CLKSRC_Pos) +#define TIMR_CR_MODE_Pos 2 //ģʽ0 ʱ 1 벶 2 Ƚ +#define TIMR_CR_MODE_Msk (0x03 << TIMR_CR_MODE_Pos) +#define TIMR_CR_ICEDGE_Pos 4 //벶ģʽ¼أ0 ˫ 1 2 ½ +#define TIMR_CR_ICEDGE_Msk (0x03 << TIMR_CR_ICEDGE_Pos) + +#define TIMR_IE_TO_Pos 0 //Time out +#define TIMR_IE_TO_Msk (0x01 << TIMR_IE_TO_Pos) +#define TIMR_IE_OC0_Pos 1 //Ƚϣһת +#define TIMR_IE_OC0_Msk (0x01 << TIMR_IE_OC0_Pos) +#define TIMR_IE_OC1_Pos 2 //Ƚϣڶת +#define TIMR_IE_OC1_Msk (0x01 << TIMR_IE_OC1_Pos) +#define TIMR_IE_ICR_Pos 3 //벶ж +#define TIMR_IE_ICR_Msk (0x01 << TIMR_IE_ICR_Pos) +#define TIMR_IE_ICF_Pos 4 //벶½ж +#define TIMR_IE_ICF_Msk (0x01 << TIMR_IE_ICF_Pos) + +#define TIMR_IF_TO_Pos 0 //ʱжϱ־д1 +#define TIMR_IF_TO_Msk (0x01 << TIMR_IF_TO_Pos) +#define TIMR_IF_OC0_Pos 1 +#define TIMR_IF_OC0_Msk (0x01 << TIMR_IF_OC0_Pos) +#define TIMR_IF_OC1_Pos 2 +#define TIMR_IF_OC1_Msk (0x01 << TIMR_IF_OC1_Pos) +#define TIMR_IF_ICR_Pos 3 +#define TIMR_IF_ICR_Msk (0x01 << TIMR_IF_ICR_Pos) +#define TIMR_IF_ICF_Pos 4 +#define TIMR_IF_ICF_Msk (0x01 << TIMR_IF_ICF_Pos) + +#define TIMR_OCCR_FORCELVL_Pos 0 //Force Levleǿƽ +#define TIMR_OCCR_FORCELVL_Msk (0x01 << TIMR_OCCR_FORCELVL_Pos) +#define TIMR_OCCR_INITLVL_Pos 1 //Initial Level, ʼƽTimerֹͣʱģʽǡȽϡʱƽ +#define TIMR_OCCR_INITLVL_Msk (0x01 << TIMR_OCCR_INITLVL_Pos) +#define TIMR_OCCR_FORCEEN_Pos 2 //Force Enable, ǿʹ +#define TIMR_OCCR_FORCEEN_Msk (0x01 << TIMR_OCCR_FORCEEN_Pos) + + +typedef struct { + __IO uint32_t HALLIE; //[0] HALLжʹ + + uint32_t RESERVED; + + __IO uint32_t HALLIF; + + __IO uint32_t HALLEN; //[0] HALLܿ + + __IO uint32_t HALLDR; //HALLؽֵ - ǰֵ˼Ĵ + + uint32_t RESERVED2[2]; + + __IO uint32_t HALLSR; + + __IO uint32_t ICSR; //Input Capture Pin Status + + uint32_t RESERVED3[7]; + + __IO uint32_t EN; +} TIMRG_TypeDef; + + +#define TIMRG_HALLIF_IN0_Pos 0 //HALLź0жϱ־д1 +#define TIMRG_HALLIF_IN0_Msk (0x01 << TIMRG_HALLIF_IN0_Pos) +#define TIMRG_HALLIF_IN1_Pos 1 +#define TIMRG_HALLIF_IN1_Msk (0x01 << TIMRG_HALLIF_IN1_Pos) +#define TIMRG_HALLIF_IN2_Pos 2 +#define TIMRG_HALLIF_IN2_Msk (0x01 << TIMRG_HALLIF_IN2_Pos) + +#define TIMRG_HALLSR_IN0_Pos 0 //HALLźŵǰƽ +#define TIMRG_HALLSR_IN0_Msk (0x01 << TIMRG_HALLSR_IN0_Pos) +#define TIMRG_HALLSR_IN1_Pos 1 +#define TIMRG_HALLSR_IN1_Msk (0x01 << TIMRG_HALLSR_IN1_Pos) +#define TIMRG_HALLSR_IN2_Pos 2 +#define TIMRG_HALLSR_IN2_Msk (0x01 << TIMRG_HALLSR_IN2_Pos) + +#define TIMRG_ICSR_TIMR0_Pos 0 +#define TIMRG_ICSR_TIMR0_Msk (0x01 << TIMRG_ICSR_TIMR0_Pos) +#define TIMRG_ICSR_TIMR1_Pos 1 +#define TIMRG_ICSR_TIMR1_Msk (0x01 << TIMRG_ICSR_TIMR1_Pos) +#define TIMRG_ICSR_TIMR2_Pos 2 +#define TIMRG_ICSR_TIMR2_Msk (0x01 << TIMRG_ICSR_TIMR2_Pos) + +#define TIMRG_EN_TIMR0_Pos 0 +#define TIMRG_EN_TIMR0_Msk (0x01 << TIMRG_EN_TIMR0_Pos) +#define TIMRG_EN_TIMR1_Pos 1 +#define TIMRG_EN_TIMR1_Msk (0x01 << TIMRG_EN_TIMR1_Pos) +#define TIMRG_EN_TIMR2_Pos 2 +#define TIMRG_EN_TIMR2_Msk (0x01 << TIMRG_EN_TIMR2_Pos) +#define TIMRG_EN_TIMR3_Pos 3 +#define TIMRG_EN_TIMR3_Msk (0x01 << TIMRG_EN_TIMR3_Pos) + + + + +typedef struct { + __IO uint32_t DATA; + + __IO uint32_t CTRL; + + __IO uint32_t BAUD; + + __IO uint32_t FIFO; + + __IO uint32_t LINCR; + + union { + __IO uint32_t CTSCR; + + __IO uint32_t RTSCR; + }; + + __IO uint32_t CFG; + + __IO uint32_t TOCR; //Timeout Control Register +} UART_TypeDef; + + +#define UART_DATA_DATA_Pos 0 +#define UART_DATA_DATA_Msk (0x1FF << UART_DATA_DATA_Pos) +#define UART_DATA_VALID_Pos 9 //DATAֶЧĽʱλӲ1ȡݺԶ +#define UART_DATA_VALID_Msk (0x01 << UART_DATA_VALID_Pos) +#define UART_DATA_PAERR_Pos 10 //Parity Error +#define UART_DATA_PAERR_Msk (0x01 << UART_DATA_PAERR_Pos) + +#define UART_CTRL_TXIDLE_Pos 0 //TX IDLE: 0 ڷ 1 ״̬ûݷ +#define UART_CTRL_TXIDLE_Msk (0x01 << UART_CTRL_TXIDLE_Pos) +#define UART_CTRL_TXFF_Pos 1 //TX FIFO Full +#define UART_CTRL_TXFF_Msk (0x01 << UART_CTRL_TXFF_Pos) +#define UART_CTRL_TXIE_Pos 2 //TX жʹ: 1 TX FF 趨ʱж +#define UART_CTRL_TXIE_Msk (0x01 << UART_CTRL_TXIE_Pos) +#define UART_CTRL_RXNE_Pos 3 //RX FIFO Not Empty +#define UART_CTRL_RXNE_Msk (0x01 << UART_CTRL_RXNE_Pos) +#define UART_CTRL_RXIE_Pos 4 //RX жʹ: 1 RX FF ݴﵽ趨ʱж +#define UART_CTRL_RXIE_Msk (0x01 << UART_CTRL_RXIE_Pos) +#define UART_CTRL_RXOV_Pos 5 //RX FIFO Overflowд1 +#define UART_CTRL_RXOV_Msk (0x01 << UART_CTRL_RXOV_Pos) +#define UART_CTRL_TXDOIE_Pos 6 //TX Done жʹܣFIFOҷͷλĴѽһλͳȥ +#define UART_CTRL_TXDOIE_Msk (0x01 << UART_CTRL_TXDOIE_Pos) +#define UART_CTRL_EN_Pos 9 +#define UART_CTRL_EN_Msk (0x01 << UART_CTRL_EN_Pos) +#define UART_CTRL_LOOP_Pos 10 +#define UART_CTRL_LOOP_Msk (0x01 << UART_CTRL_LOOP_Pos) +#define UART_CTRL_TOIE_Pos 14 //TimeOut жʹܣյϸַ󣬳 TOTIME/BAUDRAUD ûнյµ +#define UART_CTRL_TOIE_Msk (0x01 << UART_CTRL_TOIE_Pos) +#define UART_CTRL_DATA9b_Pos 18 //1 9λλ 0 8λλ +#define UART_CTRL_DATA9b_Msk (0x01 << UART_CTRL_DATA9b_Pos) +#define UART_CTRL_PARITY_Pos 19 //000 У 001 У 011 żУ 101 ̶Ϊ1 111 ̶Ϊ0 +#define UART_CTRL_PARITY_Msk (0x07 << UART_CTRL_PARITY_Pos) +#define UART_CTRL_STOP2b_Pos 22 //1 2λֹͣλ 0 1λֹͣλ +#define UART_CTRL_STOP2b_Msk (0x03 << UART_CTRL_STOP2b_Pos) + +#define UART_BAUD_BAUD_Pos 0 //ڲ = SYS_Freq/16/BAUD - 1 +#define UART_BAUD_BAUD_Msk (0x3FFF << UART_BAUD_BAUD_Pos) +#define UART_BAUD_TXD_Pos 14 //ͨλֱӶȡTXDϵĵƽ +#define UART_BAUD_TXD_Msk (0x01 << UART_BAUD_TXD_Pos) +#define UART_BAUD_RXD_Pos 15 //ͨλֱӶȡRXDϵĵƽ +#define UART_BAUD_RXD_Msk (0x01 << UART_BAUD_RXD_Pos) +#define UART_BAUD_RXTOIF_Pos 16 //&ʱжϱ־ = RXIF | TOIF +#define UART_BAUD_RXTOIF_Msk (0x01 << UART_BAUD_RXTOIF_Pos) +#define UART_BAUD_TXIF_Pos 17 //жϱ־ = TXTHRF & TXIE +#define UART_BAUD_TXIF_Msk (0x01 << UART_BAUD_TXIF_Pos) +#define UART_BAUD_RXTHRF_Pos 19 //RX FIFO Threshold FlagRX FIFOݴﵽ趨RXLVL > RXTHRʱӲ1 +#define UART_BAUD_RXTHRF_Msk (0x01 << UART_BAUD_RXTHRF_Pos) +#define UART_BAUD_TXTHRF_Pos 20 //TX FIFO Threshold FlagTX FIFO趨TXLVL <= TXTHRʱӲ1 +#define UART_BAUD_TXTHRF_Msk (0x01 << UART_BAUD_TXTHRF_Pos) +#define UART_BAUD_TOIF_Pos 21 //TimeOut жϱ־ TOTIME/BAUDRAUD ûнյµʱTOIE=1λӲλ +#define UART_BAUD_TOIF_Msk (0x01 << UART_BAUD_TOIF_Pos) +#define UART_BAUD_RXIF_Pos 22 //жϱ־ = RXTHRF & RXIE +#define UART_BAUD_RXIF_Msk (0x01 << UART_BAUD_RXIF_Pos) +#define UART_BAUD_ABREN_Pos 23 //Auto Baudrate Enableд1ԶУ׼ɺԶ +#define UART_BAUD_ABREN_Msk (0x01 << UART_BAUD_ABREN_Pos) +#define UART_BAUD_ABRBIT_Pos 24 //Auto Baudrate Bitڼ㲨ʵļλ0 1λͨʼλ 㲨ʣҪͶ˷0xFF + // 1 2λͨʼλ1λλ㲨ʣҪͶ˷0xFE + // 1 4λͨʼλ3λλ㲨ʣҪͶ˷0xF8 + // 1 8λͨʼλ7λλ㲨ʣҪͶ˷0x80 +#define UART_BAUD_ABRBIT_Msk (0x03 << UART_BAUD_ABRBIT_Pos) +#define UART_BAUD_ABRERR_Pos 26 //Auto Baudrate Error0 ԶУ׼ɹ 1 ԶУ׼ʧ +#define UART_BAUD_ABRERR_Msk (0x01 << UART_BAUD_ABRERR_Pos) +#define UART_BAUD_TXDOIF_Pos 27 //TX Done жϱ־FIFOҷͷλĴѽһλͳȥ +#define UART_BAUD_TXDOIF_Msk (0x01 << UART_BAUD_TXDOIF_Pos) +#define UART_BAUD_FRAC_Pos 28 //ʷƵֵС +#define UART_BAUD_FRAC_Msk (0x0Fu << UART_BAUD_FRAC_Pos) + +#define UART_FIFO_RXLVL_Pos 0 //RX FIFO LevelRX FIFO ַ +#define UART_FIFO_RXLVL_Msk (0xFF << UART_FIFO_RXLVL_Pos) +#define UART_FIFO_TXLVL_Pos 8 //TX FIFO LevelTX FIFO ַ +#define UART_FIFO_TXLVL_Msk (0xFF << UART_FIFO_TXLVL_Pos) +#define UART_FIFO_RXTHR_Pos 16 //RX FIFO ThresholdRXжϴޣжʹʱ RXLVL > RXTHR RXж +#define UART_FIFO_RXTHR_Msk (0xFF << UART_FIFO_RXTHR_Pos) +#define UART_FIFO_TXTHR_Pos 24 //TX FIFO ThresholdTXжϴޣжʹʱ TXLVL <= TXTHR TXж +#define UART_FIFO_TXTHR_Msk (0xFFu<< UART_FIFO_TXTHR_Pos) + +#define UART_LINCR_BRKDETIE_Pos 0 //⵽LIN Breakжʹ +#define UART_LINCR_BRKDETIE_Msk (0x01 << UART_LINCR_BRKDETIE_Pos) +#define UART_LINCR_BRKDETIF_Pos 1 //⵽LIN Breakж״̬ +#define UART_LINCR_BRKDETIF_Msk (0x01 << UART_LINCR_BRKDETIF_Pos) +#define UART_LINCR_GENBRKIE_Pos 2 //LIN Breakжʹ +#define UART_LINCR_GENBRKIE_Msk (0x01 << UART_LINCR_GENBRKIE_Pos) +#define UART_LINCR_GENBRKIF_Pos 3 //LIN Breakж״̬ +#define UART_LINCR_GENBRKIF_Msk (0x01 << UART_LINCR_GENBRKIF_Pos) +#define UART_LINCR_GENBRK_Pos 4 //LIN BreakԶ +#define UART_LINCR_GENBRK_Msk (0x01 << UART_LINCR_GENBRK_Pos) + +#define UART_CTSCR_EN_Pos 0 //CTSʹ +#define UART_CTSCR_EN_Msk (0x01 << UART_CTSCR_EN_Pos) +#define UART_CTSCR_POL_Pos 2 //CTSźżԣ0 ЧCTSΪͱʾԷ +#define UART_CTSCR_POL_Msk (0x01 << UART_CTSCR_POL_Pos) +#define UART_CTSCR_STAT_Pos 7 //CTSźŵĵǰ״̬ +#define UART_CTSCR_STAT_Msk (0x01 << UART_CTSCR_STAT_Pos) + +#define UART_RTSCR_EN_Pos 1 //RTSʹ +#define UART_RTSCR_EN_Msk (0x01 << UART_RTSCR_EN_Pos) +#define UART_RTSCR_POL_Pos 3 //RTSźż 0 ЧRTSΪͱʾԽ +#define UART_RTSCR_POL_Msk (0x01 << UART_RTSCR_POL_Pos) +#define UART_RTSCR_THR_Pos 4 //RTSصĴֵ 0 1ֽ 1 2ֽ 2 4ֽ 3 6ֽ +#define UART_RTSCR_THR_Msk (0x07 << UART_RTSCR_THR_Pos) +#define UART_RTSCR_STAT_Pos 8 //RTSźŵĵǰ״̬ +#define UART_RTSCR_STAT_Msk (0x01 << UART_RTSCR_STAT_Pos) + +#define UART_CFG_MSBF_Pos 1 //շMSB First +#define UART_CFG_MSBF_Msk (0x01 << UART_CFG_MSBF_Pos) +#define UART_CFG_BRKTXLEN_Pos 2 //1ʾ1bitԴƣĬֵ13 +#define UART_CFG_BRKTXLEN_Msk (0x0F << UART_CFG_BRKTXLEN_Pos) +#define UART_CFG_BRKRXLEN_Pos 6 //0ʾ1bitԴƣĬֵ12 +#define UART_CFG_BRKRXLEN_Msk (0x0F << UART_CFG_BRKRXLEN_Pos) +#define UART_CFG_RXINV_Pos 10 //յƽת +#define UART_CFG_RXINV_Msk (0x01 << UART_CFG_RXINV_Pos) +#define UART_CFG_TXINV_Pos 11 //͵ƽת +#define UART_CFG_TXINV_Msk (0x01 << UART_CFG_TXINV_Pos) + +#define UART_TOCR_TIME_Pos 0 //ʱʱ䳤ȣλΪ 10/BAUDRATE +#define UART_TOCR_TIME_Msk (0xFFF<< UART_TOCR_TIME_Pos) +#define UART_TOCR_MODE_Pos 12 //0 ֻеFIFOʱŴʱж 1 ʹFIFOûҲɴʱж +#define UART_TOCR_MODE_Msk (0x01 << UART_TOCR_MODE_Pos) +#define UART_TOCR_IFCLR_Pos 13 //TO Interrupt Flag Clearд1ʱжϱ־ +#define UART_TOCR_IFCLR_Msk (0x01 << UART_TOCR_IFCLR_Pos) + + + + +typedef struct { + __O uint32_t CR; + + __IO uint32_t MR; + + __O uint32_t IER; //Interrupt Enable Register + + __O uint32_t IDR; //Interrupt Disable Register + + __I uint32_t IMR; //Interrupt Enable value register + + __I uint32_t ISR; + + __I uint32_t RHR; //Receiver Holding Register + + __O uint32_t THR; //Transmitter Holding Register + + __IO uint32_t BAUD; //Baud Rate + + __IO uint32_t RXTO; //Receiver Time-out, 1-65535 bit period + + uint32_t RESERVED[11]; + + __IO uint32_t LINMR; //LIN Mode Register + + __IO uint32_t LINID; + + __I uint32_t LINBR; //LIN Baud Rate Register +} USART_TypeDef; + + +#define USART_CR_RSTRX_Pos 2 //Reset Receiver +#define USART_CR_RSTRX_Msk (0x01 << USART_CR_RSTRX_Pos) +#define USART_CR_RSTTX_Pos 3 //Reset Transmitter +#define USART_CR_RSTTX_Msk (0x01 << USART_CR_RSTTX_Pos) +#define USART_CR_RXEN_Pos 4 //Receiver Enable +#define USART_CR_RXEN_Msk (0x01 << USART_CR_RXEN_Pos) +#define USART_CR_RXDIS_Pos 5 //Receiver Disable +#define USART_CR_RXDIS_Msk (0x01 << USART_CR_RXDIS_Pos) +#define USART_CR_TXEN_Pos 6 //Transmitter Enable +#define USART_CR_TXEN_Msk (0x01 << USART_CR_TXEN_Pos) +#define USART_CR_TXDIS_Pos 7 //Transmitter Disable +#define USART_CR_TXDIS_Msk (0x01 << USART_CR_TXDIS_Pos) +#define USART_CR_RSTSTA_Pos 8 //Reset Status Bits +#define USART_CR_RSTSTA_Msk (0x01 << USART_CR_RSTSTA_Pos) +#define USART_CR_STTBRK_Pos 9 //Start Break +#define USART_CR_STTBRK_Msk (0x01 << USART_CR_STTBRK_Pos) +#define USART_CR_STPBRK_Pos 10 //Stop Break +#define USART_CR_STPBRK_Msk (0x01 << USART_CR_STPBRK_Pos) +#define USART_CR_STTTO_Pos 11 //Start Time-out +#define USART_CR_STTTO_Msk (0x01 << USART_CR_STTTO_Pos) +#define USART_CR_RETTO_Pos 15 //Rearm Time-out +#define USART_CR_RETTO_Msk (0x01 << USART_CR_RETTO_Pos) +#define USART_CR_LINABT_Pos 20 //Abort the current LIN transmission. +#define USART_CR_LINABT_Msk (0x01 << USART_CR_LINABT_Pos) +#define USART_CR_LINWKUP_Pos 21 //Sends a wakeup signal on the LIN bus. +#define USART_CR_LINWKUP_Msk (0x01 << USART_CR_LINWKUP_Pos) + +#define USART_MR_MODE_Pos 0 //0 UART 10 LIN Master 11 LIN Slave +#define USART_MR_MODE_Msk (0x0F << USART_MR_MODE_Pos) +#define USART_MR_CLKS_Pos 4 //Clock source +#define USART_MR_CLKS_Msk (0x03 << USART_MR_CLKS_Pos) +#define USART_MR_NBDATA_Pos 6 //Number of Data bits, 0 5bit 1 6bit 2 7bit 3 8bit +#define USART_MR_NBDATA_Msk (0x03 << USART_MR_NBDATA_Pos) +#define USART_MR_PARITY_Pos 9 //0 Even parity 1 Odd parity 2 force 0 3 force 1 4 No parity 6 Multidrop mode +#define USART_MR_PARITY_Msk (0x07 << USART_MR_PARITY_Pos) +#define USART_MR_NBSTOP_Pos 12 //Number of Stop bits, 0 1bit 1 1.5bit 2 2bit +#define USART_MR_NBSTOP_Msk (0x03 << USART_MR_NBSTOP_Pos) +#define USART_MR_MSBF_Pos 16 //MSB first +#define USART_MR_MSBF_Msk (0x01 << USART_MR_MSBF_Pos) +#define USART_MR_DATA9b_Pos 17 //1 9-bit data length +#define USART_MR_DATA9b_Msk (0x01 << USART_MR_DATA9b_Pos) +#define USART_MR_OVER8_Pos 19 //0 16x Oversampling 1 8x Oversampling +#define USART_MR_OVER8_Msk (0x01 << USART_MR_OVER8_Pos) + +#define USART_IER_RXRDY_Pos 0 +#define USART_IER_RXRDY_Msk (0x01 << USART_IER_RXRDY_Pos) +#define USART_IER_TXRDY_Pos 1 +#define USART_IER_TXRDY_Msk (0x01 << USART_IER_TXRDY_Pos) +#define USART_IER_RXBRK_Pos 2 +#define USART_IER_RXBRK_Msk (0x01 << USART_IER_RXBRK_Pos) +#define USART_IER_OVRERR_Pos 5 +#define USART_IER_OVRERR_Msk (0x01 << USART_IER_OVRERR_Pos) +#define USART_IER_FRAMERR_Pos 6 +#define USART_IER_FRAMERR_Msk (0x01 << USART_IER_FRAMERR_Pos) +#define USART_IER_PARITYERR_Pos 7 +#define USART_IER_PARITYERR_Msk (0x01 << USART_IER_PARITYERR_Pos) +#define USART_IER_RXTO_Pos 8 +#define USART_IER_RXTO_Msk (0x01 << USART_IER_RXTO_Pos) +#define USART_IER_TXEMPTY_Pos 9 +#define USART_IER_TXEMPTY_Msk (0x01 << USART_IER_TXEMPTY_Pos) +#define USART_IER_TXBEMPTY_Pos 11 +#define USART_IER_TXBEMPTY_Msk (0x01 << USART_IER_TXBEMPTY_Pos) +#define USART_IER_RXBFULL_Pos 12 +#define USART_IER_RXBFULL_Msk (0x01 << USART_IER_RXBFULL_Pos) +#define USART_IER_BRK_Pos 13 +#define USART_IER_BRK_Msk (0x01 << USART_IER_BRK_Pos) +#define USART_IER_ID_Pos 14 +#define USART_IER_ID_Msk (0x01 << USART_IER_ID_Pos) +#define USART_IER_DONE_Pos 15 +#define USART_IER_DONE_Msk (0x01 << USART_IER_DONE_Pos) +#define USART_IER_BITERR_Pos 25 +#define USART_IER_BITERR_Msk (0x01 << USART_IER_BITERR_Pos) +#define USART_IER_SYNCERR_Pos 26 +#define USART_IER_SYNCERR_Msk (0x01 << USART_IER_SYNCERR_Pos) +#define USART_IER_IDERR_Pos 27 +#define USART_IER_IDERR_Msk (0x01 << USART_IER_IDERR_Pos) +#define USART_IER_CHKERR_Pos 28 +#define USART_IER_CHKERR_Msk (0x01 << USART_IER_CHKERR_Pos) +#define USART_IER_NAKERR_Pos 29 +#define USART_IER_NAKERR_Msk (0x01 << USART_IER_NAKERR_Pos) +#define USART_IER_HDRTO_Pos 31 +#define USART_IER_HDRTO_Msk (0x01 << USART_IER_HDRTO_Pos) + +#define USART_IDR_RXRDY_Pos 0 +#define USART_IDR_RXRDY_Msk (0x01 << USART_IDR_RXRDY_Pos) +#define USART_IDR_TXRDY_Pos 1 +#define USART_IDR_TXRDY_Msk (0x01 << USART_IDR_TXRDY_Pos) +#define USART_IDR_RXBRK_Pos 2 +#define USART_IDR_RXBRK_Msk (0x01 << USART_IDR_RXBRK_Pos) +#define USART_IDR_OVRERR_Pos 5 +#define USART_IDR_OVRERR_Msk (0x01 << USART_IDR_OVRERR_Pos) +#define USART_IDR_FRAMERR_Pos 6 +#define USART_IDR_FRAMERR_Msk (0x01 << USART_IDR_FRAMERR_Pos) +#define USART_IDR_PARITYERR_Pos 7 +#define USART_IDR_PARITYERR_Msk (0x01 << USART_IDR_PARITYERR_Pos) +#define USART_IDR_RXTO_Pos 8 +#define USART_IDR_RXTO_Msk (0x01 << USART_IDR_RXTO_Pos) +#define USART_IDR_TXEMPTY_Pos 9 +#define USART_IDR_TXEMPTY_Msk (0x01 << USART_IDR_TXEMPTY_Pos) +#define USART_IDR_TXBEMPTY_Pos 11 +#define USART_IDR_TXBEMPTY_Msk (0x01 << USART_IDR_TXBEMPTY_Pos) +#define USART_IDR_RXBFULL_Pos 12 +#define USART_IDR_RXBFULL_Msk (0x01 << USART_IDR_RXBFULL_Pos) +#define USART_IDR_BRK_Pos 13 +#define USART_IDR_BRK_Msk (0x01 << USART_IDR_BRK_Pos) +#define USART_IDR_ID_Pos 14 +#define USART_IDR_ID_Msk (0x01 << USART_IDR_ID_Pos) +#define USART_IDR_DONE_Pos 15 +#define USART_IDR_DONE_Msk (0x01 << USART_IDR_DONE_Pos) +#define USART_IDR_BITERR_Pos 25 +#define USART_IDR_BITERR_Msk (0x01 << USART_IDR_BITERR_Pos) +#define USART_IDR_SYNCERR_Pos 26 +#define USART_IDR_SYNCERR_Msk (0x01 << USART_IDR_SYNCERR_Pos) +#define USART_IDR_IDERR_Pos 27 +#define USART_IDR_IDERR_Msk (0x01 << USART_IDR_IDERR_Pos) +#define USART_IDR_CHKERR_Pos 28 +#define USART_IDR_CHKERR_Msk (0x01 << USART_IDR_CHKERR_Pos) +#define USART_IDR_NAKERR_Pos 29 +#define USART_IDR_NAKERR_Msk (0x01 << USART_IDR_NAKERR_Pos) +#define USART_IDR_HDRTO_Pos 31 +#define USART_IDR_HDRTO_Msk (0x01 << USART_IDR_HDRTO_Pos) + +#define USART_IMR_RXRDY_Pos 0 +#define USART_IMR_RXRDY_Msk (0x01 << USART_IMR_RXRDY_Pos) +#define USART_IMR_TXRDY_Pos 1 +#define USART_IMR_TXRDY_Msk (0x01 << USART_IMR_TXRDY_Pos) +#define USART_IMR_RXBRK_Pos 2 +#define USART_IMR_RXBRK_Msk (0x01 << USART_IMR_RXBRK_Pos) +#define USART_IMR_OVRERR_Pos 5 +#define USART_IMR_OVRERR_Msk (0x01 << USART_IMR_OVRERR_Pos) +#define USART_IMR_FRAMERR_Pos 6 +#define USART_IMR_FRAMERR_Msk (0x01 << USART_IMR_FRAMERR_Pos) +#define USART_IMR_PARITYERR_Pos 7 +#define USART_IMR_PARITYERR_Msk (0x01 << USART_IMR_PARITYERR_Pos) +#define USART_IMR_RXTO_Pos 8 +#define USART_IMR_RXTO_Msk (0x01 << USART_IMR_RXTO_Pos) +#define USART_IMR_TXEMPTY_Pos 9 +#define USART_IMR_TXEMPTY_Msk (0x01 << USART_IMR_TXEMPTY_Pos) +#define USART_IMR_TXBEMPTY_Pos 11 +#define USART_IMR_TXBEMPTY_Msk (0x01 << USART_IMR_TXBEMPTY_Pos) +#define USART_IMR_RXBFULL_Pos 12 +#define USART_IMR_RXBFULL_Msk (0x01 << USART_IMR_RXBFULL_Pos) +#define USART_IMR_BRK_Pos 13 +#define USART_IMR_BRK_Msk (0x01 << USART_IMR_BRK_Pos) +#define USART_IMR_ID_Pos 14 +#define USART_IMR_ID_Msk (0x01 << USART_IMR_ID_Pos) +#define USART_IMR_DONE_Pos 15 +#define USART_IMR_DONE_Msk (0x01 << USART_IMR_DONE_Pos) +#define USART_IMR_BITERR_Pos 25 +#define USART_IMR_BITERR_Msk (0x01 << USART_IMR_BITERR_Pos) +#define USART_IMR_SYNCERR_Pos 26 +#define USART_IMR_SYNCERR_Msk (0x01 << USART_IMR_SYNCERR_Pos) +#define USART_IMR_IDERR_Pos 27 +#define USART_IMR_IDERR_Msk (0x01 << USART_IMR_IDERR_Pos) +#define USART_IMR_CHKERR_Pos 28 +#define USART_IMR_CHKERR_Msk (0x01 << USART_IMR_CHKERR_Pos) +#define USART_IMR_NAKERR_Pos 29 +#define USART_IMR_NAKERR_Msk (0x01 << USART_IMR_NAKERR_Pos) +#define USART_IMR_HDRTO_Pos 31 +#define USART_IMR_HDRTO_Msk (0x01 << USART_IMR_HDRTO_Pos) + +#define USART_ISR_RXRDY_Pos 0 //RHR ݣ RHR +#define USART_ISR_RXRDY_Msk (0x01 << USART_ISR_RXRDY_Pos) +#define USART_ISR_TXRDY_Pos 1 //THR ݣд THR +#define USART_ISR_TXRDY_Msk (0x01 << USART_ISR_TXRDY_Pos) +#define USART_ISR_RXBRK_Pos 2 //Break Received or End of Break detected, CR.RSTSTA д 1 +#define USART_ISR_RXBRK_Msk (0x01 << USART_ISR_RXBRK_Pos) +#define USART_ISR_OVRERR_Pos 5 //CR.RSTSTA д 1 +#define USART_ISR_OVRERR_Msk (0x01 << USART_ISR_OVRERR_Pos) +#define USART_ISR_FRAMERR_Pos 6 //֡ʽCR.RSTSTA д 1 +#define USART_ISR_FRAMERR_Msk (0x01 << USART_ISR_FRAMERR_Pos) +#define USART_ISR_PARITYERR_Pos 7 //УλCR.RSTSTA д 1 +#define USART_ISR_PARITYERR_Msk (0x01 << USART_ISR_PARITYERR_Pos) +#define USART_ISR_RXTO_Pos 8 //ճʱCR.STTTO д 1 +#define USART_ISR_RXTO_Msk (0x01 << USART_ISR_RXTO_Pos) +#define USART_ISR_TXEMPTY_Pos 9 //THR ͷλĴнݣд THR +#define USART_ISR_TXEMPTY_Msk (0x01 << USART_ISR_TXEMPTY_Pos) +#define USART_ISR_TXBEMPTY_Pos 11 +#define USART_ISR_TXBEMPTY_Msk (0x01 << USART_ISR_TXBEMPTY_Pos) +#define USART_ISR_RXBFULL_Pos 12 +#define USART_ISR_RXBFULL_Msk (0x01 << USART_ISR_RXBFULL_Pos) +#define USART_ISR_BRK_Pos 13 //LIN Break Sent or LIN Break Received, CR.RSTSTA д 1 +#define USART_ISR_BRK_Msk (0x01 << USART_ISR_BRK_Pos) +#define USART_ISR_ID_Pos 14 //LIN Identifier Sent or LIN Identifier Received, CR.RSTSTA д 1 +#define USART_ISR_ID_Msk (0x01 << USART_ISR_ID_Pos) +#define USART_ISR_DONE_Pos 15 //LIN Transfer Completed, CR.RSTSTA д 1 +#define USART_ISR_DONE_Msk (0x01 << USART_ISR_DONE_Pos) +#define USART_ISR_BUSSTA_Pos 23 //LIN Bus Line Status +#define USART_ISR_BUSSTA_Msk (0x01 << USART_ISR_BUSSTA_Pos) +#define USART_ISR_BITERR_Pos 25 //A Bit Error has been detected, CR.RSTSTA д 1 +#define USART_ISR_BITERR_Msk (0x01 << USART_ISR_BITERR_Pos) +#define USART_ISR_SYNCERR_Pos 26 //LIN Slave ģʽ£a LIN Inconsistent Synch Field Error has been detected, CR.RSTSTA д 1 +#define USART_ISR_SYNCERR_Msk (0x01 << USART_ISR_SYNCERR_Pos) +#define USART_ISR_IDERR_Pos 27 //A LIN Identifier Parity Error has been detected, CR.RSTSTA д 1 +#define USART_ISR_IDERR_Msk (0x01 << USART_ISR_IDERR_Pos) +#define USART_ISR_CHKERR_Pos 28 //A LIN Checksum Error has been detected, CR.RSTSTA д 1 +#define USART_ISR_CHKERR_Msk (0x01 << USART_ISR_CHKERR_Pos) +#define USART_ISR_NAKERR_Pos 29 //A LIN Slave Not Responding Error has been detected, CR.RSTSTA д 1 +#define USART_ISR_NAKERR_Msk (0x01 << USART_ISR_NAKERR_Pos) +#define USART_ISR_HDRTO_Pos 31 //A LIN Header Timeout Error has been detected, CR.RSTSTA д 1 +#define USART_ISR_HDRTO_Msk (0x01u<< USART_ISR_HDRTO_Pos) + +#define USART_RHR_DATA_Pos 0 +#define USART_RHR_DATA_Msk (0x1FF<< USART_RHR_DATA_Pos) + +#define USART_THR_DATA_Pos 0 +#define USART_THR_DATA_Msk (0x1FF<< USART_THR_DATA_Pos) + +#define USART_BAUD_IDIV_Pos 0 +#define USART_BAUD_IDIV_Msk (0xFFFF << USART_BAUD_IDIV_Pos) +#define USART_BAUD_FDIV_Pos 16 +#define USART_BAUD_FDIV_Msk (0x07 << USART_BAUD_FDIV_Pos) + +#define USART_LINMR_NACT_Pos 0 //Node Action, 0 transmit the response 1 receive the response 2 ignore +#define USART_LINMR_NACT_Msk (0x03 << USART_LINMR_NACT_Pos) +#define USART_LINMR_PARDIS_Pos 2 //Parity Disable +#define USART_LINMR_PARDIS_Msk (0x01 << USART_LINMR_PARDIS_Pos) +#define USART_LINMR_CHKDIS_Pos 3 //Checksum Disable +#define USART_LINMR_CHKDIS_Msk (0x01 << USART_LINMR_CHKDIS_Pos) +#define USART_LINMR_CHKTYP_Pos 4 //0 LIN 2.0 Enhanced Checksum 1 LIN 1.3 Classic Checksum +#define USART_LINMR_CHKTYP_Msk (0x01 << USART_LINMR_CHKTYP_Pos) +#define USART_LINMR_RDLMOD_Pos 5 //Response Data Length defined by: 0 DLC field 1 the bits 5 and 6 of LINID register +#define USART_LINMR_RDLMOD_Msk (0x01 << USART_LINMR_RDLMOD_Pos) +#define USART_LINMR_FSMDIS_Pos 6 //Frame Slot Mode Disable +#define USART_LINMR_FSMDIS_Msk (0x01 << USART_LINMR_FSMDIS_Pos) +#define USART_LINMR_WKUPTYP_Pos 7 //0 LIN 2.0 wakeup signal 1 LIN 1.3 wakeup signal +#define USART_LINMR_WKUPTYP_Msk (0x01 << USART_LINMR_WKUPTYP_Pos) +#define USART_LINMR_DLC_Pos 8 //response data length is equal to DLC+1 bytes +#define USART_LINMR_DLC_Msk (0xFF << USART_LINMR_DLC_Pos) +#define USART_LINMR_SYNCDIS_Pos 17 //Synchronization Disable +#define USART_LINMR_SYNCDIS_Msk (0x01 << USART_LINMR_SYNCDIS_Pos) + +#define USART_LINBR_IDIV_Pos 0 //Returns the baud rate value after the synchronization process completion. +#define USART_LINBR_IDIV_Msk (0xFFFF << USART_LINBR_IDIV_Pos) +#define USART_LINBR_FDIV_Pos 16 +#define USART_LINBR_FDIV_Msk (0x07 << USART_LINBR_FDIV_Pos) + + + + +typedef struct { + __IO uint32_t CTRL; + + __IO uint32_t DATA; + + __IO uint32_t STAT; + + __IO uint32_t IE; + + __IO uint32_t IF; +} SPI_TypeDef; + + +#define SPI_CTRL_CLKDIV_Pos 0 //Clock Divider, SPIʱ = SYS_Freq/pow(2, CLKDIV+2) +#define SPI_CTRL_CLKDIV_Msk (0x07 << SPI_CTRL_CLKDIV_Pos) +#define SPI_CTRL_EN_Pos 3 +#define SPI_CTRL_EN_Msk (0x01 << SPI_CTRL_EN_Pos) +#define SPI_CTRL_SIZE_Pos 4 //Data Size Select, ȡֵ3--15ʾ4--16λ +#define SPI_CTRL_SIZE_Msk (0x0F << SPI_CTRL_SIZE_Pos) +#define SPI_CTRL_CPHA_Pos 8 //0 SCLKĵһز 1 SCLKĵڶز +#define SPI_CTRL_CPHA_Msk (0x01 << SPI_CTRL_CPHA_Pos) +#define SPI_CTRL_CPOL_Pos 9 //0 ״̬SCLKΪ͵ƽ 1 ״̬SCLKΪߵƽ +#define SPI_CTRL_CPOL_Msk (0x01 << SPI_CTRL_CPOL_Pos) +#define SPI_CTRL_FFS_Pos 10 //Frame Format Select, 0 SPI 1 TI SSI 2 I2S 3 SPI Flash +#define SPI_CTRL_FFS_Msk (0x03 << SPI_CTRL_FFS_Pos) +#define SPI_CTRL_MSTR_Pos 12 //Master, 1 ģʽ 0 ģʽ +#define SPI_CTRL_MSTR_Msk (0x01 << SPI_CTRL_MSTR_Pos) +#define SPI_CTRL_FAST_Pos 13 //1 SPIʱ = SYS_Freq/2 0 SPIʱSPI->CTRL.CLKDIV +#define SPI_CTRL_FAST_Msk (0x01 << SPI_CTRL_FAST_Pos) +#define SPI_CTRL_DMATXEN_Pos 14 //1 ͨDMAдFIFO 0 ͨMCUдFIFO +#define SPI_CTRL_DMATXEN_Msk (0x01 << SPI_CTRL_DMATXEN_Pos) +#define SPI_CTRL_DMARXEN_Pos 15 //1 ͨDMAFIFO 0 ͨMCUFIFO +#define SPI_CTRL_DMARXEN_Msk (0x01 << SPI_CTRL_DMARXEN_Pos) +#define SPI_CTRL_FILTE_Pos 16 //1 SPIźŽȥ 0 SPIźŲȥ +#define SPI_CTRL_FILTE_Msk (0x01 << SPI_CTRL_FILTE_Pos) +#define SPI_CTRL_SSN_H_Pos 17 //0 SSNʼΪ0 1 ÿַ֮ὫSSN߰SCLK +#define SPI_CTRL_SSN_H_Msk (0x01 << SPI_CTRL_SSN_H_Pos) +#define SPI_CTRL_RFTHR_Pos 18 //RX FIFO Threshold0 FIFO1 ... 7 FIFO8 +#define SPI_CTRL_RFTHR_Msk (0x07 << SPI_CTRL_RFTHR_Pos) +#define SPI_CTRL_TFTHR_Pos 21 //TX FIFO Threshold0 FIFO0 ... 7 FIFO7 +#define SPI_CTRL_TFTHR_Msk (0x07 << SPI_CTRL_TFTHR_Pos) +#define SPI_CTRL_RFCLR_Pos 24 //RX FIFO Clear +#define SPI_CTRL_RFCLR_Msk (0x01 << SPI_CTRL_RFCLR_Pos) +#define SPI_CTRL_TFCLR_Pos 25 //TX FIFO Clear +#define SPI_CTRL_TFCLR_Msk (0x01 << SPI_CTRL_TFCLR_Pos) +#define SPI_CTRL_LSBF_Pos 28 //LSB Fisrt +#define SPI_CTRL_LSBF_Msk (0x01 << SPI_CTRL_LSBF_Pos) +#define SPI_CTRL_NSYNC_Pos 29 //1 SPIźŽвͬ 0 SPIźŲвͬ +#define SPI_CTRL_NSYNC_Msk (0x01 << SPI_CTRL_NSYNC_Pos) + +#define SPI_STAT_WTC_Pos 0 //Word Transmit CompleteÿһӲ1д1 +#define SPI_STAT_WTC_Msk (0x01 << SPI_STAT_WTC_Pos) +#define SPI_STAT_TFE_Pos 1 //FIFO Empty +#define SPI_STAT_TFE_Msk (0x01 << SPI_STAT_TFE_Pos) +#define SPI_STAT_TFNF_Pos 2 //FIFO Not Full +#define SPI_STAT_TFNF_Msk (0x01 << SPI_STAT_TFNF_Pos) +#define SPI_STAT_RFNE_Pos 3 //FIFO Not Empty +#define SPI_STAT_RFNE_Msk (0x01 << SPI_STAT_RFNE_Pos) +#define SPI_STAT_RFF_Pos 4 //FIFO Full +#define SPI_STAT_RFF_Msk (0x01 << SPI_STAT_RFF_Pos) +#define SPI_STAT_RFOV_Pos 5 //FIFO Overflow +#define SPI_STAT_RFOV_Msk (0x01 << SPI_STAT_RFOV_Pos) +#define SPI_STAT_TFLVL_Pos 6 //FIFOݸ 0 TFNF=0ʱʾFIFO8ݣTFNF=1ʱʾFIFO0 1--7 FIFO1--7 +#define SPI_STAT_TFLVL_Msk (0x07 << SPI_STAT_TFLVL_Pos) +#define SPI_STAT_RFLVL_Pos 9 //FIFOݸ 0 RFF =1ʱʾFIFO8ݣRFF =0ʱʾFIFO0 1--7 FIFO1--7 +#define SPI_STAT_RFLVL_Msk (0x07 << SPI_STAT_RFLVL_Pos) +#define SPI_STAT_BUSY_Pos 15 +#define SPI_STAT_BUSY_Msk (0x01 << SPI_STAT_BUSY_Pos) + +#define SPI_IE_RFOV_Pos 0 +#define SPI_IE_RFOV_Msk (0x01 << SPI_IE_RFOV_Pos) +#define SPI_IE_RFF_Pos 1 +#define SPI_IE_RFF_Msk (0x01 << SPI_IE_RFF_Pos) +#define SPI_IE_RFHF_Pos 2 +#define SPI_IE_RFHF_Msk (0x01 << SPI_IE_RFHF_Pos) +#define SPI_IE_TFE_Pos 3 +#define SPI_IE_TFE_Msk (0x01 << SPI_IE_TFE_Pos) +#define SPI_IE_TFHF_Pos 4 //FIFOݸ4 +#define SPI_IE_TFHF_Msk (0x01 << SPI_IE_TFHF_Pos) +#define SPI_IE_RFTHR_Pos 5 //FIFOݸCTRL.RFTHR趨ֵжʹ +#define SPI_IE_RFTHR_Msk (0x01 << SPI_IE_RFTHR_Pos) +#define SPI_IE_TFTHR_Pos 6 //FIFOݸСCTRL.TFTHR趨ֵжʹ +#define SPI_IE_TFTHR_Msk (0x01 << SPI_IE_TFTHR_Pos) +#define SPI_IE_WTC_Pos 8 //Word Transmit Complete +#define SPI_IE_WTC_Msk (0x01 << SPI_IE_WTC_Pos) +#define SPI_IE_FTC_Pos 9 //Frame Transmit Complete +#define SPI_IE_FTC_Msk (0x01 << SPI_IE_FTC_Pos) +#define SPI_IE_CSFALL_Pos 10 //ӻģʽ£CS½жʹ +#define SPI_IE_CSFALL_Msk (0x01 << SPI_IE_CSFALL_Pos) +#define SPI_IE_CSRISE_Pos 11 //ӻģʽ£CSжʹ +#define SPI_IE_CSRISE_Msk (0x01 << SPI_IE_CSRISE_Pos) + +#define SPI_IF_RFOV_Pos 0 //д1 +#define SPI_IF_RFOV_Msk (0x01 << SPI_IF_RFOV_Pos) +#define SPI_IF_RFF_Pos 1 //д1 +#define SPI_IF_RFF_Msk (0x01 << SPI_IF_RFF_Pos) +#define SPI_IF_RFHF_Pos 2 //д1 +#define SPI_IF_RFHF_Msk (0x01 << SPI_IF_RFHF_Pos) +#define SPI_IF_TFE_Pos 3 //д1 +#define SPI_IF_TFE_Msk (0x01 << SPI_IF_TFE_Pos) +#define SPI_IF_TFHF_Pos 4 //д1 +#define SPI_IF_TFHF_Msk (0x01 << SPI_IF_TFHF_Pos) +#define SPI_IF_RFTHR_Pos 5 //д1 +#define SPI_IF_RFTHR_Msk (0x01 << SPI_IF_RFTHR_Pos) +#define SPI_IF_TFTHR_Pos 6 //д1 +#define SPI_IF_TFTHR_Msk (0x01 << SPI_IF_TFTHR_Pos) +#define SPI_IF_WTC_Pos 8 //Word Transmit CompleteÿһӲ1 +#define SPI_IF_WTC_Msk (0x01 << SPI_IF_WTC_Pos) +#define SPI_IF_FTC_Pos 9 //Frame Transmit CompleteWTCλʱTX FIFOǿյģFTCλ +#define SPI_IF_FTC_Msk (0x01 << SPI_IF_FTC_Pos) +#define SPI_IF_CSFALL_Pos 10 +#define SPI_IF_CSFALL_Msk (0x01 << SPI_IF_CSFALL_Pos) +#define SPI_IF_CSRISE_Pos 11 +#define SPI_IF_CSRISE_Msk (0x01 << SPI_IF_CSRISE_Pos) + + + + +typedef struct { + __IO uint32_t CR; + + __IO uint32_t SR; + + __IO uint32_t TR; //Transfer Register + + __IO uint32_t RXDATA; + + __IO uint32_t TXDATA; + + __IO uint32_t IF; + + __IO uint32_t IE; + + uint32_t RESERVED1; + + __IO uint32_t MCR; //Master Control Register + + __IO uint32_t CLK; + + uint32_t RESERVED2[2]; + + __IO uint32_t SCR; //Slave Control Register + + __IO uint32_t SADDR; +} I2C_TypeDef; + + +#define I2C_CR_EN_Pos 0 +#define I2C_CR_EN_Msk (0x01 << I2C_CR_EN_Pos) +#define I2C_CR_MASTER_Pos 1 //1 Master 0 Slave +#define I2C_CR_MASTER_Msk (0x01 << I2C_CR_MASTER_Pos) +#define I2C_CR_HS_Pos 2 //1 High-Speed mode 0 Standard-mode or Fast-mode +#define I2C_CR_HS_Msk (0x01 << I2C_CR_HS_Pos) +#define I2C_CR_DNF_Pos 3 //Digital Noise Filter, ȵ DNF+1 ĵƽΪë +#define I2C_CR_DNF_Msk (0x0F << I2C_CR_DNF_Pos) + +#define I2C_SR_BUSY_Pos 0 +#define I2C_SR_BUSY_Msk (0x01 << I2C_SR_BUSY_Pos) +#define I2C_SR_SCL_Pos 1 //SCL Line Level +#define I2C_SR_SCL_Msk (0x01 << I2C_SR_SCL_Pos) +#define I2C_SR_SDA_Pos 2 //SDA Line Level +#define I2C_SR_SDA_Msk (0x01 << I2C_SR_SDA_Pos) + +#define I2C_TR_TXACK_Pos 0 //ΪʱACKλĵƽֵ +#define I2C_TR_TXACK_Msk (0x01 << I2C_TR_TXACK_Pos) +#define I2C_TR_RXACK_Pos 1 //ΪʱյACKλƽֵ +#define I2C_TR_RXACK_Msk (0x01 << I2C_TR_RXACK_Pos) +#define I2C_TR_TXCLR_Pos 2 //TX Data Clear, Զ +#define I2C_TR_TXCLR_Msk (0x01 << I2C_TR_TXCLR_Pos) +#define I2C_TR_SLVACT_Pos 8 //Slave Active, ӻģʽ±ѡʱλ +#define I2C_TR_SLVACT_Msk (0x01 << I2C_TR_SLVACT_Pos) +#define I2C_TR_SLVRD_Pos 9 //Slave Read modeӻģʽ½յʱλ +#define I2C_TR_SLVRD_Msk (0x01 << I2C_TR_SLVRD_Pos) +#define I2C_TR_SLVWR_Pos 10 //Slave Write modeӻģʽ½յдʱλ +#define I2C_TR_SLVWR_Msk (0x01 << I2C_TR_SLVWR_Pos) +#define I2C_TR_SLVSTR_Pos 11 //Slave clock stretching +#define I2C_TR_SLVSTR_Msk (0x01 << I2C_TR_SLVSTR_Pos) +#define I2C_TR_SLVRDS_Pos 12 //Slave RXDATA Status, 0 1 յַ 2 յ 3 յMaster Code +#define I2C_TR_SLVRDS_Msk (0x03 << I2C_TR_SLVRDS_Pos) + +#define I2C_IF_TXE_Pos 0 //TX EmptyдTXDATAλ +#define I2C_IF_TXE_Msk (0x01 << I2C_IF_TXE_Pos) +#define I2C_IF_RXNE_Pos 1 //RX Not EmptyRXDATAλ +#define I2C_IF_RXNE_Msk (0x01 << I2C_IF_RXNE_Pos) +#define I2C_IF_RXOV_Pos 2 //RX Overflowд1 +#define I2C_IF_RXOV_Msk (0x01 << I2C_IF_RXOV_Pos) +#define I2C_IF_TXDONE_Pos 3 //TX Doneд1 +#define I2C_IF_TXDONE_Msk (0x01 << I2C_IF_TXDONE_Pos) +#define I2C_IF_RXDONE_Pos 4 //RX Doneд1 +#define I2C_IF_RXDONE_Msk (0x01 << I2C_IF_RXDONE_Pos) +#define I2C_IF_RXSTA_Pos 8 //ӻյʼλд1 +#define I2C_IF_RXSTA_Msk (0x01 << I2C_IF_RXSTA_Pos) +#define I2C_IF_RXSTO_Pos 9 //ӻյֹͣλд1 +#define I2C_IF_RXSTO_Msk (0x01 << I2C_IF_RXSTO_Pos) +#define I2C_IF_AL_Pos 16 //ٲöʧߣд1 +#define I2C_IF_AL_Msk (0x01 << I2C_IF_AL_Pos) +#define I2C_IF_MLTO_Pos 17 //Master SCL Low Timeoutд1 +#define I2C_IF_MLTO_Msk (0x01 << I2C_IF_MLTO_Pos) + +#define I2C_IE_TXE_Pos 0 +#define I2C_IE_TXE_Msk (0x01 << I2C_IE_TXE_Pos) +#define I2C_IE_RXNE_Pos 1 +#define I2C_IE_RXNE_Msk (0x01 << I2C_IE_RXNE_Pos) +#define I2C_IE_RXOV_Pos 2 +#define I2C_IE_RXOV_Msk (0x01 << I2C_IE_RXOV_Pos) +#define I2C_IE_TXDONE_Pos 3 +#define I2C_IE_TXDONE_Msk (0x01 << I2C_IE_TXDONE_Pos) +#define I2C_IE_RXDONE_Pos 4 +#define I2C_IE_RXDONE_Msk (0x01 << I2C_IE_RXDONE_Pos) +#define I2C_IE_RXSTA_Pos 8 +#define I2C_IE_RXSTA_Msk (0x01 << I2C_IE_RXSTA_Pos) +#define I2C_IE_RXSTO_Pos 9 +#define I2C_IE_RXSTO_Msk (0x01 << I2C_IE_RXSTO_Pos) +#define I2C_IE_AL_Pos 16 +#define I2C_IE_AL_Msk (0x01 << I2C_IE_AL_Pos) +#define I2C_IE_MLTO_Pos 17 +#define I2C_IE_MLTO_Msk (0x01 << I2C_IE_MLTO_Pos) + +#define I2C_MCR_STA_Pos 0 //д1ʼλɺԶ +#define I2C_MCR_STA_Msk (0x01 << I2C_MCR_STA_Pos) +#define I2C_MCR_RD_Pos 1 +#define I2C_MCR_RD_Msk (0x01 << I2C_MCR_RD_Pos) +#define I2C_MCR_WR_Pos 2 +#define I2C_MCR_WR_Msk (0x01 << I2C_MCR_WR_Pos) +#define I2C_MCR_STO_Pos 3 //д1ֹͣλɺԶ +#define I2C_MCR_STO_Msk (0x01 << I2C_MCR_STO_Pos) + +#define I2C_CLK_SCLL_Pos 0 //SCL Low Time +#define I2C_CLK_SCLL_Msk (0xFF << I2C_CLK_SCLL_Pos) +#define I2C_CLK_SCLH_Pos 8 //SCL High Time +#define I2C_CLK_SCLH_Msk (0xFF << I2C_CLK_SCLH_Pos) +#define I2C_CLK_DIV_Pos 16 +#define I2C_CLK_DIV_Msk (0xFF << I2C_CLK_DIV_Pos) +#define I2C_CLK_SDAH_Pos 24 //SDA Hold Time +#define I2C_CLK_SDAH_Msk (0x0F << I2C_CLK_SDAH_Pos) + +#define I2C_SCR_ADDR10_Pos 0 //1 10λַ 0 7λַ +#define I2C_SCR_ADDR10_Msk (0x01 << I2C_SCR_ADDR10_Pos) +#define I2C_SCR_MCDE_Pos 1 //Master Code Detect Enable +#define I2C_SCR_MCDE_Msk (0x01 << I2C_SCR_MCDE_Pos) +#define I2C_SCR_STRE_Pos 2 //Clock Stretching Enable +#define I2C_SCR_STRE_Msk (0x01 << I2C_SCR_STRE_Pos) +#define I2C_SCR_ASDS_Pos 3 //Adaptive Stretching Data Setup +#define I2C_SCR_ASDS_Msk (0x01 << I2C_SCR_ASDS_Pos) + +#define I2C_SADDR_ADDR7_Pos 1 //7λַģʽµĵַ +#define I2C_SADDR_ADDR7_Msk (0x7F << I2C_SADDR_ADDR7_Pos) +#define I2C_SADDR_ADDR10_Pos 0 //10λַģʽµĵַ +#define I2C_SADDR_ADDR10_Msk (0x3FF<< I2C_SADDR_ADDR10_Pos) +#define I2C_SADDR_MASK7_Pos 17 //7λַģʽµĵַ룬ADDR7 & (~MASK7) յַȽ +#define I2C_SADDR_MASK7_Msk (0x7F << I2C_SADDR_MASK7_Pos) +#define I2C_SADDR_MASK10_Pos 16 //10λַģʽµĵַ룬ֻ8λ +#define I2C_SADDR_MASK10_Msk (0xFF << I2C_SADDR_MASK10_Pos) + + + + +typedef struct { + __IO uint32_t CR; + + __IO uint32_t IE; + + __IO uint32_t IF; + + __IO uint32_t SMPNUM; + + __IO uint32_t SMPTIM; + + __IO uint32_t SEQTRG; + + __IO uint32_t SEQ0CHN; + + __IO uint32_t SEQ1CHN; + + __IO uint32_t SEQ0CHK; + + __IO uint32_t SEQ1CHK; + + uint32_t RESERVED[2]; + + __IO uint32_t DATA[10]; + + uint32_t RESERVED2[6]; + + __IO uint32_t SEQ0DMA; + + __IO uint32_t SEQ1DMA; + + uint32_t RESERVED3[98]; + + __IO uint32_t START; +} ADC_TypeDef; + + +#define ADC_CR_PWDN_Pos 0 //1 Power Down 0 ģʽд 0 ȴ 32 +#define ADC_CR_PWDN_Msk (0x01 << ADC_CR_PWDN_Pos) +#define ADC_CR_RESET_Pos 1 //ģIPڲ߼λӲԶ +#define ADC_CR_RESET_Msk (0x01 << ADC_CR_RESET_Pos) +#define ADC_CR_BITS_Pos 2 //תλ0 12-bit 1 10-bit 2 8-bit 3 6-bit +#define ADC_CR_BITS_Msk (0x03 << ADC_CR_BITS_Pos) +#define ADC_CR_SEQ0DMAEN_Pos 4 +#define ADC_CR_SEQ0DMAEN_Msk (0x01 << ADC_CR_SEQ0DMAEN_Pos) +#define ADC_CR_SEQ1DMAEN_Pos 5 +#define ADC_CR_SEQ1DMAEN_Msk (0x01 << ADC_CR_SEQ1DMAEN_Pos) +#define ADC_CR_AVG_Pos 6 // +#define ADC_CR_AVG_Msk (0x03 << ADC_CR_AVG_Pos) +#define ADC_CR_CLKDIV_Pos 8 +#define ADC_CR_CLKDIV_Msk (0x1F << ADC_CR_CLKDIV_Pos) + +#define ADC_IE_SEQ0EOC_Pos 0 +#define ADC_IE_SEQ0EOC_Msk (0x01 << ADC_IE_SEQ0EOC_Pos) +#define ADC_IE_SEQ0MAX_Pos 1 +#define ADC_IE_SEQ0MAX_Msk (0x01 << ADC_IE_SEQ0MAX_Pos) +#define ADC_IE_SEQ0MIN_Pos 2 +#define ADC_IE_SEQ0MIN_Msk (0x01 << ADC_IE_SEQ0MIN_Pos) +#define ADC_IE_SEQ1EOC_Pos 8 +#define ADC_IE_SEQ1EOC_Msk (0x01 << ADC_IE_SEQ1EOC_Pos) +#define ADC_IE_SEQ1MAX_Pos 9 +#define ADC_IE_SEQ1MAX_Msk (0x01 << ADC_IE_SEQ1MAX_Pos) +#define ADC_IE_SEQ1MIN_Pos 10 +#define ADC_IE_SEQ1MIN_Msk (0x01 << ADC_IE_SEQ1MIN_Pos) + +#define ADC_IF_SEQ0EOC_Pos 0 +#define ADC_IF_SEQ0EOC_Msk (0x01 << ADC_IF_SEQ0EOC_Pos) +#define ADC_IF_SEQ0MAX_Pos 1 +#define ADC_IF_SEQ0MAX_Msk (0x01 << ADC_IF_SEQ0MAX_Pos) +#define ADC_IF_SEQ0MIN_Pos 2 +#define ADC_IF_SEQ0MIN_Msk (0x01 << ADC_IF_SEQ0MIN_Pos) +#define ADC_IF_SEQ0BRK_Pos 3 //CPUPWMϣ״̬λж +#define ADC_IF_SEQ0BRK_Msk (0x01 << ADC_IF_SEQ0BRK_Pos) +#define ADC_IF_SEQ1EOC_Pos 8 +#define ADC_IF_SEQ1EOC_Msk (0x01 << ADC_IF_SEQ1EOC_Pos) +#define ADC_IF_SEQ1MAX_Pos 9 +#define ADC_IF_SEQ1MAX_Msk (0x01 << ADC_IF_SEQ1MAX_Pos) +#define ADC_IF_SEQ1MIN_Pos 10 +#define ADC_IF_SEQ1MIN_Msk (0x01 << ADC_IF_SEQ1MIN_Pos) +#define ADC_IF_SEQ1BRK_Pos 11 +#define ADC_IF_SEQ1BRK_Msk (0x01 << ADC_IF_SEQ1BRK_Pos) + +#define ADC_SMPNUM_SEQ0_Pos 0 +#define ADC_SMPNUM_SEQ0_Msk (0xFF << ADC_SMPNUM_SEQ0_Pos) +#define ADC_SMPNUM_SEQ1_Pos 8 +#define ADC_SMPNUM_SEQ1_Msk (0xFF << ADC_SMPNUM_SEQ1_Pos) + +#define ADC_SMPTIM_SEQ0_Pos 0 +#define ADC_SMPTIM_SEQ0_Msk (0xFF << ADC_SMPTIM_SEQ0_Pos) +#define ADC_SMPTIM_SEQ1_Pos 8 +#define ADC_SMPTIM_SEQ1_Msk (0xFF << ADC_SMPTIM_SEQ1_Pos) + +#define ADC_SEQTRG_SEQ0_Pos 0 +#define ADC_SEQTRG_SEQ0_Msk (0xFF << ADC_SEQTRG_SEQ0_Pos) +#define ADC_SEQTRG_SEQ1_Pos 8 +#define ADC_SEQTRG_SEQ1_Msk (0xFF << ADC_SEQTRG_SEQ1_Pos) + +#define ADC_SEQ0CHN_CH0_Pos 0 +#define ADC_SEQ0CHN_CH0_Msk (0x0F << ADC_SEQ0CHN_CH0_Pos) +#define ADC_SEQ0CHN_CH1_Pos 4 +#define ADC_SEQ0CHN_CH1_Msk (0x0F << ADC_SEQ0CHN_CH1_Pos) +#define ADC_SEQ0CHN_CH2_Pos 8 +#define ADC_SEQ0CHN_CH2_Msk (0x0F << ADC_SEQ0CHN_CH2_Pos) +#define ADC_SEQ0CHN_CH3_Pos 12 +#define ADC_SEQ0CHN_CH3_Msk (0x0F << ADC_SEQ0CHN_CH3_Pos) +#define ADC_SEQ0CHN_CH4_Pos 16 +#define ADC_SEQ0CHN_CH4_Msk (0x0F << ADC_SEQ0CHN_CH4_Pos) +#define ADC_SEQ0CHN_CH5_Pos 20 +#define ADC_SEQ0CHN_CH5_Msk (0x0F << ADC_SEQ0CHN_CH5_Pos) +#define ADC_SEQ0CHN_CH6_Pos 24 +#define ADC_SEQ0CHN_CH6_Msk (0x0F << ADC_SEQ0CHN_CH6_Pos) +#define ADC_SEQ0CHN_CH7_Pos 28 +#define ADC_SEQ0CHN_CH7_Msk (0x0F << ADC_SEQ0CHN_CH7_Pos) + +#define ADC_SEQ1CHN_CH0_Pos 0 +#define ADC_SEQ1CHN_CH0_Msk (0x0F << ADC_SEQ1CHN_CH0_Pos) +#define ADC_SEQ1CHN_CH1_Pos 4 +#define ADC_SEQ1CHN_CH1_Msk (0x0F << ADC_SEQ1CHN_CH1_Pos) +#define ADC_SEQ1CHN_CH2_Pos 8 +#define ADC_SEQ1CHN_CH2_Msk (0x0F << ADC_SEQ1CHN_CH2_Pos) +#define ADC_SEQ1CHN_CH3_Pos 12 +#define ADC_SEQ1CHN_CH3_Msk (0x0F << ADC_SEQ1CHN_CH3_Pos) +#define ADC_SEQ1CHN_CH4_Pos 16 +#define ADC_SEQ1CHN_CH4_Msk (0x0F << ADC_SEQ1CHN_CH4_Pos) +#define ADC_SEQ1CHN_CH5_Pos 20 +#define ADC_SEQ1CHN_CH5_Msk (0x0F << ADC_SEQ1CHN_CH5_Pos) +#define ADC_SEQ1CHN_CH6_Pos 24 +#define ADC_SEQ1CHN_CH6_Msk (0x0F << ADC_SEQ1CHN_CH6_Pos) +#define ADC_SEQ1CHN_CH7_Pos 28 +#define ADC_SEQ1CHN_CH7_Msk (0x0F << ADC_SEQ1CHN_CH7_Pos) + +#define ADC_SEQ0CHK_MAX_Pos 0 +#define ADC_SEQ0CHK_MAX_Msk (0xFFF<< ADC_SEQ0CHK_MAX_Pos) +#define ADC_SEQ0CHK_MIN_Pos 16 +#define ADC_SEQ0CHK_MIN_Msk (0xFFF<< ADC_SEQ0CHK_MIN_Pos) + +#define ADC_SEQ1CHK_MAX_Pos 0 +#define ADC_SEQ1CHK_MAX_Msk (0xFFF<< ADC_SEQ1CHK_MAX_Pos) +#define ADC_SEQ1CHK_MIN_Pos 16 +#define ADC_SEQ1CHK_MIN_Msk (0xFFF<< ADC_SEQ1CHK_MIN_Pos) + +#define ADC_DATA_DATA_Pos 0 +#define ADC_DATA_DATA_Msk (0xFFF<< ADC_DATA_DATA_Pos) +#define ADC_DATA_FLAG_Pos 16 //0 ϴζȡ 1 2 ݸ +#define ADC_DATA_FLAG_Msk (0x03 << ADC_DATA_FLAG_Pos) + +#define ADC_SEQ0DMA_DATA_Pos 0 +#define ADC_SEQ0DMA_DATA_Msk (0xFFF<< ADC_SEQ0DMA_DATA_Pos) +#define ADC_SEQ0DMA_CHNUM_Pos 12 +#define ADC_SEQ0DMA_CHNUM_Msk (0x0F << ADC_SEQ0DMA_CHNUM_Pos) +#define ADC_SEQ0DMA_FLAG_Pos 16 +#define ADC_SEQ0DMA_FLAG_Msk (0x03 << ADC_SEQ0DMA_FLAG_Pos) + +#define ADC_SEQ1DMA_DATA_Pos 0 +#define ADC_SEQ1DMA_DATA_Msk (0xFFF<< ADC_SEQ1DMA_DATA_Pos) +#define ADC_SEQ1DMA_CHNUM_Pos 12 +#define ADC_SEQ1DMA_CHNUM_Msk (0x0F << ADC_SEQ1DMA_CHNUM_Pos) +#define ADC_SEQ1DMA_FLAG_Pos 16 +#define ADC_SEQ1DMA_FLAG_Msk (0x03 << ADC_SEQ1DMA_FLAG_Pos) + +#define ADC_START_ADC0SEQ0_Pos 0 +#define ADC_START_ADC0SEQ0_Msk (0x01 << ADC_START_ADC0SEQ0_Pos) +#define ADC_START_ADC0SEQ1_Pos 1 +#define ADC_START_ADC0SEQ1_Msk (0x01 << ADC_START_ADC0SEQ1_Pos) +#define ADC_START_ADC0BUSY_Pos 2 +#define ADC_START_ADC0BUSY_Msk (0x01 << ADC_START_ADC0BUSY_Pos) +#define ADC_START_ADC1SEQ0_Pos 8 +#define ADC_START_ADC1SEQ0_Msk (0x01 << ADC_START_ADC1SEQ0_Pos) +#define ADC_START_ADC1SEQ1_Pos 9 +#define ADC_START_ADC1SEQ1_Msk (0x01 << ADC_START_ADC1SEQ1_Pos) +#define ADC_START_ADC1BUSY_Pos 10 +#define ADC_START_ADC1BUSY_Msk (0x01 << ADC_START_ADC1BUSY_Pos) + + + + +typedef struct { + __IO uint32_t CR; + + __IO uint32_t OCR; + + __IO uint32_t BRKCR; + + __IO uint32_t BRKIN; + + uint32_t RESERVED[4]; + + __IO uint32_t PERIOD; //[15:0] + + __IO uint32_t CMPA; //[15:0] A·תȽֵ + + __IO uint32_t CMPB; //[15:0] B·תȽֵ + + __IO uint32_t DZA; //[9:0] + + __IO uint32_t DZB; + + __IO uint32_t CMPA2; //ǶԳĶģʽ£¼УA·תȽֵ + + __IO uint32_t CMPB2; //ǶԳĶģʽ£¼УB·תȽֵ + + uint32_t RESERVED2[5]; + + __IO uint32_t OVFTRG; + + __IO uint32_t CMPTRG; + + __IO uint32_t CMPTRG2; + + uint32_t RESERVED3; + + __IO uint32_t EVMUX; + + __IO uint32_t EVMSK; + + uint32_t RESERVED4[2]; + + __IO uint32_t IE; + + __IO uint32_t IF; + + __IO uint32_t VALUE; + + __IO uint32_t SR; +} PWM_TypeDef; + + +#define PWM_CR_MODE_Pos 0 //0 ضģʽ 1 Ķģʽ 2 ǶԳĶģʽ +#define PWM_CR_MODE_Msk (0x03 << PWM_CR_MODE_Pos) +#define PWM_CR_MULT_Pos 2 //0 μģʽ 1 μģʽ +#define PWM_CR_MULT_Msk (0x01 << PWM_CR_MULT_Pos) +#define PWM_CR_DIR_Pos 3 // 0 ϼ 1 ¼ +#define PWM_CR_DIR_Msk (0x01 << PWM_CR_DIR_Pos) +#define PWM_CR_CLKSRC_Pos 4 //ʱԴ0 ϵͳʱ 1 PWM_PULSE0 2 PWM_PULSE1 +#define PWM_CR_CLKSRC_Msk (0x03 << PWM_CR_CLKSRC_Pos) +#define PWM_CR_CLKDIV_Pos 6 //ʱԤƵ 0 1Ƶ 1 2Ƶ ... 1023 1024Ƶ +#define PWM_CR_CLKDIV_Msk (0x3FF<< PWM_CR_CLKDIV_Pos) +#define PWM_CR_RPTNUM_Pos 16 //ٴִһμĴأ0 1 1 2 ... 255 256 +#define PWM_CR_RPTNUM_Msk (0xFF << PWM_CR_RPTNUM_Pos) + +#define PWM_OCR_IDLEA_Pos 0 //A·ʱƽ +#define PWM_OCR_IDLEA_Msk (0x01 << PWM_OCR_IDLEA_Pos) +#define PWM_OCR_IDLEB_Pos 1 //B·ʱƽ +#define PWM_OCR_IDLEB_Msk (0x01 << PWM_OCR_IDLEB_Pos) +#define PWM_OCR_IDLEAN_Pos 2 //AN·ʱƽ +#define PWM_OCR_IDLEAN_Msk (0x01 << PWM_OCR_IDLEAN_Pos) +#define PWM_OCR_IDLEBN_Pos 3 //BN·ʱƽ +#define PWM_OCR_IDLEBN_Msk (0x01 << PWM_OCR_IDLEBN_Pos) +#define PWM_OCR_INVA_Pos 4 //A·Ƿȡ +#define PWM_OCR_INVA_Msk (0x01 << PWM_OCR_INVA_Pos) +#define PWM_OCR_INVB_Pos 5 //B·Ƿȡ +#define PWM_OCR_INVB_Msk (0x01 << PWM_OCR_INVB_Pos) +#define PWM_OCR_INVAN_Pos 6 //AN·Ƿȡ +#define PWM_OCR_INVAN_Msk (0x01 << PWM_OCR_INVAN_Pos) +#define PWM_OCR_INVBN_Pos 7 //BN·Ƿȡ +#define PWM_OCR_INVBN_Msk (0x01 << PWM_OCR_INVBN_Pos) +#define PWM_OCR_FORCEA_Pos 8 //A·ǿʹܣǿƵƽ IDLEA 趨 +#define PWM_OCR_FORCEA_Msk (0x01 << PWM_OCR_FORCEA_Pos) +#define PWM_OCR_FORCEB_Pos 9 +#define PWM_OCR_FORCEB_Msk (0x01 << PWM_OCR_FORCEB_Pos) +#define PWM_OCR_FORCEAN_Pos 10 +#define PWM_OCR_FORCEAN_Msk (0x01 << PWM_OCR_FORCEAN_Pos) +#define PWM_OCR_FORCEBN_Pos 11 +#define PWM_OCR_FORCEBN_Msk (0x01 << PWM_OCR_FORCEBN_Pos) + +#define PWM_BRKCR_OUTA_Pos 0 //ɲ״̬A·ƽ +#define PWM_BRKCR_OUTA_Msk (0x01 << PWM_BRKCR_OUTA_Pos) +#define PWM_BRKCR_OFFA_Pos 1 //ɲźųʱA·0 ָ 1 ֵǰֱٻָ +#define PWM_BRKCR_OFFA_Msk (0x01 << PWM_BRKCR_OFFA_Pos) +#define PWM_BRKCR_OUTB_Pos 4 //ɲ״̬B·ƽ +#define PWM_BRKCR_OUTB_Msk (0x01 << PWM_BRKCR_OUTB_Pos) +#define PWM_BRKCR_OFFB_Pos 5 //ɲźųʱB·0 ָ 1 ֵǰֱٻָ +#define PWM_BRKCR_OFFB_Msk (0x01 << PWM_BRKCR_OFFB_Pos) +#define PWM_BRKCR_OUTAN_Pos 8 //ɲ״̬AN·ƽ +#define PWM_BRKCR_OUTAN_Msk (0x01 << PWM_BRKCR_OUTAN_Pos) +#define PWM_BRKCR_OUTBN_Pos 9 //ɲ״̬BN·ƽ +#define PWM_BRKCR_OUTBN_Msk (0x01 << PWM_BRKCR_OUTBN_Pos) +#define PWM_BRKCR_STPCNT_Pos 10 //ɲ״̬Ƿֹͣ1 ֹͣ 0 +#define PWM_BRKCR_STPCNT_Msk (0x01 << PWM_BRKCR_STPCNT_Pos) +#define PWM_BRKCR_SWHALT_Pos 16 //ǰǷɲ״̬ +#define PWM_BRKCR_SWHALT_Msk (0x01 << PWM_BRKCR_SWHALT_Pos) +#define PWM_BRKCR_HWHALT_Pos 17 //ǰǷӲɲ״̬ +#define PWM_BRKCR_HWHALT_Msk (0x01 << PWM_BRKCR_HWHALT_Pos) + +#define PWM_BRKIN_BRK0A_Pos 0 //A·ǷɲPWM_BRK0Ӱ +#define PWM_BRKIN_BRK0A_Msk (0x01 << PWM_BRKIN_BRK0A_Pos) +#define PWM_BRKIN_BRK1A_Pos 1 +#define PWM_BRKIN_BRK1A_Msk (0x01 << PWM_BRKIN_BRK1A_Pos) +#define PWM_BRKIN_BRK2A_Pos 2 +#define PWM_BRKIN_BRK2A_Msk (0x01 << PWM_BRKIN_BRK2A_Pos) +#define PWM_BRKIN_BRK0B_Pos 4 +#define PWM_BRKIN_BRK0B_Msk (0x01 << PWM_BRKIN_BRK0B_Pos) +#define PWM_BRKIN_BRK1B_Pos 5 +#define PWM_BRKIN_BRK1B_Msk (0x01 << PWM_BRKIN_BRK1B_Pos) +#define PWM_BRKIN_BRK2B_Pos 6 +#define PWM_BRKIN_BRK2B_Msk (0x01 << PWM_BRKIN_BRK2B_Pos) + +#define PWM_OVFTRG_UPEN_Pos 0 //Triggerʹ +#define PWM_OVFTRG_UPEN_Msk (0x01 << PWM_OVFTRG_UPEN_Pos) +#define PWM_OVFTRG_DNEN_Pos 1 //Triggerʹ +#define PWM_OVFTRG_DNEN_Msk (0x01 << PWM_OVFTRG_DNEN_Pos) +#define PWM_OVFTRG_MUX_Pos 2 //Triggerһ·0 trig[0] 1 trig[1] 2 trig[2] ... 7 trig[7] +#define PWM_OVFTRG_MUX_Msk (0x07 << PWM_OVFTRG_MUX_Pos) + +#define PWM_CMPTRG_CMP_Pos 0 //ֵ˱ȽֵʱTriggerź +#define PWM_CMPTRG_CMP_Msk (0xFFFF<IF.HALF жϱ־λ +#define DMA_NDT_HALF_Msk (0xFFFF << DMA_NDT_HALF_Pos) + + + + +typedef struct { + __IO uint32_t CR; + + __IO uint32_t DCR; //Device Configuration Register + + __IO uint32_t SR; + + __IO uint32_t FCR; //Flag Clear Register + + __IO uint32_t DLR; //Data Length Register + //Number of data to be retrieved in indirect and status-polling modes + __IO uint32_t CCR; //Communication Configuration Register + + __IO uint32_t AR; + + __IO uint32_t ABR; //Alternate Bytes Registers + + union { + __IO uint32_t DRW; + + __IO uint16_t DRH; + + __IO uint8_t DRB; + }; + + __IO uint32_t PSMSK; //Polling Status Mask + + __IO uint32_t PSMAT; //Polling Status Match + + __IO uint32_t PSITV; //Polling Status Interval + + uint32_t RESERVED[4]; + + __IO uint32_t SSHIFT; //Sample Shift in System clock cycles, ʵʵIJӳʱǴ˼Ĵ CR.SSHIFT 趨ӳٵۼ +} QSPI_TypeDef; + + +#define QSPI_CR_EN_Pos 0 +#define QSPI_CR_EN_Msk (0x01 << QSPI_CR_EN_Pos) +#define QSPI_CR_ABORT_Pos 1 +#define QSPI_CR_ABORT_Msk (0x01 << QSPI_CR_ABORT_Pos) +#define QSPI_CR_DMAEN_Pos 2 +#define QSPI_CR_DMAEN_Msk (0x01 << QSPI_CR_DMAEN_Pos) +#define QSPI_CR_SSHIFT_Pos 4 //Sample Shift in QSPI clock cycle, 0 No shift 1 1/2 cycle shift +#define QSPI_CR_SSHIFT_Msk (0x01 << QSPI_CR_SSHIFT_Pos) +#define QSPI_CR_BIDI_Pos 5 //˫ģʽ0 IO0IO1 1 IO0 +#define QSPI_CR_BIDI_Msk (0x01 << QSPI_CR_BIDI_Pos) +#define QSPI_CR_FFTHR_Pos 8 //FIFO Thresholdindirect read ģʽ£FIFO ݸ CR.FFTHR+1 ʱSR.FFTHR λ + // indirect write ģʽ£FIFO пλ CR.FFTHR+1 ʱSR.FFTHR λ +#define QSPI_CR_FFTHR_Msk (0x0F << QSPI_CR_FFTHR_Pos) +#define QSPI_CR_ERRIE_Pos 16 //Transfer Error Interrupt Enable +#define QSPI_CR_ERRIE_Msk (0x01 << QSPI_CR_ERRIE_Pos) +#define QSPI_CR_DONEIE_Pos 17 //Transfer Done/Complete Interrupt Enable +#define QSPI_CR_DONEIE_Msk (0x01 << QSPI_CR_DONEIE_Pos) +#define QSPI_CR_FFTHRIE_Pos 18 //FIFO Threshold Interrupt Enable +#define QSPI_CR_FFTHRIE_Msk (0x01 << QSPI_CR_FFTHRIE_Pos) +#define QSPI_CR_PSMATIE_Pos 19 //Polling Status Match Interrupt Enable +#define QSPI_CR_PSMATIE_Msk (0x01 << QSPI_CR_PSMATIE_Pos) +#define QSPI_CR_PSSTPMOD_Pos 22 //Polling Status Stop Mode0 always polling until abort or QSPI disabled 1 stop polling as soon as match +#define QSPI_CR_PSSTPMOD_Msk (0x01 << QSPI_CR_PSSTPMOD_Pos) +#define QSPI_CR_PSMATMOD_Pos 23 //Polling Status Match Mode0 ANDmatch when all unmasked bits received from Flash match PSMAT register 1 OR +#define QSPI_CR_PSMATMOD_Msk (0x01 << QSPI_CR_PSMATMOD_Pos) +#define QSPI_CR_CLKDIV_Pos 24 //QSPI_SCLK = HCLK / (CR.CLKDIV + 1) +#define QSPI_CR_CLKDIV_Msk (0xFFu<< QSPI_CR_CLKDIV_Pos) + +#define QSPI_DCR_CLKMOD_Pos 0 //0 Mode 0 1 Mode 3 +#define QSPI_DCR_CLKMOD_Msk (0x01 << QSPI_DCR_CLKMOD_Pos) +#define QSPI_DCR_CSHIGH_Pos 8 //nCS stay high for at least DCR.CSHIGH+1 cycles between Flash memory commands +#define QSPI_DCR_CSHIGH_Msk (0x07 << QSPI_DCR_CSHIGH_Pos) +#define QSPI_DCR_FLSIZE_Pos 16 //Flash Size = pow(2, DCR.FLSIZE+1) +#define QSPI_DCR_FLSIZE_Msk (0x1F << QSPI_DCR_FLSIZE_Pos) + +#define QSPI_SR_ERR_Pos 0 //Transfer Error Flag +#define QSPI_SR_ERR_Msk (0x01 << QSPI_SR_ERR_Pos) +#define QSPI_SR_DONE_Pos 1 //Transfer Done/Complete Flag +#define QSPI_SR_DONE_Msk (0x01 << QSPI_SR_DONE_Pos) +#define QSPI_SR_FFTHR_Pos 2 //FIFO Threshold reached Flag +#define QSPI_SR_FFTHR_Msk (0x01 << QSPI_SR_FFTHR_Pos) +#define QSPI_SR_PSMAT_Pos 3 //Polling Status Match Flag +#define QSPI_SR_PSMAT_Msk (0x01 << QSPI_SR_PSMAT_Pos) +#define QSPI_SR_TO_Pos 4 //Time-Out +#define QSPI_SR_TO_Msk (0x01 << QSPI_SR_TO_Pos) +#define QSPI_SR_BUSY_Pos 5 //Set when operation is on going, Clear when operation done and FIFO emtpy +#define QSPI_SR_BUSY_Msk (0x01 << QSPI_SR_BUSY_Pos) +#define QSPI_SR_FFLVL_Pos 8 //FIFO Level +#define QSPI_SR_FFLVL_Msk (0x1F << QSPI_SR_FFLVL_Pos) + +#define QSPI_FCR_ERR_Pos 0 +#define QSPI_FCR_ERR_Msk (0x01 << QSPI_FCR_ERR_Pos) +#define QSPI_FCR_DONE_Pos 1 +#define QSPI_FCR_DONE_Msk (0x01 << QSPI_FCR_DONE_Pos) +#define QSPI_FCR_PSMAT_Pos 3 +#define QSPI_FCR_PSMAT_Msk (0x01 << QSPI_FCR_PSMAT_Pos) + +#define QSPI_CCR_CODE_Pos 0 //Insruction Code +#define QSPI_CCR_CODE_Msk (0xFF << QSPI_CCR_CODE_Pos) +#define QSPI_CCR_IMODE_Pos 8 //0 No instruction 1 Instruction on D0 2 on D0-1 3 on D0-3 +#define QSPI_CCR_IMODE_Msk (0x03 << QSPI_CCR_IMODE_Pos) +#define QSPI_CCR_AMODE_Pos 10 //0 No address 1 Address on D0 2 on D0-1 3 on D0-3 +#define QSPI_CCR_AMODE_Msk (0x03 << QSPI_CCR_AMODE_Pos) +#define QSPI_CCR_ASIZE_Pos 12 //Address size, 0 8-bit 1 16-bit 2 24-bit 3 32-bit +#define QSPI_CCR_ASIZE_Msk (0x03 << QSPI_CCR_ASIZE_Pos) +#define QSPI_CCR_ABMODE_Pos 14 //0 No alternate bytes 1 Alternate bytes on D0 2 on D0-1 3 on D0-3 +#define QSPI_CCR_ABMODE_Msk (0x03 << QSPI_CCR_ABMODE_Pos) +#define QSPI_CCR_ABSIZE_Pos 16 //Alternate bytes size, 0 8-bit 1 16-bit 2 24-bit 3 32-bit +#define QSPI_CCR_ABSIZE_Msk (0x03 << QSPI_CCR_ABSIZE_Pos) +#define QSPI_CCR_DUMMY_Pos 18 //Number of dummy cycles +#define QSPI_CCR_DUMMY_Msk (0x1F << QSPI_CCR_DUMMY_Pos) +#define QSPI_CCR_DMODE_Pos 24 //0 No Data 1 Data on D0 2 on D0-1 3 on D0-3 +#define QSPI_CCR_DMODE_Msk (0x03 << QSPI_CCR_DMODE_Pos) +#define QSPI_CCR_MODE_Pos 26 //0 Indirect write mode 1 Indirect read mode 2 Automatic polling mode +#define QSPI_CCR_MODE_Msk (0x03 << QSPI_CCR_MODE_Pos) +#define QSPI_CCR_SIOO_Pos 28 //Send Instruction Only Once +#define QSPI_CCR_SIOO_Msk (0x01 << QSPI_CCR_SIOO_Pos) + +#define QSPI_SSHIFT_CYCLE_Pos 0 //Sample Shift Cycle Count in System clock +#define QSPI_SSHIFT_CYCLE_Msk (0x0F << QSPI_SSHIFT_CYCLE_Pos) +#define QSPI_SSHIFT_SPACE_Pos 4 // RX FIFO ʣ SPACE λʱǰͣգֹ޷ʱͣµ FIFO +#define QSPI_SSHIFT_SPACE_Msk (0x0F << QSPI_SSHIFT_SPACE_Pos) + + + + +typedef struct { + __IO uint32_t CR; //Control Register + + __O uint32_t CMD; //Command Register + + __I uint32_t SR; //Status Register + + __IO uint32_t IF; //Interrupt Flagȡ + + __IO uint32_t IE; //Interrupt Enable + + __IO uint32_t BT2; + + __IO uint32_t BT0; //Bit Time Register 0 + + __IO uint32_t BT1; //Bit Time Register 1 + + uint32_t RESERVED; + + __IO uint32_t AFM; //Acceptance Filter Mode + + __IO uint32_t AFE; //Acceptance Filter Enable + + __I uint32_t ALC; //Arbitration Lost Capture, ٲöʧ׽ + + __I uint32_t ECC; //Error code capture, 벶׽ + + __IO uint32_t EWLIM; //Error Warning Limit, 󱨾 + + __IO uint32_t RXERR; //RX + + __IO uint32_t TXERR; //TX + + struct { + __IO uint32_t INFO; //ʽBufferдʷBuffer + + __IO uint32_t DATA[12]; + } FRAME; + + __I uint32_t RMCNT; //Receive Message Count + + uint32_t RESERVED2[162]; + + __IO uint32_t ACR[16]; //Acceptance Check Register, ռĴ + + uint32_t RESERVED3[16]; + + __IO uint32_t AMR[16]; //Acceptance Mask Register, μĴӦλд0IDռĴƥ +} CAN_TypeDef; + + +#define CAN_CR_RST_Pos 0 +#define CAN_CR_RST_Msk (0x01 << CAN_CR_RST_Pos) +#define CAN_CR_LOM_Pos 1 //Listen Only Mode +#define CAN_CR_LOM_Msk (0x01 << CAN_CR_LOM_Pos) +#define CAN_CR_STM_Pos 2 //Self Test Mode, ģʽ¼ʹûӦCANҲԳɹ +#define CAN_CR_STM_Msk (0x01 << CAN_CR_STM_Pos) +#define CAN_CR_SLEEP_Pos 4 //д1˯ģʽ߻жʱѲԶλ +#define CAN_CR_SLEEP_Msk (0x01 << CAN_CR_SLEEP_Pos) + +#define CAN_CMD_TXREQ_Pos 0 //Transmission Request +#define CAN_CMD_TXREQ_Msk (0x01 << CAN_CMD_TXREQ_Pos) +#define CAN_CMD_ABTTX_Pos 1 //Abort Transmission +#define CAN_CMD_ABTTX_Msk (0x01 << CAN_CMD_ABTTX_Pos) +#define CAN_CMD_RRB_Pos 2 //Release Receive Buffer +#define CAN_CMD_RRB_Msk (0x01 << CAN_CMD_RRB_Pos) +#define CAN_CMD_CLROV_Pos 3 //Clear Data Overrun +#define CAN_CMD_CLROV_Msk (0x01 << CAN_CMD_CLROV_Pos) +#define CAN_CMD_SRR_Pos 4 //Self Reception Request +#define CAN_CMD_SRR_Msk (0x01 << CAN_CMD_SRR_Pos) + +#define CAN_SR_RXDA_Pos 0 //Receive Data AvailableFIFOϢԶȡ +#define CAN_SR_RXDA_Msk (0x01 << CAN_SR_RXDA_Pos) +#define CAN_SR_RXOV_Pos 1 //Receive FIFO Overrun½յϢڽFIFO +#define CAN_SR_RXOV_Msk (0x01 << CAN_SR_RXOV_Pos) +#define CAN_SR_TXBR_Pos 2 //Transmit Buffer Release0 ڴǰķͣڲдµϢ 1 дµϢ +#define CAN_SR_TXBR_Msk (0x01 << CAN_SR_TXBR_Pos) +#define CAN_SR_TXOK_Pos 3 //Transmit OKsuccessfully completed +#define CAN_SR_TXOK_Msk (0x01 << CAN_SR_TXOK_Pos) +#define CAN_SR_RXBUSY_Pos 4 //Receive Busyڽ +#define CAN_SR_RXBUSY_Msk (0x01 << CAN_SR_RXBUSY_Pos) +#define CAN_SR_TXBUSY_Pos 5 //Transmit Busyڷ +#define CAN_SR_TXBUSY_Msk (0x01 << CAN_SR_TXBUSY_Pos) +#define CAN_SR_ERRWARN_Pos 6 //1 һﵽ Warning Limit +#define CAN_SR_ERRWARN_Msk (0x01 << CAN_SR_ERRWARN_Pos) +#define CAN_SR_BUSOFF_Pos 7 //1 CAN ߹ر״̬ûв뵽߻ +#define CAN_SR_BUSOFF_Msk (0x01 << CAN_SR_BUSOFF_Pos) + +#define CAN_IF_RXDA_Pos 0 //IF.RXDA = SR.RXDA & IE.RXDA +#define CAN_IF_RXDA_Msk (0x01 << CAN_IF_RXDA_Pos) +#define CAN_IF_TXBR_Pos 1 //IE.TXBR=1ʱSR.TXBR01λλ +#define CAN_IF_TXBR_Msk (0x01 << CAN_IF_TXBR_Pos) +#define CAN_IF_ERRWARN_Pos 2 //IE.ERRWARN=1ʱSR.ERRWARNSR.BUSOFF 0-to-1 1-to-0λλ +#define CAN_IF_ERRWARN_Msk (0x01 << CAN_IF_ERRWARN_Pos) +#define CAN_IF_RXOV_Pos 3 //IF.RXOV = SR.RXOV & IE.RXOV +#define CAN_IF_RXOV_Msk (0x01 << CAN_IF_RXOV_Pos) +#define CAN_IF_WKUP_Pos 4 //IE.WKUP=1ʱ˯ģʽµCAN⵽߻ʱӲλ +#define CAN_IF_WKUP_Msk (0x01 << CAN_IF_WKUP_Pos) +#define CAN_IF_ERRPASS_Pos 5 // +#define CAN_IF_ERRPASS_Msk (0x01 << CAN_IF_ERRPASS_Pos) +#define CAN_IF_ARBLOST_Pos 6 //Arbitration LostIE.ARBLOST=1ʱCANʧٲñɽշʱӲλ +#define CAN_IF_ARBLOST_Msk (0x01 << CAN_IF_ARBLOST_Pos) +#define CAN_IF_BUSERR_Pos 7 //IE.BUSERR=1ʱCAN⵽ߴʱӲλ +#define CAN_IF_BUSERR_Msk (0x01 << CAN_IF_BUSERR_Pos) + +#define CAN_IE_RXDA_Pos 0 +#define CAN_IE_RXDA_Msk (0x01 << CAN_IE_RXDA_Pos) +#define CAN_IE_TXBR_Pos 1 +#define CAN_IE_TXBR_Msk (0x01 << CAN_IE_TXBR_Pos) +#define CAN_IE_ERRWARN_Pos 2 +#define CAN_IE_ERRWARN_Msk (0x01 << CAN_IE_ERRWARN_Pos) +#define CAN_IE_RXOV_Pos 3 +#define CAN_IE_RXOV_Msk (0x01 << CAN_IE_RXOV_Pos) +#define CAN_IE_WKUP_Pos 4 +#define CAN_IE_WKUP_Msk (0x01 << CAN_IE_WKUP_Pos) +#define CAN_IE_ERRPASS_Pos 5 +#define CAN_IE_ERRPASS_Msk (0x01 << CAN_IE_ERRPASS_Pos) +#define CAN_IE_ARBLOST_Pos 6 +#define CAN_IE_ARBLOST_Msk (0x01 << CAN_IE_ARBLOST_Pos) +#define CAN_IE_BUSERR_Pos 7 +#define CAN_IE_BUSERR_Msk (0x01 << CAN_IE_BUSERR_Pos) + +#define CAN_BT2_BRP_Pos 0 +#define CAN_BT2_BRP_Msk (0x0F << CAN_BT2_BRP_Pos) + +#define CAN_BT0_BRP_Pos 0 //Baud Rate PrescalerCANʱ䵥λ=2*Tsysclk*((BT2.BRP<<6) + BT0.BRP + 1) +#define CAN_BT0_BRP_Msk (0x3F << CAN_BT0_BRP_Pos) +#define CAN_BT0_SJW_Pos 6 //Synchronization Jump Width +#define CAN_BT0_SJW_Msk (0x03 << CAN_BT0_SJW_Pos) + +#define CAN_BT1_TSEG1_Pos 0 //t_tseg1 = CANʱ䵥λ * (TSEG1+1) +#define CAN_BT1_TSEG1_Msk (0x0F << CAN_BT1_TSEG1_Pos) +#define CAN_BT1_TSEG2_Pos 4 //t_tseg2 = CANʱ䵥λ * (TSEG2+1) +#define CAN_BT1_TSEG2_Msk (0x07 << CAN_BT1_TSEG2_Pos) +#define CAN_BT1_SAM_Pos 7 // 0: sampled once 1: sampled three times +#define CAN_BT1_SAM_Msk (0x01 << CAN_BT1_SAM_Pos) + +#define CAN_ECC_SEGCODE_Pos 0 //Segment Code +#define CAN_ECC_SEGCODE_Msk (0x1F << CAN_ECC_SEGCODE_Pos) +#define CAN_ECC_DIR_Pos 5 //0 error occurred during transmission 1 during reception +#define CAN_ECC_DIR_Msk (0x01 << CAN_ECC_DIR_Pos) +#define CAN_ECC_ERRCODE_Pos 6 //Error Code0 Bit error 1 Form error 2 Stuff error 3 other error +#define CAN_ECC_ERRCODE_Msk (0x03 << CAN_ECC_ERRCODE_Pos) + +#define CAN_INFO_DLC_Pos 0 //Data Length Control +#define CAN_INFO_DLC_Msk (0x0F << CAN_INFO_DLC_Pos) +#define CAN_INFO_RTR_Pos 6 //Remote Frame1 Զ֡ 0 ֡ +#define CAN_INFO_RTR_Msk (0x01 << CAN_INFO_RTR_Pos) +#define CAN_INFO_FF_Pos 7 //Frame Format0 ׼֡ʽ 1 չ֡ʽ +#define CAN_INFO_FF_Msk (0x01 << CAN_INFO_FF_Pos) + + + + +typedef struct { + __IO uint32_t CR; + + __IO uint32_t SR; + + __IO uint32_t IE; //[0] жʹ + + uint32_t RESERVED; + + __IO uint32_t DIVIDEND; // + + __IO uint32_t DIVISOR; // + + __IO uint32_t QUO; // + + __IO uint32_t REMAIN; // + + __IO uint32_t RADICAND; // + + __IO uint32_t ROOT; //ƽ16λΪС֣16λΪ +} DIV_TypeDef; + + +#define DIV_CR_DIVGO_Pos 0 //д1㣬ɺԶ +#define DIV_CR_DIVGO_Msk (0x01 << DIV_CR_DIVGO_Pos) +#define DIV_CR_DIVSIGN_Pos 1 //0 зų 1 ޷ų +#define DIV_CR_DIVSIGN_Msk (0x01 << DIV_CR_DIVSIGN_Pos) +#define DIV_CR_ROOTGO_Pos 8 //д1ƽ㣬ɺԶ +#define DIV_CR_ROOTGO_Msk (0x01 << DIV_CR_ROOTGO_Pos) +#define DIV_CR_ROOTMOD_Pos 9 //ƽģʽ0 Ϊ 1 С +#define DIV_CR_ROOTMOD_Msk (0x01 << DIV_CR_ROOTMOD_Pos) + +#define DIV_SR_DIVEND_Pos 0 //ɱ־д1 +#define DIV_SR_DIVEND_Msk (0x01 << DIV_SR_DIVEND_Pos) +#define DIV_SR_DIVBUSY_Pos 1 //1 +#define DIV_SR_DIVBUSY_Msk (0x01 << DIV_SR_DIVBUSY_Pos) +#define DIV_SR_ROOTENDI_Pos 8 //ɱ־д1 +#define DIV_SR_ROOTENDI_Msk (0x01 << DIV_SR_ROOTENDI_Pos) +#define DIV_SR_ROOTENDF_Pos 9 //Сɱ־д1 +#define DIV_SR_ROOTENDF_Msk (0x01 << DIV_SR_ROOTENDF_Pos) +#define DIV_SR_ROOTBUSY_Pos 10 //1 +#define DIV_SR_ROOTBUSY_Msk (0x01 << DIV_SR_ROOTBUSY_Pos) + + + + +typedef struct { + __IO uint32_t CR; + + __O uint32_t DATAIN; + + __IO uint32_t INIVAL; //CR.ENд1ʱINIVALеֵдRESULT + + __I uint32_t RESULT; +} CRC_TypeDef; + + +#define CRC_CR_EN_Pos 0 +#define CRC_CR_EN_Msk (0x01 << CRC_CR_EN_Pos) +#define CRC_CR_IREV_Pos 1 //Ƿת0 bit˳򲻱 1 bit˳ȫת 2 bit˳ֽڷת 3 ֽ˳ת +#define CRC_CR_IREV_Msk (0x03 << CRC_CR_IREV_Pos) +#define CRC_CR_INOT_Pos 3 //Ƿȡ +#define CRC_CR_INOT_Msk (0x01 << CRC_CR_INOT_Pos) +#define CRC_CR_OREV_Pos 4 //Ƿת0 bit˳򲻱 1 bit˳ȫת 2 bit˳ֽڷת 3 ֽ˳ת +#define CRC_CR_OREV_Msk (0x03 << CRC_CR_OREV_Pos) +#define CRC_CR_ONOT_Pos 6 //Ƿȡ +#define CRC_CR_ONOT_Msk (0x01 << CRC_CR_ONOT_Pos) +#define CRC_CR_POLY_Pos 7 //ʽѡ0 x^16+x^12+x^5+1 1 x^8+x^2+x+1 2 x^16+x^15+x^2+1 3 x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 +#define CRC_CR_POLY_Msk (0x03 << CRC_CR_POLY_Pos) +#define CRC_CR_IBIT_Pos 9 //Чλ 0 32λ 1 16λ 2 8λ +#define CRC_CR_IBIT_Msk (0x03 << CRC_CR_IBIT_Pos) + + + + +typedef struct { + uint32_t RESERVED[2]; + + __IO uint32_t SR; + + __IO uint32_t CR; + + union { + __IO uint8_t IRB; + + __IO uint16_t IRH; + + __IO uint32_t RESERVED2; + }; + + union { + __IO uint8_t DRB; + + __IO uint16_t DRH; + + __IO uint32_t RESERVED3; + }; +} MPU_TypeDef; + + +#define MPU_SR_BUSY_Pos 0 +#define MPU_SR_BUSY_Msk (0x01 << MPU_SR_BUSY_Pos) +#define MPU_SR_DMAEN_Pos 1 +#define MPU_SR_DMAEN_Msk (0x01 << MPU_SR_DMAEN_Pos) +#define MPU_SR_ENDIAN_Pos 2 //0 С 1 +#define MPU_SR_ENDIAN_Msk (0x01 << MPU_SR_ENDIAN_Pos) + +#define MPU_CR_RCS1_0_Pos 0 //ʱCSص½ʱ0 1ʱ +#define MPU_CR_RCS1_0_Msk (0x1F << MPU_CR_RCS1_0_Pos) +#define MPU_CR_RDHOLD_Pos 5 //RD͵ƽʱ +#define MPU_CR_RDHOLD_Msk (0x1F << MPU_CR_RDHOLD_Pos) +#define MPU_CR_WCS1_0_Pos 10 //дʱCSص½ʱ +#define MPU_CR_WCS1_0_Msk (0x0F << MPU_CR_WCS1_0_Pos) +#define MPU_CR_WR1CS1_Pos 14 //WRصCSʱ +#define MPU_CR_WR1CS1_Msk (0x03 << MPU_CR_WR1CS1_Pos) +#define MPU_CR_WRHOLD_Pos 16 //WR͵ƽʱ +#define MPU_CR_WRHOLD_Msk (0x0F << MPU_CR_WRHOLD_Pos) +#define MPU_CR_CS0WR0_Pos 20 //CS½صWR½ʱ +#define MPU_CR_CS0WR0_Msk (0x03 << MPU_CR_CS0WR0_Pos) + + + + +typedef struct { + __IO uint32_t DATA; + + __IO uint32_t ADDR; + + __IO uint32_t ERASE; + + __IO uint32_t CACHE; + + __IO uint32_t CFG0; + + __IO uint32_t CFG1; //д 0x5A5A5A5A0xA5A5A5A5 readonlyдֵָ readonly + + __IO uint32_t CFG2; + + __IO uint32_t CFG3; + + __IO uint32_t CFG4; + + __IO uint32_t STAT; + + __IO uint32_t REMAP; +} FMC_TypeDef; + + +#define FMC_ERASE_ADDR_Pos 0 //512 Byte per Page +#define FMC_ERASE_ADDR_Msk (0x1FFFF<< FMC_ERASE_ADDR_Pos) +#define FMC_ERASE_REQ_Pos 24 +#define FMC_ERASE_REQ_Msk (0xFFu<< FMC_ERASE_REQ_Pos) + +#define FMC_CACHE_CEN_Pos 0 //Cache Enable +#define FMC_CACHE_CEN_Msk (0x01 << FMC_CACHE_CEN_Pos) +#define FMC_CACHE_CPEN_Pos 1 //Cache Predict Enable +#define FMC_CACHE_CPEN_Msk (0x01 << FMC_CACHE_CPEN_Pos) +#define FMC_CACHE_CCLR_Pos 31 //Cache ClearԶ +#define FMC_CACHE_CCLR_Msk (0x01u<< FMC_CACHE_CCLR_Pos) + +#define FMC_CFG0_WREN_Pos 9 +#define FMC_CFG0_WREN_Msk (0x01 << FMC_CFG0_WREN_Pos) + +#define FMC_STAT_ERASEBUSY_Pos 0 +#define FMC_STAT_ERASEBUSY_Msk (0x01 << FMC_STAT_ERASEBUSY_Pos) +#define FMC_STAT_PROGBUSY_Pos 1 +#define FMC_STAT_PROGBUSY_Msk (0x01 << FMC_STAT_PROGBUSY_Pos) +#define FMC_STAT_READBUSY_Pos 2 +#define FMC_STAT_READBUSY_Msk (0x01 << FMC_STAT_READBUSY_Pos) +#define FMC_STAT_FIFOEMPTY_Pos 3 //Write FIFO Empty +#define FMC_STAT_FIFOEMPTY_Msk (0x01 << FMC_STAT_FIFOEMPTY_Pos) +#define FMC_STAT_FIFOFULL_Pos 4 //Write FIFO Full +#define FMC_STAT_FIFOFULL_Msk (0x01 << FMC_STAT_FIFOFULL_Pos) +#define FMC_STAT_READONLY_Pos 7 +#define FMC_STAT_READONLY_Msk (0x01 << FMC_STAT_READONLY_Pos) +#define FMC_STAT_INITDONE_Pos 30 +#define FMC_STAT_INITDONE_Msk (0x01 << FMC_STAT_INITDONE_Pos) +#define FMC_STAT_IDLE_Pos 31 +#define FMC_STAT_IDLE_Msk (0x01u<< FMC_STAT_IDLE_Pos) + +#define FMC_REMAP_ON_Pos 0 +#define FMC_REMAP_ON_Msk (0x01 << FMC_REMAP_ON_Pos) +#define FMC_REMAP_OFFSET_Pos 1 //0x000-0x8002Kַķӳ䵽2K*OFFSET-2K*(OFFSET+1)ַ +#define FMC_REMAP_OFFSET_Msk (0x3F << FMC_REMAP_OFFSET_Pos) + + + + +typedef struct { + __IO uint32_t RSTVAL; //ֵʱλ + + __IO uint32_t INTVAL; //ֵʱж + + __IO uint32_t CR; + + __IO uint32_t IF; //[0] жϱ־д1 + + __IO uint32_t FEED; //д0x55ι +} WDT_TypeDef; + + +#define WDT_CR_EN_Pos 0 +#define WDT_CR_EN_Msk (0x01 << WDT_CR_EN_Pos) +#define WDT_CR_RSTEN_Pos 1 +#define WDT_CR_RSTEN_Msk (0x01 << WDT_CR_RSTEN_Pos) +#define WDT_CR_INTEN_Pos 2 +#define WDT_CR_INTEN_Msk (0x01 << WDT_CR_INTEN_Pos) +#define WDT_CR_WINEN_Pos 3 //Window function enable +#define WDT_CR_WINEN_Msk (0x01 << WDT_CR_WINEN_Pos) +#define WDT_CR_CLKDIV_Pos 8 //WDTʱӷƵֵ = pow(2, CLKDIV+1) +#define WDT_CR_CLKDIV_Msk (0x0F << WDT_CR_CLKDIV_Pos) + + + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +#define RAM_BASE 0x20000000 +#define AHB_BASE 0x40000000 +#define APB1_BASE 0x40040000 +#define APB2_BASE 0x400A0000 + + +/* AHB Peripheral memory map */ +#define SYS_BASE (AHB_BASE + 0x00000) + +#define DMA_BASE (AHB_BASE + 0x00800) + +#define QSPI0_BASE (AHB_BASE + 0x01800) + +#define CRC_BASE (AHB_BASE + 0x02800) + +#define DIV_BASE (AHB_BASE + 0x03000) + +#define GPIOA_BASE (AHB_BASE + 0x03800) +#define GPIOB_BASE (AHB_BASE + 0x04000) +#define GPIOC_BASE (AHB_BASE + 0x04800) + +#define MPU_BASE (AHB_BASE + 0x05000) + + +/* APB1 Peripheral memory map */ +#define UART0_BASE (APB1_BASE + 0x0000) +#define UART1_BASE (APB1_BASE + 0x0800) + +#define QEI_BASE (APB1_BASE + 0x1000) + +#define SPI0_BASE (APB1_BASE + 0x1800) + +#define I2C0_BASE (APB1_BASE + 0x2000) + +#define CAN0_BASE (APB1_BASE + 0x2800) + +#define PWM0_BASE (APB1_BASE + 0x3000) +#define PWM1_BASE (APB1_BASE + 0x3080) +#define PWMG_BASE (APB1_BASE + 0x3400) + +#define TIMR0_BASE (APB1_BASE + 0x3800) +#define TIMR1_BASE (APB1_BASE + 0x3840) +#define TIMR2_BASE (APB1_BASE + 0x3880) +#define TIMRG_BASE (APB1_BASE + 0x3C00) + +#define BTIMR0_BASE (APB1_BASE + 0x4000) +#define BTIMR1_BASE (APB1_BASE + 0x4040) +#define BTIMR2_BASE (APB1_BASE + 0x4080) +#define BTIMR3_BASE (APB1_BASE + 0x40C0) +#define BTIMRG_BASE (APB1_BASE + 0x4400) + +#define ADC0_BASE (APB1_BASE + 0x4800) +#define ADC1_BASE (APB1_BASE + 0x4900) + +#define FMC_BASE (APB1_BASE + 0x5000) //Flash Memory Controller + +#define PORTA_BASE (APB1_BASE + 0x6000) +#define PORTB_BASE (APB1_BASE + 0x6010) +#define PORTC_BASE (APB1_BASE + 0x6020) + +#define WDT_BASE (APB1_BASE + 0x6800) + +#define USART0_BASE (APB1_BASE + 0x7000) + + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define SYS ((SYS_TypeDef *) SYS_BASE) + +#define PORTA ((PORT_TypeDef *) PORTA_BASE) +#define PORTB ((PORT_TypeDef *) PORTB_BASE) +#define PORTC ((PORT_TypeDef *) PORTC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) + +#define TIMR0 ((TIMR_TypeDef *) TIMR0_BASE) +#define TIMR1 ((TIMR_TypeDef *) TIMR1_BASE) +#define TIMR2 ((TIMR_TypeDef *) TIMR2_BASE) +#define TIMRG ((TIMRG_TypeDef*) TIMRG_BASE) + +#define BTIMR0 ((TIMR_TypeDef *) BTIMR0_BASE) +#define BTIMR1 ((TIMR_TypeDef *) BTIMR1_BASE) +#define BTIMR2 ((TIMR_TypeDef *) BTIMR2_BASE) +#define BTIMR3 ((TIMR_TypeDef *) BTIMR3_BASE) +#define BTIMRG ((TIMRG_TypeDef*) BTIMRG_BASE) + +#define UART0 ((UART_TypeDef *) UART0_BASE) +#define UART1 ((UART_TypeDef *) UART1_BASE) + +#define USART0 ((USART_TypeDef *)USART0_BASE) + +#define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) + +#define SPI0 ((SPI_TypeDef *) SPI0_BASE) + +#define I2C0 ((I2C_TypeDef *) I2C0_BASE) + +#define CAN0 ((CAN_TypeDef *) CAN0_BASE) + +#define ADC0 ((ADC_TypeDef *) ADC0_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) + +#define PWM0 ((PWM_TypeDef *) PWM0_BASE) +#define PWM1 ((PWM_TypeDef *) PWM1_BASE) +#define PWMG ((PWMG_TypeDef *) PWMG_BASE) + +#define DIV ((DIV_TypeDef *) DIV_BASE) + +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define DMA ((DMA_TypeDef *) DMA_BASE) + +#define MPU ((MPU_TypeDef *) MPU_BASE) + +#define FMC ((FMC_TypeDef *) FMC_BASE) + +#define WDT ((WDT_TypeDef *) WDT_BASE) + +#define QEI ((QEI_TypeDef *) QEI_BASE) + + +#include "SWM221_port.h" +#include "SWM221_gpio.h" +#include "SWM221_exti.h" +#include "SWM221_timr.h" +#include "SWM221_uart.h" +#include "SWM221_spi.h" +#include "SWM221_i2c.h" +#include "SWM221_pwm.h" +#include "SWM221_adc.h" +#include "SWM221_dma.h" +#include "SWM221_mpu.h" +#include "SWM221_can.h" +#include "SWM221_div.h" +#include "SWM221_crc.h" +#include "SWM221_wdt.h" +#include "SWM221_qei.h" +#include "SWM221_qspi.h" +#include "SWM221_usart.h" +#include "SWM221_flash.h" +#include "SWM221_iofilt.h" + + + +#ifdef SW_LOG_RTT +#define log_printf(...) SEGGER_RTT_printf(0, __VA_ARGS__) +#else +#define log_printf(...) printf(__VA_ARGS__) +#endif + + +#ifndef SW_LOG_LEVEL +#define SW_LOG_LEVEL 0 +#endif + +#if (SW_LOG_LEVEL > 0) +#define SW_LOG_ERR(...) { \ + log_printf("ERROR: "); \ + log_printf(__VA_ARGS__); \ + log_printf("\n"); \ + } + +#if (SW_LOG_LEVEL > 1) +#define SW_LOG_WARN(...) { \ + log_printf("WARN : "); \ + log_printf(__VA_ARGS__); \ + log_printf("\n"); \ + } + +#if (SW_LOG_LEVEL > 2) +#define SW_LOG_INFO(...) { \ + log_printf("INFO : "); \ + log_printf(__VA_ARGS__); \ + log_printf("\n"); \ + } +#else +#define SW_LOG_INFO(...) +#endif + +#else +#define SW_LOG_WARN(...) +#define SW_LOG_INFO(...) +#endif + +#else +#define SW_LOG_ERR(...) +#define SW_LOG_WARN(...) +#define SW_LOG_INFO(...) +#endif + + +#endif //__SWM221_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/DeviceSupport/startup/arm/startup_SWM221.s b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/DeviceSupport/startup/arm/startup_SWM221.s new file mode 100644 index 0000000..7aac600 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/DeviceSupport/startup/arm/startup_SWM221.s @@ -0,0 +1,331 @@ +;****************************************************************************************************************************************** +; ļ: startup_SWM221.s +; ˵: SWM221Ƭļ +; ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +; ע: +; 汾: V1.0.0 2016130 +; ¼: +; +; +;****************************************************************************************************************************************** +; @attention +; +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +; REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +; FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +; OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +; -ECTION WITH THEIR PRODUCTS. +; +; COPYRIGHT 2012 Synwit Technology +;****************************************************************************************************************************************** + + +; Amount of memory (in bytes) allocated for Stack +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Amount of memory (in bytes) allocated for Heap +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, CODE, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UART0_Handler + DCD TIMR0_Handler + DCD CAN0_Handler + DCD UART1_Handler + DCD PWM1_Handler + DCD TIMR1_Handler + DCD HALL_Handler + DCD PWM0_Handler + DCD QSPI0_Handler + DCD PWMBRK_Handler + DCD USART0_Handler + DCD WDT_Handler + DCD I2C0_Handler + DCD XTALSTOP_Handler + DCD ADC_Handler + DCD ACMP_Handler + DCD BTIMR0_Handler + DCD BTIMR1_Handler + DCD BTIMR2_Handler + DCD BTIMR3_Handler + DCD GPIOA_Handler + DCD GPIOB_Handler + DCD GPIOC_Handler + DCD GPIOA0_GPIOC0_Handler + DCD GPIOA1_GPIOC1_Handler + DCD GPIOA2_GPIOC2_MPU_Handler + DCD GPIOA3_GPIOC3_PVD_Handler + DCD GPIOB0_GPIOA8_TIMR2_Handler + DCD GPIOB1_GPIOA9_DMA_Handler + DCD GPIOB2_GPIOA10_DIV_Handler + DCD GPIOB3_GPIOA11_SPI0_Handler + DCD GPIOB4_GPIOB10_QEI_Handler + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + + + ;AREA |.text|, CODE, READONLY + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +UART0_Handler PROC + EXPORT UART0_Handler [WEAK] + B . + ENDP + +TIMR0_Handler PROC + EXPORT TIMR0_Handler [WEAK] + B . + ENDP + +CAN0_Handler PROC + EXPORT CAN0_Handler [WEAK] + B . + ENDP + +UART1_Handler PROC + EXPORT UART1_Handler [WEAK] + B . + ENDP + +PWM1_Handler PROC + EXPORT PWM1_Handler [WEAK] + B . + ENDP + +TIMR1_Handler PROC + EXPORT TIMR1_Handler [WEAK] + B . + ENDP + +HALL_Handler PROC + EXPORT HALL_Handler [WEAK] + B . + ENDP + +PWM0_Handler PROC + EXPORT PWM0_Handler [WEAK] + B . + ENDP + +QSPI0_Handler PROC + EXPORT QSPI0_Handler [WEAK] + B . + ENDP + +PWMBRK_Handler PROC + EXPORT PWMBRK_Handler [WEAK] + B . + ENDP + +USART0_Handler PROC + EXPORT USART0_Handler [WEAK] + B . + ENDP + +WDT_Handler PROC + EXPORT WDT_Handler [WEAK] + B . + ENDP + +I2C0_Handler PROC + EXPORT I2C0_Handler [WEAK] + B . + ENDP + +XTALSTOP_Handler PROC + EXPORT XTALSTOP_Handler [WEAK] + B . + ENDP + +ADC_Handler PROC + EXPORT ADC_Handler [WEAK] + B . + ENDP + +ACMP_Handler PROC + EXPORT ACMP_Handler [WEAK] + B . + ENDP + +BTIMR0_Handler PROC + EXPORT BTIMR0_Handler [WEAK] + B . + ENDP + +BTIMR1_Handler PROC + EXPORT BTIMR1_Handler [WEAK] + B . + ENDP + +BTIMR2_Handler PROC + EXPORT BTIMR2_Handler [WEAK] + B . + ENDP + +BTIMR3_Handler PROC + EXPORT BTIMR3_Handler [WEAK] + B . + ENDP + +GPIOA_Handler PROC + EXPORT GPIOA_Handler [WEAK] + B . + ENDP + +GPIOB_Handler PROC + EXPORT GPIOB_Handler [WEAK] + B . + ENDP + +GPIOC_Handler PROC + EXPORT GPIOC_Handler [WEAK] + B . + ENDP + +GPIOA0_GPIOC0_Handler PROC + EXPORT GPIOA0_GPIOC0_Handler [WEAK] + B . + ENDP + +GPIOA1_GPIOC1_Handler PROC + EXPORT GPIOA1_GPIOC1_Handler [WEAK] + B . + ENDP + +GPIOA2_GPIOC2_MPU_Handler PROC + EXPORT GPIOA2_GPIOC2_MPU_Handler [WEAK] + B . + ENDP + +GPIOA3_GPIOC3_PVD_Handler PROC + EXPORT GPIOA3_GPIOC3_PVD_Handler [WEAK] + B . + ENDP + +GPIOB0_GPIOA8_TIMR2_Handler PROC + EXPORT GPIOB0_GPIOA8_TIMR2_Handler [WEAK] + B . + ENDP + +GPIOB1_GPIOA9_DMA_Handler PROC + EXPORT GPIOB1_GPIOA9_DMA_Handler [WEAK] + B . + ENDP + +GPIOB2_GPIOA10_DIV_Handler PROC + EXPORT GPIOB2_GPIOA10_DIV_Handler [WEAK] + B . + ENDP + +GPIOB3_GPIOA11_SPI0_Handler PROC + EXPORT GPIOB3_GPIOA11_SPI0_Handler [WEAK] + B . + ENDP + +GPIOB4_GPIOB10_QEI_Handler PROC + EXPORT GPIOB4_GPIOB10_QEI_Handler [WEAK] + B . + ENDP + + ALIGN + + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/DeviceSupport/startup/gcc/startup_SWM221.s b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/DeviceSupport/startup/gcc/startup_SWM221.s new file mode 100644 index 0000000..ffeae61 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/DeviceSupport/startup/gcc/startup_SWM221.s @@ -0,0 +1,175 @@ + .syntax unified + .arch armv6-m + +/* Memory Model + The HEAP starts at the end of the DATA section and grows upward. + + The STACK starts at the end of the RAM and grows downward */ + .section .stack + .align 3 + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space 0x800 +__StackTop: + + + .section .heap + .align 3 + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .space 0x000 +__HeapLimit: + + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop + .long Reset_Handler + .long NMI_Handler + .long HardFault_Handler + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long SVC_Handler + .long 0 + .long 0 + .long PendSV_Handler + .long SysTick_Handler + + /* External interrupts */ + .long UART0_Handler + .long TIMR0_Handler + .long CAN0_Handler + .long UART1_Handler + .long PWM1_Handler + .long TIMR1_Handler + .long HALL_Handler + .long PWM0_Handler + .long QSPI0_Handler + .long PWMBRK_Handler + .long USART0_Handler + .long WDT_Handler + .long I2C0_Handler + .long XTALSTOP_Handler + .long ADC_Handler + .long ACMP_Handler + .long BTIMR0_Handler + .long BTIMR1_Handler + .long BTIMR2_Handler + .long BTIMR3_Handler + .long GPIOA_Handler + .long GPIOB_Handler + .long GPIOC_Handler + .long GPIOA0_GPIOC0_Handler + .long GPIOA1_GPIOC1_Handler + .long GPIOA2_GPIOC2_MPU_Handler + .long GPIOA3_GPIOC3_PVD_Handler + .long GPIOB0_GPIOA8_TIMR2_Handler + .long GPIOB1_GPIOA9_DMA_Handler + .long GPIOB2_GPIOA10_DIV_Handler + .long GPIOB3_GPIOA11_SPI0_Handler + .long GPIOB4_GPIOB10_QEI_Handler + + .section .text.Reset_Handler + .align 2 + .thumb + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by symbols evaluated in linker script. */ + ldr r1, =__data_load__ + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .Lflash_to_ram_done + +.Lflash_to_ram_loop: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .Lflash_to_ram_loop +.Lflash_to_ram_done: + + + ldr r2, =__bss_start__ + ldr r3, =__bss_end__ + + subs r3, r2 + ble .Lbss_to_ram_done + + movs r0, 0 +.Lbss_to_ram_loop: + subs r3, #4 + str r0, [r2, r3] + bgt .Lbss_to_ram_loop +.Lbss_to_ram_done: + + ldr r0, =main + bx r0 + .pool + + + .text +/* Macro to define default handlers. + Default handler will be weak symbol and just dead loops. */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .endm + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler SVC_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + + def_default_handler UART0_Handler + def_default_handler TIMR0_Handler + def_default_handler CAN0_Handler + def_default_handler UART1_Handler + def_default_handler PWM1_Handler + def_default_handler TIMR1_Handler + def_default_handler HALL_Handler + def_default_handler PWM0_Handler + def_default_handler QSPI0_Handler + def_default_handler PWMBRK_Handler + def_default_handler USART0_Handler + def_default_handler WDT_Handler + def_default_handler I2C0_Handler + def_default_handler XTALSTOP_Handler + def_default_handler ADC_Handler + def_default_handler ACMP_Handler + def_default_handler BTIMR0_Handler + def_default_handler BTIMR1_Handler + def_default_handler BTIMR2_Handler + def_default_handler BTIMR3_Handler + def_default_handler GPIOA_Handler + def_default_handler GPIOB_Handler + def_default_handler GPIOC_Handler + def_default_handler GPIOA0_GPIOC0_Handler + def_default_handler GPIOA1_GPIOC1_Handler + def_default_handler GPIOA2_GPIOC2_MPU_Handler + def_default_handler GPIOA3_GPIOC3_PVD_Handler + def_default_handler GPIOB0_GPIOA8_TIMR2_Handler + def_default_handler GPIOB1_GPIOA9_DMA_Handler + def_default_handler GPIOB2_GPIOA10_DIV_Handler + def_default_handler GPIOB3_GPIOA11_SPI0_Handler + def_default_handler GPIOB4_GPIOB10_QEI_Handler + + def_default_handler Default_Handler + + .end diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/DeviceSupport/startup/iar/startup_SWM221.s b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/DeviceSupport/startup/iar/startup_SWM221.s new file mode 100644 index 0000000..68886b7 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/DeviceSupport/startup/iar/startup_SWM221.s @@ -0,0 +1,280 @@ +;****************************************************************************************************************************************** +; 文件名称: startup_SWM221.s +; 功能说明: SWM221单片机的启动文件 +; 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +; 注意事项: +; 版本日期: V1.0.0 2016年1月30日 +; 升级记录: +; +; +;****************************************************************************************************************************************** +; @attention +; +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +; REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +; FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +; OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +; -ECTION WITH THEIR PRODUCTS. +; +; COPYRIGHT 2012 Synwit Technology +;****************************************************************************************************************************************** + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UART0_Handler + DCD TIMR0_Handler + DCD CAN0_Handler + DCD UART1_Handler + DCD PWM1_Handler + DCD TIMR1_Handler + DCD HALL_Handler + DCD PWM0_Handler + DCD QSPI0_Handler + DCD PWMBRK_Handler + DCD USART0_Handler + DCD WDT_Handler + DCD I2C0_Handler + DCD XTALSTOP_Handler + DCD ADC_Handler + DCD ACMP_Handler + DCD BTIMR0_Handler + DCD BTIMR1_Handler + DCD BTIMR2_Handler + DCD BTIMR3_Handler + DCD GPIOA_Handler + DCD GPIOB_Handler + DCD GPIOC_Handler + DCD GPIOA0_GPIOC0_Handler + DCD GPIOA1_GPIOC1_Handler + DCD GPIOA2_GPIOC2_MPU_Handler + DCD GPIOA3_GPIOC3_PVD_Handler + DCD GPIOB0_GPIOA8_TIMR2_Handler + DCD GPIOB1_GPIOA9_DMA_Handler + DCD GPIOB2_GPIOA10_DIV_Handler + DCD GPIOB3_GPIOA11_SPI0_Handler + DCD GPIOB4_GPIOB10_QEI_Handler + + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK UART0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_Handler + B UART0_Handler + + PUBWEAK TIMR0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR0_Handler + B TIMR0_Handler + + PUBWEAK CAN0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN0_Handler + B CAN0_Handler + + PUBWEAK UART1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_Handler + B UART1_Handler + + PUBWEAK PWM1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM1_Handler + B PWM1_Handler + + PUBWEAK TIMR1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMR1_Handler + B TIMR1_Handler + + PUBWEAK HALL_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HALL_Handler + B HALL_Handler + + PUBWEAK PWM0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM0_Handler + B PWM0_Handler + + PUBWEAK QSPI0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +QSPI0_Handler + B QSPI0_Handler + + PUBWEAK PWMBRK_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWMBRK_Handler + B PWMBRK_Handler + + PUBWEAK USART0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_Handler + B USART0_Handler + + PUBWEAK WDT_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +WDT_Handler + B WDT_Handler + + PUBWEAK I2C0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_Handler + B I2C0_Handler + + PUBWEAK XTALSTOP_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +XTALSTOP_Handler + B XTALSTOP_Handler + + PUBWEAK ADC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_Handler + B ADC_Handler + + PUBWEAK ACMP_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP_Handler + B ACMP_Handler + + PUBWEAK BTIMR0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIMR0_Handler + B BTIMR0_Handler + + PUBWEAK BTIMR1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIMR1_Handler + B BTIMR1_Handler + + PUBWEAK BTIMR2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIMR2_Handler + B BTIMR2_Handler + + PUBWEAK BTIMR3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BTIMR3_Handler + B BTIMR3_Handler + + PUBWEAK GPIOA_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA_Handler + B GPIOA_Handler + + PUBWEAK GPIOB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB_Handler + B GPIOB_Handler + + PUBWEAK GPIOC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOC_Handler + B GPIOC_Handler + + PUBWEAK GPIOA0_GPIOC0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA0_GPIOC0_Handler + B GPIOA0_GPIOC0_Handler + + PUBWEAK GPIOA1_GPIOC1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA1_GPIOC1_Handler + B GPIOA1_GPIOC1_Handler + + PUBWEAK GPIOA2_GPIOC2_MPU_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA2_GPIOC2_MPU_Handler + B GPIOA2_GPIOC2_MPU_Handler + + PUBWEAK GPIOA3_GPIOC3_PVD_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOA3_GPIOC3_PVD_Handler + B GPIOA3_GPIOC3_PVD_Handler + + PUBWEAK GPIOB0_GPIOA8_TIMR2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB0_GPIOA8_TIMR2_Handler + B GPIOB0_GPIOA8_TIMR2_Handler + + PUBWEAK GPIOB1_GPIOA9_DMA_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB1_GPIOA9_DMA_Handler + B GPIOB1_GPIOA9_DMA_Handler + + PUBWEAK GPIOB2_GPIOA10_DIV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB2_GPIOA10_DIV_Handler + B GPIOB2_GPIOA10_DIV_Handler + + PUBWEAK GPIOB3_GPIOA11_SPI0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB3_GPIOA11_SPI0_Handler + B GPIOB3_GPIOA11_SPI0_Handler + + PUBWEAK GPIOB4_GPIOB10_QEI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIOB4_GPIOB10_QEI_Handler + B GPIOB4_GPIOB10_QEI_Handler + + END diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/DeviceSupport/system_SWM221.c b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/DeviceSupport/system_SWM221.c new file mode 100644 index 0000000..4694c7f --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/DeviceSupport/system_SWM221.c @@ -0,0 +1,224 @@ +/****************************************************************************************************************************************** +* ļ: system_SWM221.c +* ˵: SWM221Ƭʱ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.0.0 2016130 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include +#include "SWM221.h" + + +/****************************************************************************************************************************************** + * ϵͳʱ趨 + *****************************************************************************************************************************************/ +#define SYS_CLK_8MHz 3 //ڲƵ8MHz RC +#define SYS_CLK_XTAL 2 //ⲿ4-24MHz +#define SYS_CLK_PLL 1 //໷ +#define SYS_CLK_32KHz 0 //ڲƵ32KHz RC + +#define SYS_CLK SYS_CLK_PLL + + +#define SYS_CLK_DIV SYS_CLK_DIV_1 //SYS_CLK ѡʱӣ SYS_CLK_DIV Ƶϵͳʱ + + + +#define __HSI ( 8000000UL) //ڲʱ +#define __LSI ( 32000UL) //ڲʱ +#define __HSE (12000000UL) //ⲿʱ +#define __LSE ( 32768UL) //ⲿʱ + + +/********************************** PLL 趨 ********************************************** + * PLLƵ = PLLʱ / INDIV * FBDIV + *****************************************************************************************/ +#define SYS_PLL_SRC SYS_CLK_XTAL //ȡֵSYS_CLK_8MHzSYS_CLK_XTAL + +#define PLL_IN_DIV 3 + +#define PLL_FB_DIV 15 + + + +uint32_t SystemCoreClock = __HSI; //System Clock Frequency (Core Clock) +uint32_t CyclesPerUs = (__HSI / 1000000); //Cycles per micro second + + +/****************************************************************************************************************************************** +* : SystemCoreClockUpdate() +* ˵: This function is used to update the variable SystemCoreClock and must be called whenever the core clock is changed +* : +* : +* ע: +******************************************************************************************************************************************/ +void SystemCoreClockUpdate(void) +{ + if(SYS->CLKSEL & SYS_CLKSEL_SYS_Msk) //SYS <= HRC + { + SystemCoreClock = __HSI; + } + else //SYS <= CLK + { + switch((SYS->CLKSEL & SYS_CLKSEL_CLK_Msk) >> SYS_CLKSEL_CLK_Pos) + { + case SYS_CLK_8MHz: + SystemCoreClock = __HSI; + break; + + case SYS_CLK_XTAL: + SystemCoreClock = __HSE; + break; + + case SYS_CLK_PLL: + { + uint32_t indiv = (SYS->PLLCR & SYS_PLLCR_INDIV_Msk) >> SYS_PLLCR_INDIV_Pos; + uint32_t fbdiv = (SYS->PLLCR & SYS_PLLCR_FBDIV_Msk) >> SYS_PLLCR_FBDIV_Pos; + + if(SYS->PLLCR & SYS_PLLCR_INSEL_Msk) + { + SystemCoreClock = __HSE * fbdiv / indiv; + } + else + { + SystemCoreClock = __HSI * fbdiv / indiv; + } + break; + } + + case SYS_CLK_32KHz: + SystemCoreClock = __LSI; + break; + } + + SystemCoreClock /= (1 << ((SYS->CLKSEL & SYS_CLKSEL_CLK_DIVx_Msk) >> SYS_CLKSEL_CLK_DIVx_Pos)); + } + + CyclesPerUs = SystemCoreClock / 1000000; +} + + +/****************************************************************************************************************************************** +* : +* ˵: The necessary initializaiton of systerm +* : +* : +* ע: +******************************************************************************************************************************************/ +void SystemInit(void) +{ + SYS->CLKEN0 |= (1 << SYS_CLKEN0_ANAC_Pos); + + Flash_Param_at_xMHz(72); + + switchToHRC(); + + switch(SYS_CLK) + { + case SYS_CLK_8MHz: + switchOnHRC(); + break; + + case SYS_CLK_XTAL: + switchOnXTAL(); + break; + + case SYS_CLK_PLL: + switchOnPLL(SYS_PLL_SRC, PLL_IN_DIV, PLL_FB_DIV); + break; + + case SYS_CLK_32KHz: + switchOn32KHz(); + break; + } + + switchToDIV(SYS_CLK, SYS_CLK_DIV); + + Flash_Param_at_xMHz(CyclesPerUs); + + Cache_Clear(); // Cache Clear + + FMC->CACHE |= FMC_CACHE_CEN_Msk; // Cache Enable + + PORTB->PULLD &= ~((1 << PIN10) | (1 << PIN11)); + PORTB->PULLU &= ~((1 << PIN12) | (1 << PIN15)); +} + +void switchToHRC(void) +{ + SYS->RCCR |= (1 << SYS_RCCR_HON_Pos); + + for(int i = 0; i < CyclesPerUs; i++) {} + + SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS <= HRC + + SystemCoreClockUpdate(); +} + +void switchToDIV(uint32_t src, uint32_t div) +{ + SYS->CLKSEL &=~(SYS_CLKSEL_CLK_Msk | SYS_CLKSEL_CLK_DIVx_Msk); + SYS->CLKSEL |= (src << SYS_CLKSEL_CLK_Pos) | + (div << SYS_CLKSEL_CLK_DIVx_Pos); + + SYS->CLKDIVx_ON = 1; + + for(int i = 0; i < CyclesPerUs; i++) {} + + SYS->CLKSEL &=~(1 << SYS_CLKSEL_SYS_Pos); //SYS <= CLK_DIVx + + SystemCoreClockUpdate(); +} + +void switchOnHRC(void) +{ + SYS->RCCR |= (1 << SYS_RCCR_HON_Pos); +} + +void switchOnXTAL(void) +{ + PORTB->PULLU &= ~((1 << PIN11) | (1 << PIN12)); + PORTB->PULLD &= ~((1 << PIN11) | (1 << PIN12)); + + PORT_Init(PORTB, PIN11, PORTB_PIN11_XTAL_IN, 0); + PORT_Init(PORTB, PIN12, PORTB_PIN12_XTAL_OUT, 0); + + SYS->XTALCR |= (1 << SYS_XTALCR_ON_Pos) | (1 << SYS_XTALCR_DET_Pos); +} + +void switchOnPLL(uint32_t src, uint32_t indiv, uint32_t fbdiv) +{ + if(src == SYS_CLK_XTAL) + switchOnXTAL(); + else + switchOnHRC(); + + SYS->PLLCR = (0 << SYS_PLLCR_PWRDN_Pos) | + (1 << SYS_PLLCR_OUTEN_Pos) | + ((src == SYS_CLK_XTAL) << SYS_PLLCR_INSEL_Pos) | + (0 << SYS_PLLCR_BYPASS_Pos) | + (indiv << SYS_PLLCR_INDIV_Pos) | + (fbdiv << SYS_PLLCR_FBDIV_Pos); + + while((SYS->PLLSR & SYS_PLLSR_LOCK_Msk) == 0) __NOP(); //ȴPLL + + SYS->PLLSR |= SYS_PLLSR_ENA_Msk; +} + +void switchOn32KHz(void) +{ + SYS->RCCR |= (1 << SYS_RCCR_LON_Pos); +} diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/DeviceSupport/system_SWM221.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/DeviceSupport/system_SWM221.h new file mode 100644 index 0000000..4f816a1 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/CMSIS/DeviceSupport/system_SWM221.h @@ -0,0 +1,43 @@ +#ifndef __SYSTEM_SWM221_H__ +#define __SYSTEM_SWM221_H__ + +#ifdef __cplusplus + extern "C" { +#endif + + +#define SYS_CLK_8MHz 3 //ڲƵ8MHz RC +#define SYS_CLK_XTAL 2 //ⲿ4-24MHz +#define SYS_CLK_PLL 1 //໷ +#define SYS_CLK_32KHz 0 //ڲƵ32KHz RC + + +#define SYS_CLK_DIV_1 0 +#define SYS_CLK_DIV_2 1 +#define SYS_CLK_DIV_4 2 +#define SYS_CLK_DIV_8 3 + + +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) +extern uint32_t CyclesPerUs; // Cycles per micro second + + +extern void SystemInit(void); + +extern void SystemCoreClockUpdate (void); + + +extern void switchToHRC(void); +extern void switchToDIV(uint32_t src, uint32_t div); + +extern void switchOnHRC(void); +extern void switchOnXTAL(void); +extern void switchOnPLL(uint32_t src, uint32_t indiv, uint32_t fbdiv); +extern void switchOn32KHz(void); + + +#ifdef __cplusplus +} +#endif + +#endif //__SYSTEM_SWM221_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_adc.c b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_adc.c new file mode 100644 index 0000000..b696396 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_adc.c @@ -0,0 +1,311 @@ +/****************************************************************************************************************************************** +* ļ: SWM341_adc.c +* ˵: SWM341ƬADCģת +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.0.0 2016130 +* ¼: +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM221.h" +#include "SWM221_adc.h" + + +/****************************************************************************************************************************************** +* : ADC_Init() +* ˵: ADCģתʼ +* : ADC_TypeDef * ADCx ָҪõADCЧֵADC0ADC1 +* ADC_InitStructure * initStruct ADCضֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void ADC_Init(ADC_TypeDef * ADCx, ADC_InitStructure * initStruct) +{ + switch((uint32_t)ADCx) + { + case ((uint32_t)ADC0): + case ((uint32_t)ADC1): + SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_ADC0_Pos); + break; + } + + ADC_Close(ADCx); //һЩؼĴֻADCرʱ + + ADCx->CR &= ~(ADC_CR_CLKDIV_Msk | ADC_CR_AVG_Msk | ADC_CR_BITS_Pos); + ADCx->CR |= ((initStruct->clkdiv - 1) << ADC_CR_CLKDIV_Pos) | + (initStruct->samplAvg << ADC_CR_AVG_Pos) | + (0 << ADC_CR_BITS_Pos); + + if(initStruct->refsrc & (1 << 0)) + { + PORT_Init(PORTA, PIN11, PORTA_PIN11_ADC_REFP, 0); + + if(initStruct->refsrc & (1 << 1)) + { + SYS->VRFCR &=~SYS_VRFCR_LVL_Msk; + SYS->VRFCR |= (initStruct->refsrc >> 2) << SYS_VRFCR_LVL_Pos; + + SYS->VRFCR |= SYS_VRFCR_EN_Msk; + } + else + { + SYS->VRFCR &=~SYS_VRFCR_EN_Msk; + } + + SYS->ADCREF |= SYS_ADCREF_REFSEL_Msk; + } + else + { + SYS->ADCREF &=~SYS_ADCREF_REFSEL_Msk; + } +} + +static uint32_t ADC_seq2pos(uint32_t seq) +{ + uint32_t pos = 0; + + switch(seq) + { + case ADC_SEQ0: pos = 0; break; + case ADC_SEQ1: pos = 8; break; + } + + return pos; +} + +/****************************************************************************************************************************************** +* : ADC_SEQ_Init() +* ˵: ADCгʼ +* : ADC_TypeDef * ADCx ָҪõADCЧֵADC0ADC1 +* uint32_t seq ָҪõУЧֵADC_SEQ0ADC_SEQ1 +* ADC_SEQ_InitStructure * initStruct ADC趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void ADC_SEQ_Init(ADC_TypeDef * ADCx, uint32_t seq, ADC_SEQ_InitStructure * initStruct) +{ + uint32_t pos = ADC_seq2pos(seq); + + ADCx->SEQTRG &= ~(0xFFu << pos); + ADCx->SEQTRG |= (initStruct->trig_src << pos); + + ADCx->SMPTIM &= ~(0xFFu << pos); + ADCx->SMPTIM |= ((initStruct->samp_tim - 4) << pos); + + ADCx->SMPNUM &= ~(0xFFu << pos); + ADCx->SMPNUM |= ((initStruct->conv_cnt - 1) << pos); + + ADCx->IE |= (initStruct->EOCIntEn << pos); + + if(initStruct->EOCIntEn) + NVIC_EnableIRQ(ADC_IRQn); + + __IO uint32_t * SEQxCHN = (seq == ADC_SEQ0) ? &ADCx->SEQ0CHN : &ADCx->SEQ1CHN; + *SEQxCHN = 0; + for(int i = 0; i < 8; i++) + { + *SEQxCHN |= initStruct->channels[i] << (i * 4); + + if(initStruct->channels[i] == 0xF) + break; + } +} + +/****************************************************************************************************************************************** +* : ADC_CMP_Init() +* ˵: ADCȽϹܳʼ +* : ADC_TypeDef * ADCx ָҪõADCЧֵADC0ADC1 +* uint32_t seq ָҪõУЧֵADC_SEQ0ADC_SEQ1 +* ADC_CMP_InitStructure * initStruct ADCȽϹ趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void ADC_CMP_Init(ADC_TypeDef * ADCx, uint32_t seq, ADC_CMP_InitStructure * initStruct) +{ + if(seq == ADC_SEQ0) + ADCx->SEQ0CHK = (initStruct->UpperLimit << ADC_SEQ0CHK_MAX_Pos) | + (initStruct->LowerLimit << ADC_SEQ0CHK_MIN_Pos); + else + ADCx->SEQ1CHK = (initStruct->UpperLimit << ADC_SEQ1CHK_MAX_Pos) | + (initStruct->LowerLimit << ADC_SEQ1CHK_MIN_Pos); + + if(initStruct->UpperLimitIEn) + ADC_INTEn(ADCx, seq, ADC_IT_CMP_MAX); + + if(initStruct->LowerLimitIEn) + ADC_INTEn(ADCx, seq, ADC_IT_CMP_MIN); + + if(initStruct->UpperLimitIEn || initStruct->LowerLimitIEn) + NVIC_EnableIRQ(ADC_IRQn); +} + +/****************************************************************************************************************************************** +* : ADC_Open() +* ˵: ADCӲADCת +* : ADC_TypeDef * ADCx ָҪõADCЧֵADC0ADC1 +* : +* ע: +******************************************************************************************************************************************/ +void ADC_Open(ADC_TypeDef * ADCx) +{ + ADCx->CR &= ~ADC_CR_PWDN_Msk; + + int clkdiv = ((ADCx->CR & ADC_CR_CLKDIV_Msk) >> ADC_CR_CLKDIV_Pos) + 1; + + for(int i = 0; i < clkdiv * 32; i++) {} // ˳ Powerdown 32 ʱںܹ +} + +/****************************************************************************************************************************************** +* : ADC_Close() +* ˵: ADCرգ޷ӲADCת +* : ADC_TypeDef * ADCx ָҪõADCЧֵADC0ADC1 +* : +* ע: +******************************************************************************************************************************************/ +void ADC_Close(ADC_TypeDef * ADCx) +{ + ADCx->CR |= ADC_CR_PWDN_Msk; +} + +/****************************************************************************************************************************************** +* : ADC_Start() +* ˵: ģʽADCת +* : uint32_t ADC0_seq ָҪõADC0УЧֵΪADC_SEQ0ADC_SEQ1ϣλ㣩 +* uint32_t ADC1_seq ָҪõADC1УЧֵΪADC_SEQ0ADC_SEQ1ϣλ㣩 +* : +* ע: +******************************************************************************************************************************************/ +void ADC_Start(uint32_t ADC0_seq, uint32_t ADC1_seq) +{ + ADC0->START |= (ADC0_seq << ADC_START_ADC0SEQ0_Pos) | + (ADC1_seq << ADC_START_ADC1SEQ0_Pos); +} + +/****************************************************************************************************************************************** +* : ADC_Stop() +* ˵: ģʽֹͣADCת +* : uint32_t ADC0_seq ָҪõADC0УЧֵΪADC_SEQ0ADC_SEQ1ϣλ㣩 +* uint32_t ADC1_seq ָҪõADC1УЧֵΪADC_SEQ0ADC_SEQ1ϣλ㣩 +* : +* ע: +******************************************************************************************************************************************/ +void ADC_Stop(uint32_t ADC0_seq, uint32_t ADC1_seq) +{ + ADC0->START &= ~((ADC0_seq << ADC_START_ADC0SEQ0_Pos) | + (ADC1_seq << ADC_START_ADC1SEQ0_Pos)); +} + +/****************************************************************************************************************************************** +* : ADC_Busy() +* ˵: ADC æѯ +* : ADC_TypeDef * ADCx ָҪõADCЧֵADC0ADC1 +* : bool true ת false +* ע: +******************************************************************************************************************************************/ +bool ADC_Busy(ADC_TypeDef * ADCx) +{ + if(ADCx == ADC0) + return ADC0->START & ADC_START_ADC0BUSY_Msk; + else + return ADC0->START & ADC_START_ADC1BUSY_Msk; +} + +/****************************************************************************************************************************************** +* : ADC_Read() +* ˵: ȡָͨת +* : ADC_TypeDef * ADCx ָҪõADCЧֵADC0ADC1 +* uint32_t chn ҪȡͨЧֵΪADC_CH0ADC_CH1... ...ADC_CH10ADC_CH11 +* : uint32_t ȡת +* ע: +******************************************************************************************************************************************/ +uint32_t ADC_Read(ADC_TypeDef * ADCx, uint32_t chn) +{ + return ADCx->DATA[chn] & ADC_DATA_DATA_Msk; +} + +/****************************************************************************************************************************************** +* : ADC_DataAvailable() +* ˵: ָǷݿɶȡ +* : ADC_TypeDef * ADCx ָҪõADCЧֵADC0ADC1 +* uint32_t chn ҪȡͨЧֵΪADC_CH0ADC_CH1... ...ADC_CH10ADC_CH11 +* : uint32_t 1 ݿɶȡ 0 +* ע: ADC תеô˺һתʱ ADCx->DATA.FLAG λ޷ +******************************************************************************************************************************************/ +uint32_t ADC_DataAvailable(ADC_TypeDef * ADCx, uint32_t chn) +{ + return (ADCx->DATA[chn] & ADC_DATA_FLAG_Msk) != 0; +} + + +/****************************************************************************************************************************************** +* : ADC_INTEn() +* ˵: жʹ +* : ADC_TypeDef * ADCx ָҪõADCЧֵADC0ADC1 +* uint32_t seq ָҪõADCУЧֵΪADC_SEQ0ADC_SEQ1 +* uint32_t it interrupt typeЧֵADC_IT_EOCADC_IT_CMP_MAXADC_IT_CMP_MIN 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void ADC_INTEn(ADC_TypeDef * ADCx, uint32_t seq, uint32_t it) +{ + uint32_t pos = ADC_seq2pos(seq); + + ADCx->IE |= (it << pos); +} + +/****************************************************************************************************************************************** +* : ADC_INTDis() +* ˵: жϽֹ +* : ADC_TypeDef * ADCx ָҪõADCЧֵADC0ADC1 +* uint32_t seq ָҪõADCУЧֵΪADC_SEQ0ADC_SEQ1 +* uint32_t it interrupt typeЧֵADC_IT_EOCADC_IT_CMP_MAXADC_IT_CMP_MIN 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void ADC_INTDis(ADC_TypeDef * ADCx, uint32_t seq, uint32_t it) +{ + uint32_t pos = ADC_seq2pos(seq); + + ADCx->IE &= ~(it << pos); +} + +/****************************************************************************************************************************************** +* : ADC_INTClr() +* ˵: жϱ־ +* : ADC_TypeDef * ADCx ָҪõADCЧֵADC0ADC1 +* uint32_t seq ָҪõADCУЧֵΪADC_SEQ0ADC_SEQ1 +* uint32_t it interrupt typeЧֵADC_IT_EOCADC_IT_CMP_MAXADC_IT_CMP_MIN 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void ADC_INTClr(ADC_TypeDef * ADCx, uint32_t seq, uint32_t it) +{ + uint32_t pos = ADC_seq2pos(seq); + + ADCx->IF = (it << pos); +} + +/****************************************************************************************************************************************** +* : ADC_INTStat() +* ˵: ж״̬ѯ +* : ADC_TypeDef * ADCx ָҪõADCЧֵADC0ADC1 +* uint32_t seq ָҪѯADCУЧֵΪADC_SEQ0ADC_SEQ1 +* uint32_t it interrupt typeЧֵADC_IT_EOCADC_IT_CMP_MAXADC_IT_CMP_MIN 䡰 +* : uint32_t 1 жϷ 0 жδ +* ע: +******************************************************************************************************************************************/ +uint32_t ADC_INTStat(ADC_TypeDef * ADCx, uint32_t seq, uint32_t it) +{ + uint32_t pos = ADC_seq2pos(seq); + + return (ADCx->IF & (it << pos)) ? 1 : 0; +} diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_adc.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_adc.h new file mode 100644 index 0000000..c125590 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_adc.h @@ -0,0 +1,88 @@ +#ifndef __SWM221_ADC_H__ +#define __SWM221_ADC_H__ + + +typedef struct { + uint8_t clkdiv; //1-32 + uint8_t refsrc; //ADC_REF_VDDADC_REF_REFPADC_REF_2V4ADC_REF_3V6ADC_REF_4V5 + uint8_t samplAvg; //ADC_AVG_SAMPLE1ADC_AVG_SAMPLE2ADC_AVG_SAMPLE4ADC_AVG_SAMPLE8 +} ADC_InitStructure; + + +typedef struct { + uint8_t trig_src; //ADCдʽADC_TRIGGER_SWADC_TRIGGER_TIMER0ADC_TRIGGER_TIMER1... ... + uint8_t samp_tim; //ADCвʱ䣬ȡֵ4--259 + uint8_t conv_cnt; //ADCתȡֵ1--256 + uint8_t EOCIntEn; //תжʹܣȡֵ01 + uint8_t *channels; //תͨѡԪΪ ADC_CH0ADC_CH1...ADC_CH11 飬 8 ͨ 0xF ͨظ +} ADC_SEQ_InitStructure; + + +typedef struct { + uint16_t UpperLimit; //Ƚֵ + uint16_t UpperLimitIEn; //ADCתUpperLimitжʹ + uint16_t LowerLimit; //Ƚֵ + uint16_t LowerLimitIEn; //ADCתСLowerLimitжʹ +} ADC_CMP_InitStructure; + + +#define ADC_SEQ0 0x1 +#define ADC_SEQ1 0x2 + +#define ADC_CH0 0 +#define ADC_CH1 1 +#define ADC_CH2 2 +#define ADC_CH3 3 +#define ADC_CH4 4 +#define ADC_CH5 5 +#define ADC_CH6 6 +#define ADC_CH7 7 +#define ADC_CH8 8 +#define ADC_CH9 9 + +#define ADC_REF_VDD (0) +#define ADC_REF_REFP (1 | (0 << 1)) +#define ADC_REF_2V4 (1 | (1 << 1) | (0 << 2)) +#define ADC_REF_3V6 (1 | (1 << 1) | (1 << 2)) +#define ADC_REF_4V5 (1 | (1 << 1) | (2 << 2)) + +#define ADC_AVG_SAMPLE1 0 +#define ADC_AVG_SAMPLE2 1 //һת2ΣνƽֵΪת +#define ADC_AVG_SAMPLE4 2 +#define ADC_AVG_SAMPLE8 3 + +#define ADC_TRIGGER_NO 0 +#define ADC_TRIGGER_SW 1 // +#define ADC_TRIGGER_TIMER0 2 +#define ADC_TRIGGER_TIMER1 3 +#define ADC_TRIGGER_TIMER2 4 +#define ADC_TRIGGER_PWM0 16 +#define ADC_TRIGGER_PWM1 17 + + +/* Interrupt Type */ +#define ADC_IT_EOC (1 << 0) //End Of Conversion +#define ADC_IT_CMP_MAX (1 << 1) //תCOMP.MAX +#define ADC_IT_CMP_MIN (1 << 2) //תСCOMP.MIN + + +void ADC_Init(ADC_TypeDef * ADCx, ADC_InitStructure * initStruct); //ADCģתʼ +void ADC_SEQ_Init(ADC_TypeDef * ADCx, uint32_t seq, ADC_SEQ_InitStructure * initStruct); //ADCгʼ +void ADC_CMP_Init(ADC_TypeDef * ADCx, uint32_t seq, ADC_CMP_InitStructure * initStruct); //ADCȽϹܳʼ +void ADC_Open(ADC_TypeDef * ADCx); //ADCӲADCת +void ADC_Close(ADC_TypeDef * ADCx); //ADCرգ޷ӲADCת +void ADC_Start(uint32_t ADC0_seq, uint32_t ADC1_seq); //ָADCʼģת +void ADC_Stop(uint32_t ADC0_seq, uint32_t ADC1_seq); //رָADCֹͣģת +bool ADC_Busy(ADC_TypeDef * ADCx); + +uint32_t ADC_Read(ADC_TypeDef * ADCx, uint32_t chn); //ָͨȡת +uint32_t ADC_DataAvailable(ADC_TypeDef * ADCx, uint32_t chn); //ָͨǷݿɶȡ + + +void ADC_INTEn(ADC_TypeDef * ADCx, uint32_t seq, uint32_t it); +void ADC_INTEn(ADC_TypeDef * ADCx, uint32_t seq, uint32_t it); +void ADC_INTClr(ADC_TypeDef * ADCx, uint32_t seq, uint32_t it); +uint32_t ADC_INTStat(ADC_TypeDef * ADCx, uint32_t seq, uint32_t it); + + +#endif //__SWM221_ADC_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_can.c b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_can.c new file mode 100644 index 0000000..62a9a3e --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_can.c @@ -0,0 +1,427 @@ +/****************************************************************************************************************************************** +* ļ: SWM221_can.c +* ˵: SWM221ƬCANģ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM221.h" +#include "SWM221_can.h" + + +/****************************************************************************************************************************************** +* : CAN_Init() +* ˵: CANӿڳʼ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN0 +* CAN_InitStructure * initStruct CANӿ趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void CAN_Init(CAN_TypeDef * CANx, CAN_InitStructure * initStruct) +{ + uint32_t brp = SystemCoreClock/2/initStruct->Baudrate/(1 + (initStruct->CAN_bs1 + 1) + (initStruct->CAN_bs2 + 1)) - 1; + + switch((uint32_t)CANx) + { + case ((uint32_t)CAN0): + SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_CAN0_Pos); + break; + } + + CAN_Close(CANx); //һЩؼĴֻCANرʱ + + CANx->CR &= ~(CAN_CR_LOM_Msk | CAN_CR_STM_Msk); + CANx->CR |= (initStruct->Mode << CAN_CR_LOM_Pos); + + CANx->BT1 = (0 << CAN_BT1_SAM_Pos) | + (initStruct->CAN_bs1 << CAN_BT1_TSEG1_Pos) | + (initStruct->CAN_bs2 << CAN_BT1_TSEG2_Pos); + + CANx->BT0 = (initStruct->CAN_sjw << CAN_BT0_SJW_Pos) | + ((brp & 0x3F) << CAN_BT0_BRP_Pos); + + CANx->BT2 = ((brp >> 6) << CAN_BT2_BRP_Pos); + + CANx->RXERR = 0; //ֻڸλģʽ + CANx->TXERR = 0; + + CANx->IE = (initStruct->RXNotEmptyIEn << CAN_IE_RXDA_Pos) | + (initStruct->ArbitrLostIEn << CAN_IE_ARBLOST_Pos) | + (initStruct->ErrPassiveIEn << CAN_IE_ERRPASS_Pos); + + switch((uint32_t)CANx) + { + case ((uint32_t)CAN0): + if(initStruct->RXNotEmptyIEn | initStruct->ArbitrLostIEn | initStruct->ErrPassiveIEn) + { + NVIC_EnableIRQ(CAN0_IRQn); + } + else + { + NVIC_DisableIRQ(CAN0_IRQn); + } + break; + } +} + +/****************************************************************************************************************************************** +* : CAN_Open() +* ˵: CANӿڴ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN0 +* : +* ע: +******************************************************************************************************************************************/ +void CAN_Open(CAN_TypeDef * CANx) +{ + CANx->CR &= ~(0x01 << CAN_CR_RST_Pos); //˳λģʽ빤ģʽ +} + +/****************************************************************************************************************************************** +* : CAN_Close() +* ˵: CANӿڹر +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN0 +* : +* ע: +******************************************************************************************************************************************/ +void CAN_Close(CAN_TypeDef * CANx) +{ + CANx->CR |= (0x01 << CAN_CR_RST_Pos); //븴λģʽܷͺͽ +} + +/****************************************************************************************************************************************** +* : CAN_Transmit() +* ˵: CAN +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN0 +* uint32_t format CAN_FRAME_STD ׼֡ CAN_FRAME_EXT չ֡ +* uint32_t id ϢID +* uint8_t data[] Ҫ͵ +* uint32_t size Ҫ͵ݵĸ +* uint32_t once ֻһΣʹʧܣٲöʧͳNAKҲط +* : +* ע: +******************************************************************************************************************************************/ +void CAN_Transmit(CAN_TypeDef * CANx, uint32_t format, uint32_t id, uint8_t data[], uint32_t size, uint32_t once) +{ + uint32_t i; + + if(format == CAN_FRAME_STD) + { + CANx->FRAME.INFO = (0 << CAN_INFO_FF_Pos) | + (0 << CAN_INFO_RTR_Pos) | + (size << CAN_INFO_DLC_Pos); + + CANx->FRAME.DATA[0] = id >> 3; + CANx->FRAME.DATA[1] = id << 5; + + for(i = 0; i < size; i++) + { + CANx->FRAME.DATA[i+2] = data[i]; + } + } + else //if(format == CAN_FRAME_EXT) + { + CANx->FRAME.INFO = (1 << CAN_INFO_FF_Pos) | + (0 << CAN_INFO_RTR_Pos) | + (size << CAN_INFO_DLC_Pos); + + CANx->FRAME.DATA[0] = id >> 21; + CANx->FRAME.DATA[1] = id >> 13; + CANx->FRAME.DATA[2] = id >> 5; + CANx->FRAME.DATA[3] = id << 3; + + for(i = 0; i < size; i++) + { + CANx->FRAME.DATA[i+4] = data[i]; + } + } + + if(CANx->CR & CAN_CR_STM_Msk) + { + CANx->CMD = (1 << CAN_CMD_SRR_Pos); + } + else + { + if(once == 0) + { + CANx->CMD = (1 << CAN_CMD_TXREQ_Pos); + } + else + { + CANx->CMD = (1 << CAN_CMD_TXREQ_Pos) | (1 << CAN_CMD_ABTTX_Pos); + } + } +} + +/****************************************************************************************************************************************** +* : CAN_TransmitRequest() +* ˵: CANԶԶ̽ڵ㷢 +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN0 +* uint32_t format CAN_FRAME_STD ׼֡ CAN_FRAME_EXT չ֡ +* uint32_t id ϢID +* uint32_t once ֻһΣʹʧܣٲöʧͳNAKҲط +* : +* ע: +******************************************************************************************************************************************/ +void CAN_TransmitRequest(CAN_TypeDef * CANx, uint32_t format, uint32_t id, uint32_t once) +{ + if(format == CAN_FRAME_STD) + { + CANx->FRAME.INFO = (0 << CAN_INFO_FF_Pos) | + (1 << CAN_INFO_RTR_Pos) | + (0 << CAN_INFO_DLC_Pos); + + CANx->FRAME.DATA[0] = id >> 3; + CANx->FRAME.DATA[1] = id << 5; + } + else //if(format == CAN_FRAME_EXT) + { + CANx->FRAME.INFO = (1 << CAN_INFO_FF_Pos) | + (1 << CAN_INFO_RTR_Pos) | + (0 << CAN_INFO_DLC_Pos); + + CANx->FRAME.DATA[0] = id >> 21; + CANx->FRAME.DATA[1] = id >> 13; + CANx->FRAME.DATA[2] = id >> 5; + CANx->FRAME.DATA[3] = id << 3; + } + + if(once == 0) + { + CANx->CMD = (1 << CAN_CMD_TXREQ_Pos); + } + else + { + CANx->CMD = (1 << CAN_CMD_TXREQ_Pos) | (1 << CAN_CMD_ABTTX_Pos); + } +} + +/****************************************************************************************************************************************** +* : CAN_Receive() +* ˵: CAN +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN0 +* CAN_RXMessage *msg յϢ洢ڴ˽ṹ +* : +* ע: +******************************************************************************************************************************************/ +void CAN_Receive(CAN_TypeDef * CANx, CAN_RXMessage *msg) +{ + uint32_t i; + msg->format = (CANx->FRAME.INFO & CAN_INFO_FF_Msk) >> CAN_INFO_FF_Pos; + + msg->remote = (CANx->FRAME.INFO & CAN_INFO_RTR_Msk) >> CAN_INFO_RTR_Pos; + msg->size = (CANx->FRAME.INFO & CAN_INFO_DLC_Msk) >> CAN_INFO_DLC_Pos; + + if(msg->format == CAN_FRAME_STD) + { + msg->id = (CANx->FRAME.DATA[0] << 3) | (CANx->FRAME.DATA[1] >> 5); + + for(i = 0; i < msg->size; i++) + { + msg->data[i] = CANx->FRAME.DATA[i+2]; + } + } + else //if(msg->format == CAN_FRAME_EXT) + { + msg->id = (CANx->FRAME.DATA[0] << 21) | (CANx->FRAME.DATA[1] << 13) | (CANx->FRAME.DATA[2] << 5) | (CANx->FRAME.DATA[3] >> 3); + + for(i = 0; i < msg->size; i++) + { + msg->data[i] = CANx->FRAME.DATA[i+4]; + } + } + + CANx->CMD = (1 << CAN_CMD_RRB_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_TXComplete() +* ˵: Ƿ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN0 +* : uint32_t 1 Ѿ 0 δ +* ע: ͱAbortҲᴥɣᴥͳɹ +******************************************************************************************************************************************/ +uint32_t CAN_TXComplete(CAN_TypeDef * CANx) +{ + return (CANx->SR & CAN_SR_TXBR_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : CAN_TXSuccess() +* ˵: Ƿɹ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN0 +* : uint32_t 1 ͳɹ 0 ʧ +* ע: +******************************************************************************************************************************************/ +uint32_t CAN_TXSuccess(CAN_TypeDef * CANx) +{ + return (CANx->SR & CAN_SR_TXOK_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : CAN_AbortTransmit() +* ˵: ֹ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN0 +* : +* ע: ڽеķ޷ִֹдʧܲط +******************************************************************************************************************************************/ +void CAN_AbortTransmit(CAN_TypeDef * CANx) +{ + CANx->CMD = (1 << CAN_CMD_ABTTX_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_TXBufferReady() +* ˵: TX BufferǷ׼ÿдϢ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN0 +* : uint32_t 1 ׼ 0 δ׼ +* ע: +******************************************************************************************************************************************/ +uint32_t CAN_TXBufferReady(CAN_TypeDef * CANx) +{ + return (CANx->SR & CAN_SR_TXBR_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : CAN_RXDataAvailable() +* ˵: RX FIFOǷݿɶ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN0 +* : uint32_t 1 ݿɶ 0 û +* ע: +******************************************************************************************************************************************/ +uint32_t CAN_RXDataAvailable(CAN_TypeDef * CANx) +{ + return (CANx->SR & CAN_SR_RXDA_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : CAN_SetBaudrate() +* ˵: ò +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN0 +* uint32_t baudrate ʣλ +* uint32_t CAN_bs1 CAN_BS1_1tqCAN_BS1_2tq... ... CAN_BS1_16tq +* uint32_t CAN_bs2 CAN_BS2_1tqCAN_BS2_2tq... ... CAN_BS2_8tq +* uint32_t CAN_sjw CAN_SJW_1tqCAN_SJW_2tqCAN_SJW_3tqCAN_SJW_4tq +* : +* ע: ǰҪȵCAN_Close()رCANģ +******************************************************************************************************************************************/ +void CAN_SetBaudrate(CAN_TypeDef * CANx, uint32_t baudrate, uint32_t CAN_bs1, uint32_t CAN_bs2, uint32_t CAN_sjw) +{ + uint32_t brp = SystemCoreClock/2/baudrate/(1 + (CAN_bs1 + 1) + (CAN_bs2 + 1)) - 1; + + CANx->BT1 = (0 << CAN_BT1_SAM_Pos) | + (CAN_bs1 << CAN_BT1_TSEG1_Pos) | + (CAN_bs2 << CAN_BT1_TSEG2_Pos); + + CANx->BT0 = (CAN_sjw << CAN_BT0_SJW_Pos) | + ((brp & 0x3F) << CAN_BT0_BRP_Pos); + + CANx->BT2 = ((brp >> 6) << CAN_BT2_BRP_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_SetFilter32b() +* ˵: ý˲ģʽΪ132λ˲ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN0 +* uint32_t filter Ҫõ˲ЧֵCAN_FILTER_1CAN_FILTER_2...CAN_FILTER_16 +* uint32_t check maskһ˽յMessageǷԼҪģcheck & mask == ID & maskMessageͨ +* uint32_t mask +* : +* ע: ֻڹرʱ +******************************************************************************************************************************************/ +void CAN_SetFilter32b(CAN_TypeDef * CANx, uint32_t filter, uint32_t check, uint32_t mask) +{ + CANx->AFM |= (1 << filter); + + CANx->ACR[filter] = __REV(check << 3); // 29λ + CANx->AMR[filter] = __REV(~(mask << 3)); + + CANx->AFE |= (1 << filter); +} + +/****************************************************************************************************************************************** +* : CAN_SetFilter16b() +* ˵: ý˲ģʽΪ216λ˲ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN0 +* uint32_t filter Ҫõ˲ЧֵCAN_FILTER_1CAN_FILTER_2...CAN_FILTER_16 +* uint16_t check1 maskһ˽յMessageǷԼҪģcheck & mask == ID & maskMessageͨ +* uint16_t mask1 +* uint16_t check2 +* uint16_t mask2 +* : +* ע: ֻڹرʱ +******************************************************************************************************************************************/ +void CAN_SetFilter16b(CAN_TypeDef * CANx, uint32_t filter, uint16_t check1, uint16_t mask1, uint16_t check2, uint16_t mask2) +{ + CANx->AFM &= ~(1 << filter); + + CANx->ACR[filter] = __REV((check1 << 5) | (check2 << 21)); // 11λ + CANx->AMR[filter] = __REV(~((mask1 << 5) | (mask2 << 21))); + + CANx->AFE |= (1 << filter); +} + +/****************************************************************************************************************************************** +* : CAN_INTEn() +* ˵: ʹָж +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN0 +* uint32_t it interrupt typeЧֵ CAN_IT_RX_NOTEMPTYCAN_IT_RX_OVERFLOWCAN_IT_TX_EMPTYCAN_IT_ARBLOST +* CAN_IT_ERRCAN_IT_ERR_WARNCAN_IT_ERR_PASSCAN_IT_WAKEUP 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void CAN_INTEn(CAN_TypeDef * CANx, uint32_t it) +{ + CANx->IE |= it; +} + +/****************************************************************************************************************************************** +* : CAN_INTDis() +* ˵: رָж +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN0 +* uint32_t it interrupt typeЧֵ CAN_IT_RX_NOTEMPTYCAN_IT_RX_OVERFLOWCAN_IT_TX_EMPTYCAN_IT_ARBLOST +* CAN_IT_ERRCAN_IT_ERR_WARNCAN_IT_ERR_PASSCAN_IT_WAKEUP 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void CAN_INTDis(CAN_TypeDef * CANx, uint32_t it) +{ + CANx->IE &= ~it; +} + +/****************************************************************************************************************************************** +* : CAN_INTClr() +* ˵: жϱ־ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN0 +* uint32_t it interrupt typeЧֵ CAN_IT_RX_OVERFLOW +* : +* ע: +******************************************************************************************************************************************/ +void CAN_INTClr(CAN_TypeDef * CANx, uint32_t it) +{ + CANx->CMD = (1 << CAN_CMD_CLROV_Pos); +} + +/****************************************************************************************************************************************** +* : CAN_INTStat() +* ˵: ѯж״̬ +* : CAN_TypeDef * CANx ָҪõCANӿڣЧֵCAN0 +* : uint32_t ǰж״̬ +* ע: CANx->IFȡ㣬жISRֻܶȡһΣܶζȡ +******************************************************************************************************************************************/ +uint32_t CAN_INTStat(CAN_TypeDef * CANx) +{ + return CANx->IF; +} diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_can.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_can.h new file mode 100644 index 0000000..d1eeab4 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_can.h @@ -0,0 +1,121 @@ +#ifndef __SWM221_CAN_H__ +#define __SWM221_CAN_H__ + + +typedef struct { + uint8_t Mode; //CAN_MODE_NORMALCAN_MODE_LISTENCAN_MODE_SELFTEST + uint8_t CAN_bs1; //CAN_BS1_1tqCAN_BS1_2tq... ... CAN_BS1_16tq + uint8_t CAN_bs2; //CAN_BS2_1tqCAN_BS2_2tq... ... CAN_BS2_8tq + uint8_t CAN_sjw; //CAN_SJW_1tqCAN_SJW_2tqCAN_SJW_3tqCAN_SJW_4tq + uint32_t Baudrate; //ʣλʣȡֵ1--1000000 + uint8_t RXNotEmptyIEn; //FIFOǿգݿɶ + uint8_t ArbitrLostIEn; //ʧٲñɽշ + uint8_t ErrPassiveIEn; ///ʹֵﵽ127 +} CAN_InitStructure; + + +#define CAN_MODE_NORMAL 0 //ģʽ +#define CAN_MODE_LISTEN 1 //ģʽ +#define CAN_MODE_SELFTEST 2 //Բģʽ + +#define CAN_BS1_1tq 0 +#define CAN_BS1_2tq 1 +#define CAN_BS1_3tq 2 +#define CAN_BS1_4tq 3 +#define CAN_BS1_5tq 4 +#define CAN_BS1_6tq 5 +#define CAN_BS1_7tq 6 +#define CAN_BS1_8tq 7 +#define CAN_BS1_9tq 8 +#define CAN_BS1_10tq 9 +#define CAN_BS1_11tq 10 +#define CAN_BS1_12tq 11 +#define CAN_BS1_13tq 12 +#define CAN_BS1_14tq 13 +#define CAN_BS1_15tq 14 +#define CAN_BS1_16tq 15 + +#define CAN_BS2_1tq 0 +#define CAN_BS2_2tq 1 +#define CAN_BS2_3tq 2 +#define CAN_BS2_4tq 3 +#define CAN_BS2_5tq 4 +#define CAN_BS2_6tq 5 +#define CAN_BS2_7tq 6 +#define CAN_BS2_8tq 7 + +#define CAN_SJW_1tq 0 +#define CAN_SJW_2tq 1 +#define CAN_SJW_3tq 2 +#define CAN_SJW_4tq 3 + +#define CAN_FRAME_STD 0 +#define CAN_FRAME_EXT 1 + +#define CAN_FILTER_1 0 +#define CAN_FILTER_2 1 +#define CAN_FILTER_3 2 +#define CAN_FILTER_4 3 +#define CAN_FILTER_5 4 +#define CAN_FILTER_6 5 +#define CAN_FILTER_7 6 +#define CAN_FILTER_8 7 +#define CAN_FILTER_9 8 +#define CAN_FILTER_10 9 +#define CAN_FILTER_11 10 +#define CAN_FILTER_12 11 +#define CAN_FILTER_13 12 +#define CAN_FILTER_14 13 +#define CAN_FILTER_15 14 +#define CAN_FILTER_16 15 + + +/* Interrupt Type */ +#define CAN_IT_RX_NOTEMPTY (0x01 << 0) //RX Buffer Not Empty +#define CAN_IT_RX_OVERFLOW (0x01 << 3) //RX Buffer Overflow +#define CAN_IT_TX_EMPTY (0x01 << 1) //TX Buffer Empty +#define CAN_IT_ARBLOST (0x01 << 6) //Arbitration lost +#define CAN_IT_ERR (0x01 << 7) +#define CAN_IT_ERR_WARN (0x01 << 2) //TXERR/RXERRֵﵽError Warning Limit +#define CAN_IT_ERR_PASS (0x01 << 5) //TXERR/RXERRֵﵽ127 +#define CAN_IT_WAKEUP (0x01 << 4) + + + +typedef struct { + uint32_t id; //ϢID + uint8_t format; //֡ʽCAN_FRAME_STD(11bit ID)CAN_FRAME_EXT(29bit ID) + uint8_t remote; //ϢǷΪԶ֡ + uint8_t size; //յݸ + uint8_t data[8]; //յ +} CAN_RXMessage; + + +void CAN_Init(CAN_TypeDef * CANx, CAN_InitStructure * initStruct); +void CAN_Open(CAN_TypeDef * CANx); +void CAN_Close(CAN_TypeDef * CANx); + +void CAN_Transmit(CAN_TypeDef * CANx, uint32_t format, uint32_t id, uint8_t data[], uint32_t size, uint32_t once); +void CAN_TransmitRequest(CAN_TypeDef * CANx, uint32_t format, uint32_t id, uint32_t once); +void CAN_Receive(CAN_TypeDef * CANx, CAN_RXMessage *msg); + +uint32_t CAN_TXComplete(CAN_TypeDef * CANx); +uint32_t CAN_TXSuccess(CAN_TypeDef * CANx); + +void CAN_AbortTransmit(CAN_TypeDef * CANx); + +uint32_t CAN_TXBufferReady(CAN_TypeDef * CANx); +uint32_t CAN_RXDataAvailable(CAN_TypeDef * CANx); + +void CAN_SetBaudrate(CAN_TypeDef * CANx, uint32_t baudrate, uint32_t CAN_bs1, uint32_t CAN_bs2, uint32_t CAN_sjw); + +void CAN_SetFilter32b(CAN_TypeDef * CANx, uint32_t filter, uint32_t check, uint32_t mask); +void CAN_SetFilter16b(CAN_TypeDef * CANx, uint32_t filter, uint16_t check1, uint16_t mask1, uint16_t check2, uint16_t mask2); + +void CAN_INTEn(CAN_TypeDef * CANx, uint32_t it); +void CAN_INTDis(CAN_TypeDef * CANx, uint32_t it); +void CAN_INTClr(CAN_TypeDef * CANx, uint32_t it); +uint32_t CAN_INTStat(CAN_TypeDef * CANx); + + +#endif //__SWM221_CAN_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_crc.c b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_crc.c new file mode 100644 index 0000000..98547e1 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_crc.c @@ -0,0 +1,67 @@ +/****************************************************************************************************************************************** +* ļ: SWM341_crc.c +* ˵: SWM341ƬCRCģ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM221.h" +#include "SWM221_crc.h" + + +/****************************************************************************************************************************************** +* : CRC_Init() +* ˵: CRC ʼ +* : CRC_TypeDef * CRCx ָҪõCRCӿڣЧֵCRC +* CRC_InitStructure * initStruct CRC趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void CRC_Init(CRC_TypeDef * CRCx, CRC_InitStructure * initStruct) +{ + switch((uint32_t)CRCx) + { + case ((uint32_t)CRC): + SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_CRC_Pos); + break; + } + + CRCx->INIVAL = initStruct->init_crc; + + CRCx->CR = (1 << CRC_CR_EN_Pos) | + (initStruct->Poly << CRC_CR_POLY_Pos) | + (initStruct->in_width << CRC_CR_IBIT_Pos) | + (initStruct->in_rev << CRC_CR_IREV_Pos) | + (initStruct->in_not << CRC_CR_INOT_Pos) | + (initStruct->out_rev << CRC_CR_OREV_Pos) | + (initStruct->out_not << CRC_CR_ONOT_Pos); +} + + +/****************************************************************************************************************************************** +* : CRC_SetInitVal() +* ˵: CRCʼֵ +* : CRC_TypeDef * CRCx ָҪõCRCӿڣЧֵCRC +* uint32_t init_crc CRCʼֵ +* : +* ע: +******************************************************************************************************************************************/ +void CRC_SetInitVal(CRC_TypeDef * CRCx, uint32_t init_crc) +{ + CRCx->INIVAL = init_crc; + + CRCx->CR |= (1 << CRC_CR_EN_Pos); +} diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_crc.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_crc.h new file mode 100644 index 0000000..5c4cfbc --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_crc.h @@ -0,0 +1,59 @@ +#ifndef __SWM221_CRC_H__ +#define __SWM221_CRC_H__ + + +typedef struct { + uint32_t init_crc; // ʼֵ + uint8_t Poly; // CRCʽȡֵCRC_POLY_11021CRC_POLY_107CRC_POLY_18005CRC_POLY_104C11DB7 + uint8_t in_width; // ݿȣȡֵCRC_WIDTH_32CRC_WIDTH_16CRC_WIDTH_8 + uint8_t in_rev; // ݷתȡֵCRC_REV_NOTCRC_REV_ALLCRC_REV_IN_BYTECRC_REV_BYTE + bool in_not; // ȡ + uint8_t out_rev; // תȡֵCRC_REV_NOTCRC_REV_ALLCRC_REV_IN_BYTECRC_REV_BYTE + bool out_not; // ȡ +} CRC_InitStructure; + + +#define CRC_POLY_11021 0 // x^16+x^12+x^5+1 +#define CRC_POLY_107 1 // x^8+x^2+x+1 +#define CRC_POLY_18005 2 // x^16+x^15+x^2+1 +#define CRC_POLY_104C11DB7 3 // x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 + +#define CRC_WIDTH_32 0 +#define CRC_WIDTH_16 1 +#define CRC_WIDTH_8 2 + +#define CRC_REV_NOT 0 // bit˳򲻱 +#define CRC_REV_ALL 1 // bit˳ȫת +#define CRC_REV_IN_BYTE 2 // bit˳ֽڷת +#define CRC_REV_BYTE 3 // ֽ˳ת + + +void CRC_Init(CRC_TypeDef * CRCx, CRC_InitStructure * initStruct); +void CRC_SetInitVal(CRC_TypeDef * CRCx, uint32_t init_crc); + + +/****************************************************************************************************************************************** +* : CRC_Write() +* ˵: CRCд +* : uint32_t data Ҫд +* : +* ע: +******************************************************************************************************************************************/ +static __INLINE void CRC_Write(uint32_t data) +{ + CRC->DATAIN = data; +} + +/****************************************************************************************************************************************** +* : CRC_Result() +* ˵: ȡCRC +* : +* : uint32_t CRC +* ע: +******************************************************************************************************************************************/ +static __INLINE uint32_t CRC_Result(void) +{ + return CRC->RESULT; +} + +#endif //__SWM221_CRC_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_div.c b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_div.c new file mode 100644 index 0000000..241dc57 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_div.c @@ -0,0 +1,40 @@ +/****************************************************************************************************************************************** +* ļ: SWM221_div.c +* ˵: SWM221ƬDIVӲ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.0.0 2016130 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM221.h" +#include "SWM221_div.h" + + +/****************************************************************************************************************************************** +* : DIV_Init() +* ˵: Ӳʼ +* : DIV_TypeDef * DIVx ָҪõӲЧֵDIV +* : +* ע: +******************************************************************************************************************************************/ +void DIV_Init(DIV_TypeDef * DIVx) +{ + switch((uint32_t)DIVx) + { + case ((uint32_t)DIV): + SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_DIV_Pos); + break; + } +} diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_div.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_div.h new file mode 100644 index 0000000..54aea4b --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_div.h @@ -0,0 +1,129 @@ +#ifndef __SWM221_DIV_H__ +#define __SWM221_DIV_H__ + + +void DIV_Init(DIV_TypeDef * DIVx); + + +/****************************************************************************************************************************************** +* : DIV_UDiv() +* ˵: ʹӲִ޷ +* : uint32_t dividend +* uint32_t divisor +* : +* ע: +******************************************************************************************************************************************/ +static __INLINE void DIV_UDiv(uint32_t dividend, uint32_t divisor) +{ + DIV->DIVIDEND = dividend; + DIV->DIVISOR = divisor; + + DIV->CR = (1 << DIV_CR_DIVSIGN_Pos) | (1 << DIV_CR_DIVGO_Pos); +} + +/****************************************************************************************************************************************** +* : DIV_SDiv() +* ˵: ʹӲִз +* : int32_t dividend +* int32_t divisor +* : +* ע: +******************************************************************************************************************************************/ +static __INLINE void DIV_SDiv(int32_t dividend, int32_t divisor) +{ + DIV->DIVIDEND = dividend; + DIV->DIVISOR = divisor; + + DIV->CR = (0 << DIV_CR_DIVSIGN_Pos) | (1 << DIV_CR_DIVGO_Pos); +} + +/****************************************************************************************************************************************** +* : DIV_Div_IsBusy() +* ˵: ӲǷִг +* : +* : uint32_t 1 Ӳִг 0 Ӳɳ㣬ȡ +* ע: +******************************************************************************************************************************************/ +static __INLINE uint32_t DIV_Div_IsBusy(void) +{ + return (DIV->SR & DIV_SR_DIVBUSY_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : DIV_UDiv_Result() +* ˵: ȡӲ +* : +* : uint32_t *quotient +* uint32_t *remainder +* ע: +******************************************************************************************************************************************/ +static __INLINE void DIV_UDiv_Result(uint32_t *quotient, uint32_t *remainder) +{ + *quotient = DIV->QUO; + *remainder = DIV->REMAIN; +} + +/****************************************************************************************************************************************** +* : DIV_SDiv_Result() +* ˵: ȡӲ +* : +* : int32_t *quotient +* int32_t *remainder +* ע: +******************************************************************************************************************************************/ +static __INLINE void DIV_SDiv_Result(int32_t *quotient, int32_t *remainder) +{ + *quotient = DIV->QUO & 0x7FFFFFFF; + if(DIV->QUO & (1u << 31)) *quotient = 0 - *quotient; + + *remainder = DIV->REMAIN & 0x7FFFFFFF; + if(DIV->REMAIN & (1u << 31)) *remainder = 0 - *remainder; +} + +/****************************************************************************************************************************************** +* : DIV_Root() +* ˵: ʹӲģִп +* : uint32_t radicand +* uint32_t calcu_frac 0 Ϊ16λ 1 Ϊ16λ+16λС +* : +* ע: +******************************************************************************************************************************************/ +static __INLINE void DIV_Root(uint32_t radicand, uint32_t calcu_fractional) +{ + DIV->RADICAND = radicand; + + DIV->CR = (1 << DIV_CR_ROOTGO_Pos) | (calcu_fractional << DIV_CR_ROOTMOD_Pos); +} + +/****************************************************************************************************************************************** +* : DIV_Root_IsBusy() +* ˵: ӲģǷִп +* : +* : uint32_t 1 Ӳģִп 0 Ӳģɿ㣬ȡ +* ע: +******************************************************************************************************************************************/ +static __INLINE uint32_t DIV_Root_IsBusy(void) +{ + return (DIV->SR & DIV_SR_ROOTBUSY_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : DIV_Root_Result() +* ˵: ȡӲģ +* : +* : uint32_t +* ע: +******************************************************************************************************************************************/ +static __INLINE uint32_t DIV_Root_Result(void) +{ + if(DIV->CR & DIV_CR_ROOTMOD_Msk) + { + return DIV->ROOT; + } + else + { + return DIV->ROOT >> 16; + } +} + +#endif //__SWM221_DIV_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_dma.c b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_dma.c new file mode 100644 index 0000000..9f1ca6a --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_dma.c @@ -0,0 +1,159 @@ +/****************************************************************************************************************************************** +* ļ: SWM342_dma.c +* ˵: SWM342ƬDMA +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.0.0 2016130 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM221.h" +#include "SWM221_dma.h" + + +/****************************************************************************************************************************************** +* : DMA_CH_Init() +* ˵: DMAͨʼ +* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1 +* DMA_InitStructure * initStruct DMAͨ趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void DMA_CH_Init(uint32_t chn, DMA_InitStructure * initStruct) +{ + DMA_CH_Close(chn); //رպ + + DMA->CH[chn].CR = (initStruct->Mode << DMA_CR_CIRC_Pos) | + (initStruct->Unit << DMA_CR_MSIZ_Pos) | + (initStruct->Unit << DMA_CR_PSIZ_Pos) | + (initStruct->MemoryAddrInc << DMA_CR_MINC_Pos) | + (initStruct->PeripheralAddrInc << DMA_CR_PINC_Pos) | + (initStruct->Priority << DMA_CR_PL_Pos); + + DMA->CH[chn].NDT = ( initStruct->Count << DMA_NDT_LEN_Pos) | + ((initStruct->Count / 2) << DMA_NDT_HALF_Pos); + + DMA->CH[chn].MAR = initStruct->MemoryAddr; + DMA->CH[chn].PAR = initStruct->PeripheralAddr; + + switch(initStruct->Handshake & DMA_HS_MSK) + { + case DMA_HS_NO: + DMA->CH[chn].MUX = 0; + DMA->CH[chn].CR |= DMA_CR_DIR_Msk | DMA_CR_MEM2MEM_Msk; + break; + + case DMA_HS_MRD: + DMA->CH[chn].MUX = ((initStruct->Handshake & 0xF) << DMA_MUX_MRDHSSIG_Pos) | (1 << DMA_MUX_MRDHSEN_Pos); + DMA->CH[chn].CR |= DMA_CR_DIR_Msk; + break; + + case DMA_HS_MWR: + DMA->CH[chn].MUX = ((initStruct->Handshake & 0xF) << DMA_MUX_MWRHSSIG_Pos) | (1 << DMA_MUX_MWRHSEN_Pos); + DMA->CH[chn].CR &= ~DMA_CR_DIR_Msk; + break; + + case DMA_HS_EXT | DMA_HS_MRD: + DMA->CH[chn].MUX = ((initStruct->Handshake & 0xF) << DMA_MUX_EXTHSSIG_Pos) | (1 << DMA_MUX_EXTHSEN_Pos); + DMA->CH[chn].CR |= DMA_CR_DIR_Msk; + break; + + case DMA_HS_EXT | DMA_HS_MWR: + DMA->CH[chn].MUX = ((initStruct->Handshake & 0xF) << DMA_MUX_EXTHSSIG_Pos) | (1 << DMA_MUX_EXTHSEN_Pos); + DMA->CH[chn].CR &= ~DMA_CR_DIR_Msk; + break; + } + + DMA_CH_INTClr(chn, initStruct->INTEn); + DMA_CH_INTEn(chn, initStruct->INTEn); + + if(initStruct->INTEn) NVIC_EnableIRQ(GPIOB1_GPIOA9_DMA_IRQn); +} + +/****************************************************************************************************************************************** +* : DMA_CH_Open() +* ˵: DMAͨͨ䣻Ӳͨȳִźźſʼ +* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1 +* : +* ע: +******************************************************************************************************************************************/ +void DMA_CH_Open(uint32_t chn) +{ + DMA->CH[chn].CR |= DMA_CR_EN_Msk; +} + +/****************************************************************************************************************************************** +* : DMA_CH_Close() +* ˵: DMAͨر +* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1 +* : +* ע: +******************************************************************************************************************************************/ +void DMA_CH_Close(uint32_t chn) +{ + DMA->CH[chn].CR &= ~DMA_CR_EN_Msk; +} + + +/****************************************************************************************************************************************** +* : DMA_CH_INTEn() +* ˵: DMAжʹ +* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1 +* uint32_t it interrupt typeЧֵ DMA_IT_DONEDMA_IT_HALFDMA_IT_ERROR +* : +* ע: +******************************************************************************************************************************************/ +void DMA_CH_INTEn(uint32_t chn, uint32_t it) +{ + DMA->CH[chn].CR |= it; +} + +/****************************************************************************************************************************************** +* : DMA_CH_INTDis() +* ˵: DMAжϽֹ +* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1 +* uint32_t it interrupt typeЧֵ DMA_IT_DONEDMA_IT_HALFDMA_IT_ERROR +* : +* ע: +******************************************************************************************************************************************/ +void DMA_CH_INTDis(uint32_t chn, uint32_t it) +{ + DMA->CH[chn].CR &= ~it; +} + +/****************************************************************************************************************************************** +* : DMA_CH_INTClr() +* ˵: DMAжϱ־ +* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1 +* uint32_t it interrupt typeЧֵ DMA_IT_DONEDMA_IT_HALFDMA_IT_ERROR +* : +* ע: +******************************************************************************************************************************************/ +void DMA_CH_INTClr(uint32_t chn, uint32_t it) +{ + DMA->IFC = (it << (chn * 4)); +} + +/****************************************************************************************************************************************** +* : DMA_CH_INTStat() +* ˵: DMAж״̬ѯ +* : uint32_t chn ָҪõͨЧֵDMA_CH0DMA_CH1 +* uint32_t it interrupt typeЧֵ DMA_IT_DONEDMA_IT_HALFDMA_IT_ERROR +* : uint32_t 0 ָжδ 0 ָжѷ +* ע: +******************************************************************************************************************************************/ +uint32_t DMA_CH_INTStat(uint32_t chn, uint32_t it) +{ + return DMA->IF & (it << (chn * 4)); +} diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_dma.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_dma.h new file mode 100644 index 0000000..2fe7e6f --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_dma.h @@ -0,0 +1,128 @@ +#ifndef __SWM221_DMA_H__ +#define __SWM221_DMA_H__ + + +typedef struct { + uint8_t Mode; //DMA_MODE_SINGLEDMA_MODE_CIRCLE + + uint8_t Unit; //DMA_UNIT_BYTEDMA_UNIT_HALFWORDDMA_UNIT_WORD + + uint32_t Count; // Unit ȡֵ0xFFFF + + uint32_t MemoryAddr; + + uint32_t PeripheralAddr; + + uint8_t MemoryAddrInc; //0 ̶ַ 1 ַ + + uint8_t PeripheralAddrInc; + + uint8_t Handshake; //źţDMA_HS_NODMA_CH0_UART0TXDMA_CH0_SPI0TX... ... + + uint8_t Priority; //DMA_PRI_HIGHESTDMA_PRI_VERY_HIGH...DMA_PRI_LOWEST + + uint32_t INTEn; //жʹܣЧֵ DMA_IT_DONEDMA_IT_HALFDMA_IT_ERROR 䡰 +} DMA_InitStructure; + + +#define DMA_CH0 0 +#define DMA_CH1 1 + +#define DMA_MODE_SINGLE 0 // ģʽɺֹͣ +#define DMA_MODE_CIRCLE 1 // ģʽɺͷִһִ + +#define DMA_UNIT_BYTE 0 +#define DMA_UNIT_HALFWORD 1 +#define DMA_UNIT_WORD 2 + +#define DMA_PRI_HIGHEST 0 +#define DMA_PRI_VERY_HIGH 2 +#define DMA_PRI_HIGH 4 +#define DMA_PRI_LOW 11 +#define DMA_PRI_VERY_LOW 13 +#define DMA_PRI_LOWEST 15 + + +#define DMA_HS_NO (0 << 4) // źţ Memory to Memory 䣬PeripheralAddr Ŀĵַ +#define DMA_HS_MRD (1 << 4) // memory read handshake Memory to Peripheral +#define DMA_HS_MWR (2 << 4) // memory write handshake Peripheral to Memory +#define DMA_HS_EXT (4 << 4) // external handshake +#define DMA_HS_MSK (7 << 4) + +// memory read handshake signal +#define DMA_CH0_UART0TX (0 | DMA_HS_MRD) +#define DMA_CH0_SPI0TX (1 | DMA_HS_MRD) +#define DMA_CH0_QSPI0TX (2 | DMA_HS_MRD) + +#define DMA_CH1_USART0TX (0 | DMA_HS_MRD) +#define DMA_CH1_UART1TX (1 | DMA_HS_MRD) +#define DMA_CH1_MPUTX (2 | DMA_HS_MRD) + +// memory write handshake signal +#define DMA_CH0_USART0RX (0 | DMA_HS_MWR) +#define DMA_CH0_UART1RX (1 | DMA_HS_MWR) +#define DMA_CH0_MPURX (2 | DMA_HS_MWR) +#define DMA_CH0_ADC0SEQ1 (3 | DMA_HS_MWR) + +#define DMA_CH1_UART0RX (0 | DMA_HS_MWR) +#define DMA_CH1_SPI0RX (1 | DMA_HS_MWR) +#define DMA_CH1_QSPI0RX (2 | DMA_HS_MWR) +#define DMA_CH1_ADC1SEQ1 (3 | DMA_HS_MWR) + + +// ⲿź +#define DMA_EXMRD_TIMR0 (0 | DMA_HS_MRD | DMA_HS_EXT) +#define DMA_EXMRD_TIMR1 (1 | DMA_HS_MRD | DMA_HS_EXT) +#define DMA_EXMRD_TIMR2 (2 | DMA_HS_MRD | DMA_HS_EXT) +#define DMA_EXMRD_TIMR3 (3 | DMA_HS_MRD | DMA_HS_EXT) +#define DMA_EXMRD_TRIG0 (4 | DMA_HS_MRD | DMA_HS_EXT) // DMA_TRIG0 +#define DMA_EXMRD_TRIG1 (5 | DMA_HS_MRD | DMA_HS_EXT) // DMA_TRIG1 + +#define DMA_EXMWR_TIMR0 (0 | DMA_HS_MWR | DMA_HS_EXT) +#define DMA_EXMWR_TIMR1 (1 | DMA_HS_MWR | DMA_HS_EXT) +#define DMA_EXMWR_TIMR2 (2 | DMA_HS_MWR | DMA_HS_EXT) +#define DMA_EXMWR_TIMR3 (3 | DMA_HS_MWR | DMA_HS_EXT) +#define DMA_EXMWR_TRIG0 (4 | DMA_HS_MWR | DMA_HS_EXT) +#define DMA_EXMWR_TRIG1 (5 | DMA_HS_MWR | DMA_HS_EXT) + + + +/* Interrupt Type */ +#define DMA_IT_DONE (1 << 1) //Transfer Done +#define DMA_IT_HALF (1 << 2) //Transfer Half +#define DMA_IT_ERROR (1 << 3) //Transfer Error + + + +void DMA_CH_Init(uint32_t chn, DMA_InitStructure * initStruct); //DMAͨ +void DMA_CH_Open(uint32_t chn); +void DMA_CH_Close(uint32_t chn); + + +static inline void DMA_CH_SetCount(uint32_t chn, uint32_t count) +{ + DMA->CH[chn].NDT = ( count << DMA_NDT_LEN_Pos) | + ((count / 2) << DMA_NDT_HALF_Pos); +} + + +static inline uint32_t DMA_CH_GetRemaining(uint32_t chn) +{ + return (DMA->CH[chn].NDT & DMA_NDT_LEN_Msk); +} + + +static inline void DMA_CH_SetAddrAndCount(uint32_t chn, uint32_t addr, uint32_t count) +{ + DMA->CH[chn].MAR = addr; + + DMA_CH_SetCount(chn, count); +} + +void DMA_CH_INTEn(uint32_t chn, uint32_t it); //DMAжʹ +void DMA_CH_INTDis(uint32_t chn, uint32_t it); //DMAжϽֹ +void DMA_CH_INTClr(uint32_t chn, uint32_t it); //DMAжϱ־ +uint32_t DMA_CH_INTStat(uint32_t chn, uint32_t it); //DMAж״̬ѯ + + +#endif //__SWM221_DMA_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_exti.c b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_exti.c new file mode 100644 index 0000000..e12ec95 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_exti.c @@ -0,0 +1,131 @@ +/****************************************************************************************************************************************** +* ļ: SWM221_exti.c +* ˵: SWM221ƬⲿжϹ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.0.0 2016130 +* ¼: +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM221.h" +#include "SWM221_exti.h" + + +/****************************************************************************************************************************************** +* : EXTI_Init() +* ˵: ָⲿжϳʼ +* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOC +* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* uint32_t mode ЧֵEXTI_FALL_EDGEEXTI_RISE_EDGEEXTI_BOTH_EDGEEXTI_LOW_LEVELEXTI_HIGH_LEVEL +* : +* ע: +******************************************************************************************************************************************/ +void EXTI_Init(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t mode) +{ + EXTI_Close(GPIOx, n); //ùؼĴǰȹر + + if(mode & 0x10) + { + GPIOx->INTLVLTRG |= (0x01 << n); //ƽ + + if(mode & 0x01) + GPIOx->INTRISEEN |= (0x01 << n); //ߵƽ + else + GPIOx->INTRISEEN &= ~(0x01 << n); //͵ƽ + } + else + { + GPIOx->INTLVLTRG &= ~(0x01 << n); //ش + + if(mode & 0x02) + { + GPIOx->INTBE |= (0x01 << n); //˫ش + } + else + { + GPIOx->INTBE &= ~(0x01 << n); //ش + + if(mode & 0x01) + GPIOx->INTRISEEN |= (0x01 << n); //ش + else + GPIOx->INTRISEEN &= ~(0x01 << n); //½ش + } + } + + GPIOx->INTCLR = (1 << n); //Ϊģʽÿܲж +} + +/****************************************************************************************************************************************** +* : EXTI_Open() +* ˵: ָⲿжϴ򿪣ʹܣ +* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOC +* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* : +* ע: +******************************************************************************************************************************************/ +void EXTI_Open(GPIO_TypeDef * GPIOx, uint32_t n) +{ + GPIOx->INTEN |= (0x01 << n); +} + +/****************************************************************************************************************************************** +* : EXTI_Close() +* ˵: ָⲿжϹرգܣ +* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOC +* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* : +* ע: +******************************************************************************************************************************************/ +void EXTI_Close(GPIO_TypeDef * GPIOx, uint32_t n) +{ + GPIOx->INTEN &= ~(0x01 << n); +} + +/****************************************************************************************************************************************** +* : EXTI_State() +* ˵: ָǷ񴥷ж +* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOC +* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* : uint32_t 1 Ŵж 0 δж +* ע: +******************************************************************************************************************************************/ +uint32_t EXTI_State(GPIO_TypeDef * GPIOx, uint32_t n) +{ + return (GPIOx->INTSTAT >> n) & 0x01; +} + +/****************************************************************************************************************************************** +* : EXTI_RawState() +* ˵: ָǷ/жϴжϹرʱͨô˺ԲѯķʽǷ/жϴ +* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOC +* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* : uint32_t 1 /жϴ 0 δ/жϴ +* ע: +******************************************************************************************************************************************/ +uint32_t EXTI_RawState(GPIO_TypeDef * GPIOx, uint32_t n) +{ + return (GPIOx->INTRAWSTAT >> n) & 0x01; +} + +/****************************************************************************************************************************************** +* : EXTI_Clear() +* ˵: ָⲿжжϱ־ٴνжϣ +* : GPIO_TypeDef * GPIOx ָⲿжϵGPIO˿ڣЧֵGPIOAGPIOBGPIOC +* uint32_t n ָⲿжϵGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* : +* ע: ֻشжϵı־ƽжϵı־޷ֻŵƽжϴӲԶ +******************************************************************************************************************************************/ +void EXTI_Clear(GPIO_TypeDef * GPIOx, uint32_t n) +{ + GPIOx->INTCLR = (0x01 << n); +} diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_exti.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_exti.h new file mode 100644 index 0000000..eb75bc8 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_exti.h @@ -0,0 +1,20 @@ +#ifndef __SWM221_EXTI_H__ +#define __SWM221_EXTI_H__ + +void EXTI_Init(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t mode); //ָⲿжϳʼ +void EXTI_Open(GPIO_TypeDef * GPIOx, uint32_t n); //ָⲿжϴ򿪣ʹܣ +void EXTI_Close(GPIO_TypeDef * GPIOx, uint32_t n); //ָⲿжϹرգܣ + +uint32_t EXTI_State(GPIO_TypeDef * GPIOx, uint32_t n); //ָǷ񴥷ж +uint32_t EXTI_RawState(GPIO_TypeDef * GPIOx, uint32_t n); //ָǷ/жϴжϹرʱͨô˺ԲѯķʽǷ/жϴ +void EXTI_Clear(GPIO_TypeDef * GPIOx, uint32_t n); //ָⲿжжϱ־ٴνжϣ + + +#define EXTI_FALL_EDGE 0x00 //½شж +#define EXTI_RISE_EDGE 0x01 //شж +#define EXTI_BOTH_EDGE 0x02 //˫شж +#define EXTI_LOW_LEVEL 0x10 //͵ƽж +#define EXTI_HIGH_LEVEL 0x11 //ߵƽж + + +#endif //__SWM221_EXTI_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_flash.c b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_flash.c new file mode 100644 index 0000000..edd641a --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_flash.c @@ -0,0 +1,166 @@ +/****************************************************************************************************************************************** +* ļ: SWM221_flash.c +* ˵: ʹоƬIAPܽƬFlashģEEPROMݣ󲻶ʧ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.0.0 2016130 +* ¼: +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM221.h" +#include "SWM221_flash.h" + + +typedef int (*IAP_Flash_Param_t)(uint32_t param, uint32_t flag); +typedef int (*IAP_Flash_Erase_t)(uint32_t sector, uint32_t flag); +typedef int (*IAP_Flash_Write_t)(uint32_t flash_addr, uint32_t ram_addr, uint32_t count, uint32_t flag); + + +IAP_Flash_Erase_t IAP_Flash_Erase = (IAP_Flash_Erase_t)0x01000401; +IAP_Flash_Write_t IAP_Flash_Write = (IAP_Flash_Write_t)0x01000461; +IAP_Flash_Param_t IAP_Flash_Param = (IAP_Flash_Param_t)0x010004D1; + + +/****************************************************************************************************************************************** +* : FLASH_Erase() +* ˵: ƬFlash +* : uint32_t addr ַСΪ512 Byte +* : uint32_t FLASH_RES_OKFLASH_RES_TOFLASH_RES_ERR +* ע: +******************************************************************************************************************************************/ +uint32_t FLASH_Erase(uint32_t addr) +{ + __disable_irq(); + + IAP_Flash_Erase(addr / 0x200, 0x0B11FFAC); + + Cache_Clear(); + + __enable_irq(); + + return FLASH_RES_OK; +} + + +/****************************************************************************************************************************************** +* : FLASH_Write() +* ˵: ƬFlashд +* : uint32_t addr дַ +* uint32_t buff[] Ҫд +* uint32_t count ҪдݵĸΪλұ2д2 +* : uint32_t FLASH_RES_OKFLASH_RES_TOFLASH_RES_ERR +* ע: дݸ2д2 +******************************************************************************************************************************************/ +uint32_t FLASH_Write(uint32_t addr, uint32_t buff[], uint32_t count) +{ + __disable_irq(); + + IAP_Flash_Write(addr, (uint32_t)buff, count/2, 0x0B11FFAC); + + Cache_Clear(); + + __enable_irq(); + + return FLASH_RES_OK; +} + + +/****************************************************************************************************************************************** +* : Flash_Param_at_xMHz() +* ˵: FlashóxMHzƵʱIJ +* : uint32_t x ϵͳƵλMHz +* : +* ע: +******************************************************************************************************************************************/ +void Flash_Param_at_xMHz(uint32_t x) +{ + __disable_irq(); + + IAP_Flash_Param(1000 / x, 0x0B11FFAC); + + __enable_irq(); +} + + +#if defined ( __CC_ARM ) || defined (__ARMCC_VERSION) + +/* Code_Cache_Clear Ǵ˺ɵָ +__asm void Cache_Clear(void) +{ + NOP + NOP + NOP + NOP + MOVS R0, #0x40 // 0x40045000 + LSLS R0, R0, #8 + ADDS R0, R0, #0x04 + LSLS R0, R0, #8 + ADDS R0, R0, #0x50 + LSLS R0, R0, #8 + LDR R1,[R0, #0xC] + MOVS R2, #1 + LSLS R2, R2, #31 + ORRS R1, R1, R2 + STR R1,[R0, #0xC] + NOP + NOP + NOP + NOP + BX LR +} +*/ +uint16_t Code_Cache_Clear[] = { + 0xBF00, 0xBF00, 0xBF00, 0xBF00, 0x2040, 0x0200, 0x1D00, 0x0200, + 0x3050, 0x0200, 0x68C1, 0x2201, 0x07D2, 0x4311, 0x60C1, 0xBF00, + 0xBF00, 0xBF00, 0xBF00, 0x4770, +}; + +#if defined ( __CC_ARM ) +__asm void Cache_Clear(void) // AC5 +{ + IMPORT Code_Cache_Clear + PUSH {LR} + NOP + LDR R0,=Code_Cache_Clear + ADDS R0, R0, #1 + NOP + BLX R0 + POP {R0} + BX R0 +} +#else +void Cache_Clear(void) // AC6 +{ +__asm( + "PUSH {LR}\n" + "NOP\n" + "LDR R0,=Code_Cache_Clear\n" + "ADDS R0, R0, #1\n" + "NOP\n" + "BLX R0\n" + "POP {R0}\n" + "BX R0\n"); +} +#endif + +#elif defined ( __ICCARM__ ) + +__ramfunc void Cache_Clear(void) +{ + __NOP(); __NOP(); __NOP(); __NOP(); + + FMC->CACHE |= FMC_CACHE_CCLR_Msk; // Cache Clear + + __NOP(); __NOP(); __NOP(); __NOP(); +} + +#endif diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_flash.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_flash.h new file mode 100644 index 0000000..660d2dd --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_flash.h @@ -0,0 +1,19 @@ +#ifndef __SWM221_FLASH_H__ +#define __SWM221_FLASH_H__ + + +uint32_t FLASH_Erase(uint32_t addr); +uint32_t FLASH_Write(uint32_t addr, uint32_t buff[], uint32_t cnt); +void Flash_Param_at_xMHz(uint32_t x); +void Cache_Clear(void); + + +#define FLASH_SECTOR_SIZE 512 + + +#define FLASH_RES_OK 0 +#define FLASH_RES_TO 1 //Timeout +#define FLASH_RES_ERR 2 + + +#endif //__SWM221_FLASH_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_gpio.c b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_gpio.c new file mode 100644 index 0000000..bd62556 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_gpio.c @@ -0,0 +1,263 @@ +/****************************************************************************************************************************************** +* ļ: SWM221_gpio.c +* ˵: SWM221Ƭͨ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.0.0 2016130 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM221.h" +#include "SWM221_gpio.h" + + +/****************************************************************************************************************************************** +* : GPIO_Init() +* ˵: ųʼŷ© +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOC +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* uint32_t dir ŷ0 1 +* uint32_t pull_up ʹ +* uint32_t pull_down ʹ +* uint32_t open_drain ©ʹ +* : +* ע: +******************************************************************************************************************************************/ +void GPIO_Init(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, uint32_t pull_down, uint32_t open_drain) +{ + PORT_TypeDef * PORTx = PORTA; + + switch((uint32_t)GPIOx) + { + case ((uint32_t)GPIOA): + SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_GPIOA_Pos); + + PORTx = PORTA; + break; + + case ((uint32_t)GPIOB): + SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_GPIOB_Pos); + + PORTx = PORTB; + break; + + case ((uint32_t)GPIOC): + SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_GPIOC_Pos); + + PORTx = PORTC; + break; + } + + PORT_Init(PORTx, n, 0, 1); //PORTx.PINnΪGPIOܣ뿪 + if(dir == 1) + { + GPIOx->DIR |= (0x01 << n); + } + else + { + GPIOx->DIR &= ~(0x01 << n); + } + + if(pull_up == 1) PORTx->PULLU |= (1 << n); + else PORTx->PULLU &= ~(1 << n); + if(pull_down == 1) PORTx->PULLD |= (1 << n); + else PORTx->PULLD &= ~(1 << n); + if(open_drain == 1) PORTx->OPEND |= (1 << n); + else PORTx->OPEND &= ~(1 << n); +} + +/****************************************************************************************************************************************** +* : GPIO_SetBit() +* ˵: ָŵƽø +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOC +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* : +* ע: +******************************************************************************************************************************************/ +void GPIO_SetBit(GPIO_TypeDef * GPIOx, uint32_t n) +{ + *(&GPIOx->DATAPIN0 + n) = 1; +} + +/****************************************************************************************************************************************** +* : GPIO_ClrBit() +* ˵: ָŵƽõ +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOC +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* : +* ע: +******************************************************************************************************************************************/ +void GPIO_ClrBit(GPIO_TypeDef * GPIOx, uint32_t n) +{ + *(&GPIOx->DATAPIN0 + n) = 0; +} + +/****************************************************************************************************************************************** +* : GPIO_InvBit() +* ˵: ָŵƽת +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOC +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* : +* ע: +******************************************************************************************************************************************/ +void GPIO_InvBit(GPIO_TypeDef * GPIOx, uint32_t n) +{ + *(&GPIOx->DATAPIN0 + n) = 1 - *(&GPIOx->DATAPIN0 + n); +} + +/****************************************************************************************************************************************** +* : GPIO_GetBit() +* ˵: ȡָŵĵƽ״̬ +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOC +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* : ָŵĵƽ״̬ 0 ͵ƽ 1 ߵƽ +* ע: +******************************************************************************************************************************************/ +uint32_t GPIO_GetBit(GPIO_TypeDef * GPIOx, uint32_t n) +{ + return *(&GPIOx->DATAPIN0 + n); +} + +/****************************************************************************************************************************************** +* : GPIO_SetBits() +* ˵: ָĴnʼwλŵĵƽø +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOC +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* uint32_t w ָҪŵƽøߵŵĸ +* : +* ע: +******************************************************************************************************************************************/ +void GPIO_SetBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFF >> (16 - w); + + GPIOx->ODR |= (bits << n); +} + +/****************************************************************************************************************************************** +* : GPIO_ClrBits() +* ˵: ָĴnʼwλŵĵƽõ +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOC +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* uint32_t w ָҪŵƽõ͵ŵĸ +* : +* ע: +******************************************************************************************************************************************/ +void GPIO_ClrBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFF >> (16 - w); + + GPIOx->ODR &= ~(bits << n); +} + +/****************************************************************************************************************************************** +* : GPIO_InvBits() +* ˵: ָĴnʼwλŵĵƽת +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOC +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* uint32_t w ָҪŵƽתŵĸ +* : +* ע: +******************************************************************************************************************************************/ +void GPIO_InvBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFF >> (16 - w); + + GPIOx->ODR ^= (bits << n); +} + +/****************************************************************************************************************************************** +* : GPIO_GetBits() +* ˵: ȡָĴnʼwλŵĵƽ״̬ +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOC +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* uint32_t w ָҪŵƽøߵŵĸ +* : ָĴnʼwλŵĵƽ״̬ 0 ͵ƽ 1 ߵƽ +* ֵĵ0λʾnĵƽ״ֵ̬ĵ1λʾn+1ĵƽ״̬... ...ֵĵwλʾn+wĵƽ״̬ +* ע: +******************************************************************************************************************************************/ +uint32_t GPIO_GetBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFF >> (16 - w); + + return ((GPIOx->IDR >> n) & bits); +} + +/****************************************************************************************************************************************** +* : GPIO_AtomicSetBits() +* ˵: ָĴnʼwλŵĵƽøߣȷš--дԭԣжISRϣ +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOC +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* uint32_t w ָҪŵƽøߵŵĸ +* : +* ע: GPIOx16УЩѭвЩжISRвʱGPIOxű붼GPIO_Atomicͺ +******************************************************************************************************************************************/ +void GPIO_AtomicSetBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFF >> (16 - w); + + __disable_irq(); + GPIOx->ODR |= (bits << n); + __enable_irq(); +} + +/****************************************************************************************************************************************** +* : GPIO_AtomicClrBits() +* ˵: ָĴnʼwλŵĵƽõͣȷš--дԭԣжISRϣ +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOC +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* uint32_t w ָҪŵƽõ͵ŵĸ +* : +* ע: GPIOx16УЩѭвЩжISRвʱGPIOxű붼GPIO_Atomicͺ +******************************************************************************************************************************************/ +void GPIO_AtomicClrBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFF >> (16 - w); + + __disable_irq(); + GPIOx->ODR &= ~(bits << n); + __enable_irq(); +} + +/****************************************************************************************************************************************** +* : GPIO_AtomicInvBits() +* ˵: ָĴnʼwλŵĵƽתȷš--дԭԣжISRϣ +* : GPIO_TypeDef * GPIOx ָGPIO˿ڣЧֵGPIOAGPIOBGPIOC +* uint32_t n ָGPIOţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* uint32_t w ָҪŵƽתŵĸ +* : +* ע: GPIOx16УЩѭвЩжISRвʱGPIOxű붼GPIO_Atomicͺ +******************************************************************************************************************************************/ +void GPIO_AtomicInvBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w) +{ + uint32_t bits; + + bits = 0xFFFF >> (16 - w); + + __disable_irq(); + GPIOx->ODR ^= (bits << n); + __enable_irq(); +} diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_gpio.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_gpio.h new file mode 100644 index 0000000..3724ee1 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_gpio.h @@ -0,0 +1,38 @@ +#ifndef __SWM221_GPIO_H__ +#define __SWM221_GPIO_H__ + + +void GPIO_Init(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t dir, uint32_t pull_up, uint32_t pull_down, uint32_t open_drain); //ųʼŷ© + +#define GPIO_INPUT ((0 << 0) | (0 << 1) | (0 << 2) | (0 << 3)) +#define GPIO_INPUT_PullUp ((0 << 0) | (1 << 1) | (0 << 2) | (0 << 3)) +#define GPIO_INPUT_PullDown ((0 << 0) | (0 << 1) | (1 << 2) | (0 << 3)) +#define GPIO_OUTPUT ((1 << 0) | (0 << 1) | (0 << 2) | (0 << 3)) +#define GPIO_OUTPUT_OpenDrain ((1 << 0) | (0 << 1) | (0 << 2) | (1 << 3)) +#define GPIO_OUTPUT_OpenDrain_PullUp ((1 << 0) | (1 << 1) | (0 << 2) | (1 << 3)) + +#define GPIO_INIT(GPIOx, n, mode) GPIO_Init(GPIOx, n, (mode & 1) ? 1 : 0, (mode & 2) ? 1 : 0, (mode & 4) ? 1 : 0, (mode & 8) ? 1 : 0) + + +void GPIO_SetBit(GPIO_TypeDef * GPIOx, uint32_t n); //ָŵƽø +void GPIO_ClrBit(GPIO_TypeDef * GPIOx, uint32_t n); //ָŵƽõ +void GPIO_InvBit(GPIO_TypeDef * GPIOx, uint32_t n); //ָŵƽת +uint32_t GPIO_GetBit(GPIO_TypeDef * GPIOx, uint32_t n); //ȡָŵĵƽ״̬ +void GPIO_SetBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w); //ָĴnʼwλŵĵƽø +void GPIO_ClrBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w); //ָĴnʼwλŵĵƽõ +void GPIO_InvBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w); //ָĴnʼwλŵĵƽת +uint32_t GPIO_GetBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w); //ȡָĴnʼwλŵĵƽ״̬ + + +void GPIO_AtomicSetBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w); +void GPIO_AtomicClrBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w); +void GPIO_AtomicInvBits(GPIO_TypeDef * GPIOx, uint32_t n, uint32_t w); + + +// for compatibility +#define GPIO_AtomicSetBit GPIO_SetBit +#define GPIO_AtomicClrBit GPIO_ClrBit +#define GPIO_AtomicInvBit GPIO_InvBit + + +#endif //__SWM221_GPIO_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_i2c.c b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_i2c.c new file mode 100644 index 0000000..d09e2f3 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_i2c.c @@ -0,0 +1,308 @@ +/****************************************************************************************************************************************** +* ļ: SWM221_i2c.c +* ˵: SWM221ƬI2Cнӿڹ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.0.0 2016130 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIES AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIEE. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIES ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM221.h" +#include "SWM221_i2c.h" + + +/****************************************************************************************************************************************** +* : I2C_Init() +* ˵: I2Cʼ +* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0 +* I2C_InitStructure * initStruct I2C趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void I2C_Init(I2C_TypeDef * I2Cx, I2C_InitStructure * initStruct) +{ + switch((uint32_t)I2Cx) + { + case ((uint32_t)I2C0): + SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_I2C0_Pos); + break; + } + + __NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP();__NOP(); + + I2C_Close(I2Cx); //һЩؼĴֻI2Cرʱ + + if(initStruct->Master == 1) + { + int total_clkdiv, clkdiv, scl_hi = 0; + + I2Cx->CR |= (1 << I2C_CR_MASTER_Pos); + + total_clkdiv = SystemCoreClock / initStruct->MstClk; + if(total_clkdiv < 17) + total_clkdiv = 17; //޷ָƵʣӽƵ + + do { + scl_hi++; + clkdiv = (total_clkdiv - 14) / (scl_hi + scl_hi * 2); + } while(clkdiv > 256); + + I2Cx->CLK = ((scl_hi * 2 - 1) << I2C_CLK_SCLL_Pos) | + ((scl_hi - 1) << I2C_CLK_SCLH_Pos) | + ((clkdiv - 1) << I2C_CLK_DIV_Pos); + + I2Cx->IF = 0xFFFFFFFF; + I2Cx->IE = (initStruct->TXEmptyIEn << I2C_IE_TXE_Pos) | + (initStruct->RXNotEmptyIEn << I2C_IE_RXNE_Pos); + + switch((uint32_t)I2Cx) + { + case ((uint32_t)I2C0): + if(initStruct->TXEmptyIEn | initStruct->RXNotEmptyIEn) + { + NVIC_EnableIRQ(I2C0_IRQn); + } + else + { + NVIC_DisableIRQ(I2C0_IRQn); + } + break; + } + } + else + { + I2Cx->CR &= ~(1 << I2C_CR_MASTER_Pos); + + I2Cx->SCR &= ~I2C_SCR_ADDR10_Msk; + I2Cx->SCR |= (initStruct->Addr10b << I2C_SCR_ADDR10_Pos); + + if(initStruct->Addr10b) + I2Cx->SADDR = (initStruct->SlvAddr << I2C_SADDR_ADDR10_Pos) | + (initStruct->SlvAddrMsk << I2C_SADDR_MASK10_Pos); + else + I2Cx->SADDR = (initStruct->SlvAddr << I2C_SADDR_ADDR7_Pos) | + (initStruct->SlvAddrMsk << I2C_SADDR_MASK7_Pos); + + I2Cx->IF = 0xFFFFFFFF; + I2Cx->IE = (initStruct->TXEmptyIEn << I2C_IE_TXE_Pos) | + (initStruct->RXNotEmptyIEn << I2C_IE_RXNE_Pos) | + (initStruct->SlvSTADetIEn << I2C_IE_RXSTA_Pos) | + (initStruct->SlvSTODetIEn << I2C_IE_RXSTO_Pos); + + switch((uint32_t)I2Cx) + { + case ((uint32_t)I2C0): + if(initStruct->SlvSTADetIEn | initStruct->SlvSTODetIEn | initStruct->TXEmptyIEn | initStruct->RXNotEmptyIEn) + { + NVIC_EnableIRQ(I2C0_IRQn); + } + else + { + NVIC_DisableIRQ(I2C0_IRQn); + } + break; + } + } +} + +/****************************************************************************************************************************************** +* : I2C_Open() +* ˵: I2C򿪣շ +* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0 +* : +* ע: +******************************************************************************************************************************************/ +void I2C_Open(I2C_TypeDef * I2Cx) +{ + I2Cx->CR |= (0x01 << I2C_CR_EN_Pos); +} + +/****************************************************************************************************************************************** +* : I2C_Close() +* ˵: I2Cرգֹշ +* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0 +* : +* ע: +******************************************************************************************************************************************/ +void I2C_Close(I2C_TypeDef * I2Cx) +{ + I2Cx->CR &= ~(0x01 << I2C_CR_EN_Pos); +} + +/****************************************************************************************************************************************** +* : I2C_Start() +* ˵: ʼźŲ豸ַ +* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0I2C1 +* uint8_t addr 豸ַ +* uint8_t wait Ƿȴɣ1 ȴ 0 ȴ +* : uint8_t 1 յACK 0 յNACK +* ע: ѡ񲻵ȴأ򷵻ֵ壻ͨ I2C_StartDone() ѯǷɣɺ I2C_IsAck() ѯյACKNACK +******************************************************************************************************************************************/ +uint8_t I2C_Start(I2C_TypeDef * I2Cx, uint8_t addr, uint8_t wait) +{ + I2Cx->TXDATA = addr; + I2Cx->MCR = (1 << I2C_MCR_STA_Pos) | + (1 << I2C_MCR_WR_Pos); //ʼλʹӻַ + + if(wait == 0) + return 0; + + while(I2Cx->MCR & I2C_MCR_WR_Msk) __NOP(); //ȴ + + return (I2Cx->TR & I2C_TR_RXACK_Msk) ? 0 : 1; +} + +uint8_t I2C_StartDone(I2C_TypeDef * I2Cx) +{ + return (I2Cx->MCR & I2C_MCR_WR_Msk) ? 0 : 1; +} + +uint8_t I2C_IsAck(I2C_TypeDef * I2Cx) +{ + return (I2Cx->TR & I2C_TR_RXACK_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* : I2C_Stop() +* ˵: ֹͣź +* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0I2C1 +* uint8_t wait Ƿȴɣ1 ȴ 0 ȴ +* : +* ע: ѡ񲻵ȴأͨ I2C_StopDone() ѯǷ +******************************************************************************************************************************************/ +void I2C_Stop(I2C_TypeDef * I2Cx, uint8_t wait) +{ + I2Cx->MCR = (1 << I2C_MCR_STO_Pos); + + if(wait == 0) + return; + + while(I2Cx->MCR & I2C_MCR_STO_Msk) __NOP(); //ȴ +} + +uint8_t I2C_StopDone(I2C_TypeDef * I2Cx) +{ + return (I2Cx->MCR & I2C_MCR_STO_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* : I2C_Write() +* ˵: дһ +* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0I2C1 +* uint8_t data Ҫд +* uint8_t wait Ƿȴɣ1 ȴ 0 ȴ +* : uint8_t 1 յACK 0 յNACK +* ע: ѡ񲻵ȴأ򷵻ֵ壻ͨ I2C_WriteDone() ѯǷɣɺ I2C_IsAck() ѯյACKNACK +******************************************************************************************************************************************/ +uint8_t I2C_Write(I2C_TypeDef * I2Cx, uint8_t data, uint8_t wait) +{ + I2Cx->TXDATA = data; + I2Cx->MCR = (1 << I2C_MCR_WR_Pos); + + if(wait == 0) + return 0; + + while(I2Cx->MCR & I2C_MCR_WR_Msk) __NOP(); //ȴ + + return (I2Cx->TR & I2C_TR_RXACK_Msk) ? 0 : 1; +} + +uint8_t I2C_WriteDone(I2C_TypeDef * I2Cx) +{ + return (I2Cx->MCR & I2C_MCR_WR_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* : I2C_Read() +* ˵: ȡһ +* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0I2C1 +* uint8_t ack 1 ACK 0 NACK +* uint8_t wait Ƿȴɣ1 ȴ 0 ȴ +* : uint8_t ȡ +* ע: ѡ񲻵ȴأ򷵻ֵ壻ͨ I2C_ReadDone() ѯǷɣɺͨ I2Cx->RXDATA ȡȡ +******************************************************************************************************************************************/ +uint8_t I2C_Read(I2C_TypeDef * I2Cx, uint8_t ack, uint8_t wait) +{ + I2Cx->TR = ((ack ? 0 : 1) << I2C_TR_TXACK_Pos); + + I2Cx->MCR = (1 << I2C_MCR_RD_Pos); + + if(wait == 0) + return 0; + + while(I2Cx->MCR & I2C_MCR_RD_Msk) __NOP(); //ȴ + + return I2Cx->RXDATA; +} + +uint8_t I2C_ReadDone(I2C_TypeDef * I2Cx) +{ + return (I2Cx->MCR & I2C_MCR_RD_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* : I2C_INTEn() +* ˵: жʹ +* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0 +* uint32_t it interrupt typeЧֵI2C_IT_TX_EMPTYI2C_IT_RX_NOT_EMPTYI2C_IT_RX_OVFI2C_IT_TX_DONEI2C_IT_RX_DONE +* I2C_IT_SLV_DET_STAI2C_IT_SLV_DET_STPI2C_IT_ARB_LOSTI2C_IT_SCL_LOW_TO 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void I2C_INTEn(I2C_TypeDef * I2Cx, uint32_t it) +{ + I2Cx->IE |= it; +} + +/****************************************************************************************************************************************** +* : I2C_INTDis() +* ˵: жϽֹ +* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0 +* uint32_t it interrupt typeЧֵI2C_IT_TX_EMPTYI2C_IT_RX_NOT_EMPTYI2C_IT_RX_OVFI2C_IT_TX_DONEI2C_IT_RX_DONE +* I2C_IT_SLV_DET_STAI2C_IT_SLV_DET_STPI2C_IT_ARB_LOSTI2C_IT_SCL_LOW_TO 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void I2C_INTDis(I2C_TypeDef * I2Cx, uint32_t it) +{ + I2Cx->IE &= ~it; +} + +/****************************************************************************************************************************************** +* : I2C_INTClr() +* ˵: жϱ־ +* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0 +* uint32_t it interrupt typeЧֵI2C_IT_TX_EMPTYI2C_IT_RX_NOT_EMPTYI2C_IT_RX_OVFI2C_IT_TX_DONEI2C_IT_RX_DONE +* I2C_IT_SLV_DET_STAI2C_IT_SLV_DET_STPI2C_IT_ARB_LOSTI2C_IT_SCL_LOW_TO 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void I2C_INTClr(I2C_TypeDef * I2Cx, uint32_t it) +{ + I2Cx->IF = it; +} + +/****************************************************************************************************************************************** +* : I2C_INTStat() +* ˵: ж״̬ѯ +* : I2C_TypeDef * I2Cx ָҪõI2CЧֵI2C0 +* uint32_t it interrupt typeЧֵI2C_IT_TX_EMPTYI2C_IT_RX_NOT_EMPTYI2C_IT_RX_OVFI2C_IT_TX_DONEI2C_IT_RX_DONE +* I2C_IT_SLV_DET_STAI2C_IT_SLV_DET_STPI2C_IT_ARB_LOSTI2C_IT_SCL_LOW_TO 䡰 +* : uint32_t 1 жϷ 0 жδ +* ע: +******************************************************************************************************************************************/ +uint32_t I2C_INTStat(I2C_TypeDef * I2Cx, uint32_t it) +{ + return (I2Cx->IF & it) ? 1 : 0; +} diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_i2c.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_i2c.h new file mode 100644 index 0000000..ebe8e75 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_i2c.h @@ -0,0 +1,53 @@ +#ifndef __SWM221_I2C_H__ +#define __SWM221_I2C_H__ + +typedef struct { + uint8_t Master; //1 ģʽ 0 ӻģʽ + uint32_t MstClk; //ʱƵ + + uint8_t Addr10b; //1 10λַģʽ 0 7λַģʽ + uint16_t SlvAddr; //ӻַ + uint16_t SlvAddrMsk; + + uint8_t TXEmptyIEn; //ͼĴжʹ + uint8_t RXNotEmptyIEn; //ռĴǿжʹ + uint8_t SlvSTADetIEn; //ӻ⵽ʼжʹ + uint8_t SlvSTODetIEn; //ӻ⵽ֹжʹ +} I2C_InitStructure; + + +/* Interrupt Type */ +#define I2C_IT_TX_EMPTY (1 << 0) //TX FIFO Empty +#define I2C_IT_RX_NOT_EMPTY (1 << 1) //RX FIFO Not Empty +#define I2C_IT_RX_OVF (1 << 2) //RX FIFO Overflow +#define I2C_IT_TX_DONE (1 << 3) //ɣյACK +#define I2C_IT_RX_DONE (1 << 4) //ɣͳACK +#define I2C_IT_SLV_DET_STA (1 << 8) //ӻ⵽ʼλ +#define I2C_IT_SLV_DET_STP (1 << 9) //ӻ⵽ֹͣλ +#define I2C_IT_ARB_LOST (1 << 16) //Arbitration lost +#define I2C_IT_SCL_LOW_TO (1 << 17) //SCL Low Timeout + + +void I2C_Init(I2C_TypeDef * I2Cx, I2C_InitStructure * initStruct); + +void I2C_Open(I2C_TypeDef * I2Cx); +void I2C_Close(I2C_TypeDef * I2Cx); + +uint8_t I2C_Start(I2C_TypeDef * I2Cx, uint8_t addr, uint8_t wait); +void I2C_Stop(I2C_TypeDef * I2Cx, uint8_t wait); +uint8_t I2C_Write(I2C_TypeDef * I2Cx, uint8_t data, uint8_t wait); +uint8_t I2C_Read(I2C_TypeDef * I2Cx, uint8_t ack, uint8_t wait); + +uint8_t I2C_StartDone(I2C_TypeDef * I2Cx); +uint8_t I2C_StopDone(I2C_TypeDef * I2Cx); +uint8_t I2C_WriteDone(I2C_TypeDef * I2Cx); +uint8_t I2C_ReadDone(I2C_TypeDef * I2Cx); +uint8_t I2C_IsAck(I2C_TypeDef * I2Cx); + +void I2C_INTEn(I2C_TypeDef * I2Cx, uint32_t it); //жʹ +void I2C_INTDis(I2C_TypeDef * I2Cx, uint32_t it); //жϽֹ +void I2C_INTClr(I2C_TypeDef * I2Cx, uint32_t it); //жϱ־ +uint32_t I2C_INTStat(I2C_TypeDef * I2Cx, uint32_t it); //ж״̬ѯ + + +#endif //__SWM221_I2C_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_iofilt.c b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_iofilt.c new file mode 100644 index 0000000..adf4975 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_iofilt.c @@ -0,0 +1,46 @@ +/****************************************************************************************************************************************** +* ļ: SWM221_iofilt.c +* ˵: SWM221ƬIO˲ģ飬PADģź˲խָȵẹ̈ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.0.0 2016130 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM221.h" +#include "SWM221_iofilt.h" + + +/****************************************************************************************************************************************** +* : IOFILT_Init() +* ˵: IO˲ʼ +* : uint32_t IOFILTn Ҫʼ˲ȡֵ 0-1 +* uint32_t signal ҪЩźŽ˲ IOFILTn = 0 ʱȡֵ IOFILT0_PB14IOFILT0_PB4IOFILT0_PB5IOFILT0_PB6 䡰 +* IOFILTn = 1 ʱȡֵ IOFILT1_ACMP0IOFILT1_ACMP1 䡰 +* uint32_t width ѡźϿС width 屻ẹ̈˵ȡֵ IOFILT_WIDTH_250nsIOFILT_WIDTH_500ns... +* : +* ע: +******************************************************************************************************************************************/ +void IOFILT_Init(uint32_t IOFILTn, uint32_t signal, uint32_t width) +{ + SYS->CLKSEL &= ~SYS_CLKSEL_IOFILT_Msk; + SYS->CLKSEL |= (0 << SYS_CLKSEL_IOFILT_Pos); //˲ʱԴHRC + + SYS->CLKEN0 |= SYS_CLKEN0_IOFILT_Msk; + for(int i = 0; i < 10; i++) __NOP(); + + *(&SYS->IOFILT0 + IOFILTn) = (signal << SYS_IOFILT_IO0EN_Pos) | + (0 << SYS_IOFILT_CLKDIV_Pos) | + (width << SYS_IOFILT_TIM_Pos); +} diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_iofilt.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_iofilt.h new file mode 100644 index 0000000..325dde3 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_iofilt.h @@ -0,0 +1,35 @@ +#ifndef __SWM221_IOFILT_H__ +#define __SWM221_IOFILT_H__ + + +/* ѡĸźŽ˲ */ +#define IOFILT0_PB14 1 +#define IOFILT0_PB4 2 +#define IOFILT0_PB5 4 +#define IOFILT0_PB6 8 + +#define IOFILT1_ACMP0 1 // ACMP0_OUT ˲ACMP0 ״̬SYS->ACMPSR.CMP0OUTжϣSYS->ACMPSR.CMP0IFΪ PWM ɲźž˲ +#define IOFILT1_ACMP1 2 + +#define IOFILT_WIDTH_250ns 1 // ˲ʱԴΪ HRC ˲ʱӲƵʱÿ˲Ϊ 1/8MHz = 125ns +#define IOFILT_WIDTH_500ns 2 +#define IOFILT_WIDTH_1us 3 +#define IOFILT_WIDTH_2us 4 +#define IOFILT_WIDTH_4us 5 +#define IOFILT_WIDTH_8us 6 +#define IOFILT_WIDTH_16us 7 +#define IOFILT_WIDTH_32us 8 +#define IOFILT_WIDTH_64us 9 +#define IOFILT_WIDTH_128us 10 +#define IOFILT_WIDTH_256us 11 +#define IOFILT_WIDTH_512us 12 +#define IOFILT_WIDTH_1024us 13 +#define IOFILT_WIDTH_2048us 14 +#define IOFILT_WIDTH_4096us 15 + + + +void IOFILT_Init(uint32_t IOFILTn, uint32_t signal, uint32_t width); + + +#endif // __SWM221_IOFILT_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_mpu.c b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_mpu.c new file mode 100644 index 0000000..56ce5a6 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_mpu.c @@ -0,0 +1,90 @@ +/****************************************************************************************************************************************** +* ļ: SWM221_mpu.c +* ˵: SWM221ƬMPU +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.0.0 2016130 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM221.h" +#include "SWM221_mpu.h" + + +/****************************************************************************************************************************************** +* : MPU_Init() +* ˵: MPU LCDʼ +* : MPU_TypeDef * MPUx ָҪõMPUЧֵMPU +* MPU_InitStructure * initStruct MPU LCD趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void MPU_Init(MPU_TypeDef * MPUx, MPU_InitStructure * initStruct) +{ + switch((uint32_t)MPUx) + { + case ((uint32_t)MPU): + SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_MPU_Pos); + __NOP();__NOP();__NOP(); + break; + } + + MPUx->SR = initStruct->ByteOrder << MPU_SR_ENDIAN_Pos; + + MPUx->CR = ((initStruct->RDHoldTime - 1) << MPU_CR_RDHOLD_Pos) | + ((initStruct->WRHoldTime - 1) << MPU_CR_WRHOLD_Pos) | + ((initStruct->CSFall_WRFall - 1) << MPU_CR_CS0WR0_Pos) | + ((initStruct->WRRise_CSRise - 1) << MPU_CR_WR1CS1_Pos) | + ((initStruct->RDCSRise_Fall - 1) << MPU_CR_RCS1_0_Pos) | + ((initStruct->WRCSRise_Fall - 1) << MPU_CR_WCS1_0_Pos); +} + + +static uint32_t MPU_IsBusy(MPU_TypeDef * MPUx) +{ + return (MPUx->SR & MPU_SR_BUSY_Msk); +} + + +void MPU_WR_REG8(MPU_TypeDef * MPUx, uint8_t reg) +{ + MPUx->IRB = reg; + while(MPU_IsBusy(MPUx)) {} +} + +void MPU_WR_DATA8(MPU_TypeDef * MPUx, uint8_t val) +{ + MPUx->DRB = val; + while(MPU_IsBusy(MPUx)) {} +} + +void MPU_WR_DATA16(MPU_TypeDef * MPUx, uint16_t val) +{ + MPUx->DRH = val; + while(MPU_IsBusy(MPUx)) {} +} + +void MPU_WriteReg(MPU_TypeDef * MPUx, uint8_t reg, uint8_t val) +{ + MPU_WR_REG8(MPUx, reg); + + MPU_WR_DATA8(MPUx, val); +} + +uint8_t MPU_ReadReg(MPU_TypeDef * MPUx, uint8_t reg) +{ + MPU_WR_REG8(MPUx, reg); + + return MPUx->DRB; +} diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_mpu.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_mpu.h new file mode 100644 index 0000000..5e45b69 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_mpu.h @@ -0,0 +1,29 @@ +#ifndef __SWM221_MPU_H__ +#define __SWM221_MPU_H__ + +typedef struct { + uint8_t ByteOrder; //ִадʱȷ͵ 8 λȷ͸ 8 λȡֵ MPU_LITTLE_ENDIANMPU_BIG_ENDIAN + uint8_t RDHoldTime; //LCD_RD͵ƽʱ,ȡֵ1--32 + uint8_t WRHoldTime; //LCD_WR͵ƽʱ,ȡֵ1--16 + uint8_t CSFall_WRFall; //LCD_CS½صLCD_WR½ʱȡֵ1--4 + uint8_t WRRise_CSRise; //LCD_WRصLCD_CSʱȡֵ1--4 + uint8_t RDCSRise_Fall; //ʱLCD_CSص½ʱȡֵ1--32 + uint8_t WRCSRise_Fall; //дʱLCD_CSص½ʱȡֵ1--16 +} MPU_InitStructure; + + +#define MPU_LITTLE_ENDIAN 0 +#define MPU_BIG_ENDIAN 1 + + +void MPU_Init(MPU_TypeDef * MPUx, MPU_InitStructure * initStruct); + +void MPU_WR_REG8(MPU_TypeDef * MPUx, uint8_t reg); +void MPU_WR_DATA8(MPU_TypeDef * MPUx, uint8_t val); +void MPU_WR_DATA16(MPU_TypeDef * MPUx, uint16_t val); + +void MPU_WriteReg(MPU_TypeDef * MPUx, uint8_t reg, uint8_t val); +uint8_t MPU_ReadReg(MPU_TypeDef * MPUx, uint8_t reg); + + +#endif // __SWM221_MPU_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_port.c b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_port.c new file mode 100644 index 0000000..62b8fc0 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_port.c @@ -0,0 +1,49 @@ +/****************************************************************************************************************************************** +* ļ: SWM221_port.c +* ˵: SWM221ƬĶ˿Źѡ⺯ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.0.0 2016130 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM221.h" + + +/****************************************************************************************************************************************** +* : PORT_Init() +* ˵: ˿Źѡ񣬿õĹܼ"SWM221_port.h"ļ +* : PORT_TypeDef * PORTx ָPORT˿ڣЧֵPORTAPORTBPORTC +* uint32_t n ָPORTţЧֵPIN0PIN1PIN2... ... PIN14PIN15 +* uint32_t func ָ˿Ҫ趨Ĺܣȡֵ"SWM221_port.h"ļ +* uint32_t digit_in_en ʹ +* : +* ע: +******************************************************************************************************************************************/ +void PORT_Init(PORT_TypeDef * PORTx, uint32_t n, uint32_t func, uint32_t digit_in_en) +{ + if(n < PIN8) + { + PORTx->FUNC0 &= ~(0x0F << (n*4)); + PORTx->FUNC0 |= (func << (n*4)); + } + else + { + PORTx->FUNC1 &= ~(0x0F << ((n-8)*4)); + PORTx->FUNC1 |= (func << ((n-8)*4)); + } + + if(digit_in_en) PORTx->INEN |= (1 << n); + else PORTx->INEN &= ~(1 << n); +} diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_port.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_port.h new file mode 100644 index 0000000..6120cc7 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_port.h @@ -0,0 +1,268 @@ +#ifndef __SWM221_PORT_H__ +#define __SWM221_PORT_H__ + +void PORT_Init(PORT_TypeDef * PORTx, uint32_t n, uint32_t func, uint32_t digit_in_en); //˿Źѡȡֵ£ + + +#define PORTA_PIN0_GPIO 0 +#define PORTA_PIN0_MPU_D7 1 +#define PORTA_PIN0_I2C0_SCL 2 +#define PORTA_PIN0_UART0_RX 3 +#define PORTA_PIN0_PWM0AN 4 +#define PORTA_PIN0_PWM1BN 5 +#define PORTA_PIN0_PWM0A 6 + +#define PORTA_PIN1_GPIO 0 +#define PORTA_PIN1_I2C0_SDA 1 +#define PORTA_PIN1_UART0_TX 2 +#define PORTA_PIN1_PWM1BN 3 +#define PORTA_PIN1_PWM1B 4 + +#define PORTA_PIN2_GPIO 0 +#define PORTA_PIN2_USART0_TX 1 +#define PORTA_PIN2_PWM1AN 2 +#define PORTA_PIN2_PWM0AN 3 +#define PORTA_PIN2_PWM1A 4 + +#define PORTA_PIN3_GPIO 0 +#define PORTA_PIN3_USART0_RX 1 +#define PORTA_PIN3_PWM0A 2 +#define PORTA_PIN3_PWM1AN 3 +#define PORTA_PIN3_PWM0AN 4 + +#define PORTA_PIN4_GPIO 0 +#define PORTA_PIN4_UART1_TX 1 +#define PORTA_PIN4_PWM1B 2 +#define PORTA_PIN4_PWM1AN 3 +#define PORTA_PIN4_PWM1BN 4 + +#define PORTA_PIN5_GPIO 0 +#define PORTA_PIN5_UART1_RX 1 +#define PORTA_PIN5_PWM1A 2 +#define PORTA_PIN5_PWM0AN 3 +#define PORTA_PIN5_PWM1AN 4 + +#define PORTA_PIN6_GPIO 0 +#define PORTA_PIN6_I2C0_SCL 1 +#define PORTA_PIN6_USART0_TX 2 +#define PORTA_PIN6_CAN0_RX 3 +#define PORTA_PIN6_PWM0B 4 +#define PORTA_PIN6_BTIMR0_OUT 5 + +#define PORTA_PIN7_GPIO 0 +#define PORTA_PIN7_I2C0_SDA 1 +#define PORTA_PIN7_USART0_RX 2 +#define PORTA_PIN7_CAN0_TX 3 +#define PORTA_PIN7_PWM0BN 4 +#define PORTA_PIN7_BTIMR1_OUT 5 + +#define PORTA_PIN8_GPIO 0 +#define PORTA_PIN8_MPU_D0 1 +#define PORTA_PIN8_SPI0_SCLK 2 +#define PORTA_PIN8_QSPI0_SCLK 3 +#define PORTA_PIN8_ADC0_CH2 7 +#define PORTA_PIN8_OPA1_OUT 7 + +#define PORTA_PIN9_GPIO 0 +#define PORTA_PIN9_MPU_D1 1 +#define PORTA_PIN9_USART0_TX 2 +#define PORTA_PIN9_SPI0_MOSI 3 +#define PORTA_PIN9_QSPI0_MOSI 4 +#define PORTA_PIN9_OPA1_INP 7 + +#define PORTA_PIN10_GPIO 0 +#define PORTA_PIN10_MPU_D2 1 +#define PORTA_PIN10_USART0_RX 2 +#define PORTA_PIN10_SPI0_MISO 3 +#define PORTA_PIN10_QSPI0_MISO 4 +#define PORTA_PIN10_OPA1_INN 7 + +#define PORTA_PIN11_GPIO 0 +#define PORTA_PIN11_MPU_D3 1 +#define PORTA_PIN11_SPI0_SSEL 2 +#define PORTA_PIN11_QSPI0_SSEL 3 +#define PORTA_PIN11_PWM_CLK1 4 +#define PORTA_PIN11_ADC0_CH1 7 +#define PORTA_PIN11_ADC_REFP 7 + +#define PORTA_PIN12_GPIO 0 +#define PORTA_PIN12_MPU_D4 1 +#define PORTA_PIN12_UART1_TX 2 +#define PORTA_PIN12_QSPI0_D2 3 +#define PORTA_PIN12_ADC1_CH1 7 +#define PORTA_PIN12_ACMP1_INN 7 + +#define PORTA_PIN13_GPIO 0 +#define PORTA_PIN13_MPU_D5 1 +#define PORTA_PIN13_UART1_RX 2 +#define PORTA_PIN13_QSPI0_D3 3 +#define PORTA_PIN13_ADC1_CH0 7 + +#define PORTA_PIN14_GPIO 0 +#define PORTA_PIN14_MPU_D6 1 +#define PORTA_PIN14_TIMR0_IN 2 +#define PORTA_PIN14_TIMR0_OUT 3 +#define PORTA_PIN14_ADC0_CH0 7 +#define PORTA_PIN14_ACMP1_INP 7 + +#define PORTA_PIN15_GPIO 0 +#define PORTA_PIN15_QSPI0_MOSI 1 +#define PORTA_PIN15_PWM1A 2 +#define PORTA_PIN15_HALL_IN2 3 + +#define PORTB_PIN0_GPIO 0 +#define PORTB_PIN0_UART1_TX 1 +#define PORTB_PIN0_QSPI0_MISO 2 +#define PORTB_PIN0_BTIMR2_OUT 3 +#define PORTB_PIN0_TIMR0_IN 4 +#define PORTB_PIN0_TIMR0_OUT 5 +#define PORTB_PIN0_ADC1_CH6 7 +#define PORTB_PIN0_OPA2_INN 7 + +#define PORTB_PIN1_GPIO 0 +#define PORTB_PIN1_UART1_RX 1 +#define PORTB_PIN1_QSPI0_D2 2 +#define PORTB_PIN1_BTIMR3_OUT 3 +#define PORTB_PIN1_TIMR2_IN 4 +#define PORTB_PIN1_TIMR2_OUT 5 +#define PORTB_PIN1_OPA2_INP 7 + +#define PORTB_PIN2_GPIO 0 +#define PORTB_PIN2_UART0_TX 1 +#define PORTB_PIN2_QSPI0_D3 2 +#define PORTB_PIN2_BTIMR0_OUT 3 +#define PORTB_PIN2_TIMR1_IN 4 +#define PORTB_PIN2_TIMR1_OUT 5 +#define PORTB_PIN2_ADC0_CH8 7 +#define PORTB_PIN2_OPA2_OUT 7 + +#define PORTB_PIN3_GPIO 0 +#define PORTB_PIN3_UART0_RX 1 +#define PORTB_PIN3_BTIMR1_OUT 2 +#define PORTB_PIN3_TIMR2_IN 3 +#define PORTB_PIN3_TIMR2_OUT 4 +#define PORTB_PIN3_ACMP0_INN 7 + +#define PORTB_PIN4_GPIO 0 +#define PORTB_PIN4_MPU_CS 1 +#define PORTB_PIN4_QEI_A 2 +#define PORTB_PIN4_I2C0_SCL 3 +#define PORTB_PIN4_QSPI0_MOSI 4 +#define PORTB_PIN4_HALL_IN0 5 +#define PORTB_PIN4_ADC0_CH7 7 +#define PORTB_PIN4_ACMP0_INP2 7 + +#define PORTB_PIN5_GPIO 0 +#define PORTB_PIN5_MPU_RS 1 +#define PORTB_PIN5_QEI_B 2 +#define PORTB_PIN5_I2C0_SDA 3 +#define PORTB_PIN5_HALL_IN1 4 +#define PORTB_PIN5_TIMR1_IN 5 +#define PORTB_PIN5_TIMR1_OUT 6 +#define PORTB_PIN5_ADC0_CH6 7 +#define PORTB_PIN5_ACMP0_INP1 7 + +#define PORTB_PIN6_GPIO 0 +#define PORTB_PIN6_MPU_WR 1 +#define PORTB_PIN6_QEI_Z 2 +#define PORTB_PIN6_PWM_BRK1 3 +#define PORTB_PIN6_HALL_IN2 4 +#define PORTB_PIN6_TIMR0_IN 5 +#define PORTB_PIN6_TIMR0_OUT 6 +#define PORTB_PIN6_ADC0_CH5 7 +#define PORTB_PIN6_ACMP0_INP0 7 + +#define PORTB_PIN7_GPIO 0 +#define PORTB_PIN7_QEI_DIR 1 +#define PORTB_PIN7_UART1_TX 2 +#define PORTB_PIN7_CAN0_RX 3 +#define PORTB_PIN7_TIMR2_IN 4 +#define PORTB_PIN7_TIMR2_OUT 5 +#define PORTB_PIN7_ADC1_CH3 7 +#define PORTB_PIN7_OPA0_INP 7 + +#define PORTB_PIN8_GPIO 0 +#define PORTB_PIN8_UART1_RX 1 +#define PORTB_PIN8_CAN0_TX 2 +#define PORTB_PIN8_OPA0_INN 7 + +#define PORTB_PIN9_GPIO 0 +#define PORTB_PIN9_MPU_RD 1 +#define PORTB_PIN9_ADC1_CH2 7 +#define PORTB_PIN9_OPA0_OUT 7 + +#define PORTB_PIN10_GPIO 0 +#define PORTB_PIN10_UART1_TX 1 +#define PORTB_PIN10_UART1_RX 2 +#define PORTB_PIN10_SPI0_SCLK 3 +#define PORTB_PIN10_PWM0AN 4 +#define PORTB_PIN10_TIMR0_IN 5 +#define PORTB_PIN10_TIMR0_OUT 6 + +#define PORTB_PIN11_GPIO 0 +#define PORTB_PIN11_UART0_TX 1 +#define PORTB_PIN11_SPI0_SCLK 2 +#define PORTB_PIN11_PWM0BN 3 +#define PORTB_PIN11_TIMR1_IN 4 +#define PORTB_PIN11_TIMR1_OUT 5 +#define PORTB_PIN11_XTAL_IN 7 + +#define PORTB_PIN12_GPIO 0 +#define PORTB_PIN12_UART0_RX 1 +#define PORTB_PIN12_SPI0_MOSI 2 +#define PORTB_PIN12_PWM0B 3 +#define PORTB_PIN12_TIMR2_IN 4 +#define PORTB_PIN12_TIMR2_OUT 5 +#define PORTB_PIN12_XTAL_OUT 7 + +#define PORTB_PIN13_GPIO 0 +#define PORTB_PIN13_SPI0_MOSI 1 +#define PORTB_PIN13_PWM0A 2 + +#define PORTB_PIN14_GPIO 0 +#define PORTB_PIN14_USART0_TX 1 +#define PORTB_PIN14_UART0_TX 2 +#define PORTB_PIN14_SPI0_MISO 3 +#define PORTB_PIN14_PWM_BRK0 4 +#define PORTB_PIN14_BTIMR2_OUT 5 +#define PORTB_PIN14_ADC1_CH9 7 + +#define PORTB_PIN15_GPIO 0 +#define PORTB_PIN15_USART0_RX 1 +#define PORTB_PIN15_UART0_RX 2 +#define PORTB_PIN15_SPI0_SSEL 3 +#define PORTB_PIN15_BTIMR3_OUT 4 +#define PORTB_PIN15_TIMR0_IN 5 +#define PORTB_PIN15_TIMR0_OUT 5 +#define PORTB_PIN15_ADC1_CH8 7 + +#define PORTC_PIN0_GPIO 0 +#define PORTC_PIN0_SWCLK 1 +#define PORTC_PIN0_UART1_TX 2 +#define PORTC_PIN0_PWM_CLK0 3 +#define PORTC_PIN0_TIMR1_IN 4 +#define PORTC_PIN0_TIMR1_OUT 5 +#define PORTC_PIN0_ADC1_CH7 7 + +#define PORTC_PIN1_GPIO 0 +#define PORTC_PIN1_SWDIO 1 +#define PORTC_PIN1_UART1_RX 2 +#define PORTC_PIN1_BTIMR3_OUT 3 + +#define PORTC_PIN2_GPIO 0 +#define PORTC_PIN2_I2C0_SCL 1 +#define PORTC_PIN2_UART0_TX 2 +#define PORTC_PIN2_QSPI0_SSEL 3 +#define PORTC_PIN2_CAN0_RX 4 +#define PORTC_PIN2_PWM0A 5 +#define PORTC_PIN2_HALL_IN0 6 + +#define PORTC_PIN3_GPIO 0 +#define PORTC_PIN3_I2C0_SDA 1 +#define PORTC_PIN3_UART0_RX 2 +#define PORTC_PIN3_QSPI0_SCLK 3 +#define PORTC_PIN3_CAN0_TX 4 +#define PORTC_PIN3_PWM0B 5 +#define PORTC_PIN3_HALL_IN1 7 + +#endif //__SWM221_PORT_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_pwm.c b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_pwm.c new file mode 100644 index 0000000..ba00a1e --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_pwm.c @@ -0,0 +1,528 @@ +/****************************************************************************************************************************************** +* ļ: SWM221_pwm.c +* ˵: SWM221ƬPWM +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.0.0 2016130 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM221.h" +#include "SWM221_pwm.h" + + +/****************************************************************************************************************************************** +* : PWM_Init() +* ˵: PWMʼ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1 +* PWM_InitStructure * initStruct PWM趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void PWM_Init(PWM_TypeDef * PWMx, PWM_InitStructure * initStruct) +{ + SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_PWM_Pos); + + PWMx->CR = (initStruct->Mode << PWM_CR_MODE_Pos) | + (1 << PWM_CR_MULT_Pos) | // μģʽǵΣ + (0 << PWM_CR_DIR_Pos) | // ϼ + (0 << PWM_CR_CLKSRC_Pos) | // ϵͳʱ + ((initStruct->Clkdiv - 1) << PWM_CR_CLKDIV_Pos) | + (0 << PWM_CR_RPTNUM_Pos); // ÿμִмĴؼ + + PWMx->OCR = ((initStruct->IdleLevelA ? 1 : 0) << PWM_OCR_IDLEA_Pos) | + ((initStruct->IdleLevelB ? 1 : 0) << PWM_OCR_IDLEB_Pos) | + ((initStruct->IdleLevelAN ? 1 : 0) << PWM_OCR_IDLEAN_Pos) | + ((initStruct->IdleLevelBN ? 1 : 0) << PWM_OCR_IDLEBN_Pos) | + ((initStruct->OutputInvA ? 1 : 0) << PWM_OCR_INVA_Pos) | + ((initStruct->OutputInvB ? 1 : 0) << PWM_OCR_INVB_Pos) | + ((initStruct->OutputInvAN ? 1 : 0) << PWM_OCR_INVAN_Pos) | + ((initStruct->OutputInvBN ? 1 : 0) << PWM_OCR_INVBN_Pos); + + PWMx->PERIOD = initStruct->Period - 1; + + PWMx->CMPA = initStruct->HdutyA; + PWMx->CMPA2 = initStruct->HdutyA2; + PWMx->DZA = initStruct->DeadzoneA; + + PWMx->CMPB = initStruct->HdutyB; + PWMx->CMPB2 = initStruct->HdutyB2; + PWMx->DZB = initStruct->DeadzoneB; + + PWMG->RELOADEN = 0x3F; + + PWMx->IF = 0x3F; + PWMx->IE = ((initStruct->UpOvfIE ? 1 : 0) << PWM_IE_UPOVF_Pos) | + ((initStruct->DownOvfIE ? 1 : 0) << PWM_IE_DNOVF_Pos) | + ((initStruct->UpCmpAIE ? 1 : 0) << PWM_IE_UPCMPA_Pos) | + ((initStruct->DownCmpAIE ? 1 : 0) << PWM_IE_DNCMPA_Pos) | + ((initStruct->UpCmpBIE ? 1 : 0) << PWM_IE_UPCMPB_Pos) | + ((initStruct->DownCmpBIE ? 1 : 0) << PWM_IE_DNCMPB_Pos); + + if(initStruct->UpOvfIE || initStruct->DownOvfIE || initStruct->UpCmpAIE || + initStruct->DownCmpAIE || initStruct->UpCmpBIE || initStruct->DownCmpBIE) + { + switch((uint32_t)PWMx) + { + case((uint32_t)PWM0): + NVIC_EnableIRQ(PWM0_IRQn); + break; + + case((uint32_t)PWM1): + NVIC_EnableIRQ(PWM1_IRQn); + break; + } + } +} + +/****************************************************************************************************************************************** +* : PWM_Start() +* ˵: PWMʼPWM +* : uint32_t pwm PWM0_MSKPWM1_MSKPWM2_MSKPWM3_MSKPWM4_MSKPWM5_MSK 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void PWM_Start(uint32_t pwm) +{ + PWMG->START |= pwm; +} + +/****************************************************************************************************************************************** +* : PWM_Stop() +* ˵: رPWMֹͣPWM +* : uint32_t pwm PWM0_MSKPWM1_MSKPWM2_MSKPWM3_MSKPWM4_MSKPWM5_MSK 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void PWM_Stop(uint32_t pwm) +{ + PWMG->START &= ~pwm; +} + +/****************************************************************************************************************************************** +* : PWM_Restart() +* ˵: PWMPWM㣬Ȼʹµڡߵƽʱʱ趨ֵʼ +* : uint32_t pwm PWM0_MSKPWM1_MSKPWM2_MSKPWM3_MSKPWM4_MSKPWM5_MSK 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void PWM_Restart(uint32_t pwm) +{ + PWMG->RESTART = (pwm << PWMG_RESTART_PWM0_Pos); +} + +/****************************************************************************************************************************************** +* : PWM_ReloadEn() +* ˵: ֻе Reload Enable ʱд PERIODCMPACMPBDZADZB ȼĴֵŻᣨڼʱصڲĴ +* : uint32_t pwm PWM0_MSKPWM1_MSKPWM2_MSKPWM3_MSKPWM4_MSKPWM5_MSK 䡰 +* : +* ע: Ҫ֤д PERIODCMPACMPBDZADZB ȼĴУЩĴֵᱻصڲĴ² +* һPWM_ReloadDis(PWM0_MSK | PWM1_MSK); +* ڶд PERIODCMPACMPBDZADZB ȼĴ +* PWM_ReloadEn(PWM0_MSK | PWM1_MSK); +******************************************************************************************************************************************/ +void PWM_ReloadEn(uint32_t pwm) +{ + PWMG->RELOADEN |= pwm; +} + +/****************************************************************************************************************************************** +* : PWM_ReloadDis() +* ˵: ֻе Reload Enable ʱд PERIODCMPACMPBDZADZB ȼĴֵŻᣨڼʱصڲĴ +* : uint32_t pwm PWM0_MSKPWM1_MSKPWM2_MSKPWM3_MSKPWM4_MSKPWM5_MSK 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void PWM_ReloadDis(uint32_t pwm) +{ + PWMG->RELOADEN &= ~pwm; +} + +/****************************************************************************************************************************************** +* : PWM_BrkInPolarity() +* ˵: ɲЧ +* : uint32_t brk PWM_BRK0PWM_BRK1PWM_BRK2 䡰 +* uint32_t level 0 ͵ƽɲ 1 ߵƽɲ +* : +* ע: +******************************************************************************************************************************************/ +void PWM_BrkInPolarity(uint32_t brk, uint32_t level) +{ + if(level) + PWMG->BRKPOL |= brk; + else + PWMG->BRKPOL &= ~brk; +} + +/****************************************************************************************************************************************** +* : PWM_BrkConfig() +* ˵: ɲ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1 +* uint32_t chn ָҪõPWMͨЧֵPWM_CH_APWM_CH_B +* uint32_t brk ɲ룬PWM_BRK0PWM_BRK1PWM_BRK2 䡰 +* uint32_t out ɲPWMxA/PWMxBƽ +* uint32_t outN ɲPWMxAN/PWMxBNƽ +* uint32_t outHold ɲźų0 ָ 1 ֵٻָ +* uint32_t stpCount ɲ״̬Ƿֹͣ1 ֹͣ +* : +* ע: +******************************************************************************************************************************************/ +void PWM_BrkConfig(PWM_TypeDef * PWMx, uint32_t chn, uint32_t brk, uint32_t out, uint32_t outN, uint32_t outHold, uint32_t stpCount) +{ + if(chn == PWM_CH_A) + { + PWMx->BRKIN &= ~(0x7 << PWM_BRKIN_BRK0A_Pos); + PWMx->BRKIN |= (brk << PWM_BRKIN_BRK0A_Pos); + + PWMx->BRKCR &= ~(PWM_BRKCR_OUTA_Msk | PWM_BRKCR_OUTAN_Msk | PWM_BRKCR_OFFA_Msk); + PWMx->BRKCR |= (out << PWM_BRKCR_OUTA_Pos) | + (outN << PWM_BRKCR_OUTAN_Pos) | + (outHold << PWM_BRKCR_OFFA_Pos) | + (stpCount << PWM_BRKCR_STPCNT_Pos); + } + else + { + PWMx->BRKIN &= ~(0x7 << PWM_BRKIN_BRK0B_Pos); + PWMx->BRKIN |= (brk << PWM_BRKIN_BRK0B_Pos); + + PWMx->BRKCR &= ~(PWM_BRKCR_OUTB_Msk | PWM_BRKCR_OUTBN_Msk | PWM_BRKCR_OFFB_Msk); + PWMx->BRKCR |= (out << PWM_BRKCR_OUTB_Pos) | + (outN << PWM_BRKCR_OUTBN_Pos) | + (outHold << PWM_BRKCR_OFFB_Pos) | + (stpCount << PWM_BRKCR_STPCNT_Pos); + } +} + +/****************************************************************************************************************************************** +* : PWM_OvfTrigger() +* ˵: ʱź +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1 +* uint32_t en_up ϼʱǷ񷢳ź +* uint32_t en_down ¼ʱǷ񷢳ź +* uint32_t trig_chn ź8ͨѡ˴źĸͨȡֵPWM_TRG_0PWM_TRG_1...PWM_TRG_7 +* : +* ע: +******************************************************************************************************************************************/ +void PWM_OvfTrigger(PWM_TypeDef * PWMx, uint32_t en_up, uint32_t en_down, uint32_t trig_chn) +{ + PWMx->OVFTRG = (en_up << PWM_OVFTRG_UPEN_Pos) | + (en_down << PWM_OVFTRG_DNEN_Pos) | + (trig_chn << PWM_OVFTRG_MUX_Pos); +} + +/****************************************************************************************************************************************** +* : PWM_CmpTrigger() +* ˵: ֵָʱź +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1 +* uint16_t match ֵmatchʱź +* uint32_t dir PWM_DIR_UP ϼʱmatchֵȽ PWM_DIR_DOWN ¼ʱmatchֵȽ +* uint32_t width ĴźŵĿȣȡֵ04812...252 PWMʱ +* uint32_t trig_chn ź8ͨѡ˴źĸͨȡֵPWM_TRG_0PWM_TRG_1...PWM_TRG_7 +* uint32_t trig_interval 0 ÿڴ 1 1ڴһ 2 2ڴһ ... 7 7ڴһ +* : +* ע: +******************************************************************************************************************************************/ +void PWM_CmpTrigger(PWM_TypeDef * PWMx, uint16_t match, uint32_t dir, uint32_t width, uint32_t trig_chn, uint32_t trig_interval) +{ + PWMx->CMPTRG = (1 << PWM_CMPTRG_EN_Pos) | + (match << PWM_CMPTRG_CMP_Pos) | + (dir << PWM_CMPTRG_DIR_Pos) | + ((width/4) << PWM_CMPTRG_WIDTH_Pos) | + (trig_chn << PWM_CMPTRG_MUX_Pos) | + /* ڷָȴźŵͬʱڸôźſȵ PWM->CMPTRG.ATP/8 λôadcźţȡֵ0--7 */ + (3 << PWM_CMPTRG_ATP_Pos); + + PWMx->CMPTRG2 = (trig_interval << PWM_CMPTRG2_INTV_Pos); +} + +/****************************************************************************************************************************************** +* : PWM_OutMask() +* ˵: ΣָźΪʱPWM̶ƽ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1 +* uint32_t chn ָҪõPWMͨЧֵPWM_CH_APWM_CH_B +* uint32_t evt PWMxY · event źΣȡֵPWM_EVT_DISPWM_EVT_0PWM_EVT_1...PWM_EVT_6 +* uint32_t out PWMxY ʱʲôƽ +* uint32_t evt_n PWMxYN· event źΣȡֵPWM_EVT_DISPWM_EVT_0PWM_EVT_1...PWM_EVT_6 +* uint32_t out_n PWMxYNʱʲôƽ +* : +* ע: +******************************************************************************************************************************************/ +void PWM_OutMask(PWM_TypeDef * PWMx, uint32_t chn, uint32_t evt, uint32_t out, uint32_t evt_n, uint32_t out_n) +{ + if(chn == PWM_CH_A) + { + PWMx->EVMUX &= ~(PWM_EVMUX_MASKA_Msk | PWM_EVMUX_MASKAN_Msk); + PWMx->EVMUX |= (evt << PWM_EVMUX_MASKA_Pos) | + (evt_n << PWM_EVMUX_MASKAN_Pos); + + PWMx->EVMSK &= ~(PWM_EVMSK_OUTA_Msk | PWM_EVMSK_OUTAN_Msk); + PWMx->EVMSK |= (out << PWM_EVMSK_OUTA_Pos) | + (out_n << PWM_EVMSK_OUTAN_Pos) | + (1 << PWM_EVMSK_IMME_Pos); + } + else + { + PWMx->EVMUX &= ~(PWM_EVMUX_MASKB_Msk | PWM_EVMUX_MASKBN_Msk); + PWMx->EVMUX |= (evt << PWM_EVMUX_MASKB_Pos) | + (evt_n << PWM_EVMUX_MASKBN_Pos); + + PWMx->EVMSK &= ~(PWM_EVMSK_OUTB_Msk | PWM_EVMSK_OUTBN_Msk); + PWMx->EVMSK |= (out << PWM_EVMSK_OUTB_Pos) | + (out_n << PWM_EVMSK_OUTBN_Pos) | + (1 << PWM_EVMSK_IMME_Pos); + } +} + +/****************************************************************************************************************************************** +* : PWM_SetPeriod() +* ˵: +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1 +* uint16_t period Ҫ趨ֵ +* : +* ע: +******************************************************************************************************************************************/ +void PWM_SetPeriod(PWM_TypeDef * PWMx, uint16_t period) +{ + PWMx->PERIOD = period - 1; +} + +/****************************************************************************************************************************************** +* : PWM_GetPeriod() +* ˵: ȡ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1 +* : uint16_t ȡֵ +* ע: +******************************************************************************************************************************************/ +uint16_t PWM_GetPeriod(PWM_TypeDef * PWMx) +{ + return PWMx->PERIOD + 1; +} + +/****************************************************************************************************************************************** +* : PWM_SetHDuty() +* ˵: øߵƽʱ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1 +* uint32_t chn ָҪõPWMͨЧֵPWM_CH_APWM_CH_B +* uint16_t hduty Ҫ趨ĸߵƽʱ +* : +* ע: +******************************************************************************************************************************************/ +void PWM_SetHDuty(PWM_TypeDef * PWMx, uint32_t chn, uint16_t hduty) +{ + if(chn == PWM_CH_A) + PWMx->CMPA = hduty; + else + PWMx->CMPB = hduty; +} + +/****************************************************************************************************************************************** +* : PWM_GetHDuty() +* ˵: ȡߵƽʱ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1 +* uint32_t chn ָҪõPWMͨЧֵPWM_CH_APWM_CH_B +* : uint16_t ȡĸߵƽʱ +* ע: +******************************************************************************************************************************************/ +uint16_t PWM_GetHDuty(PWM_TypeDef * PWMx, uint32_t chn) +{ + if(chn == PWM_CH_A) + return PWMx->CMPA; + else + return PWMx->CMPB; +} + +/****************************************************************************************************************************************** +* : PWM_SetHDuty2() +* ˵: øߵƽʱڷǶԳĶģʽ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1 +* uint32_t chn ָҪõPWMͨЧֵPWM_CH_APWM_CH_B +* uint16_t hduty Ҫ趨ǰڸߵƽʱ +* uint16_t hduty2 Ҫ趨ĺڸߵƽʱ +* : +* ע: +******************************************************************************************************************************************/ +void PWM_SetHDuty2(PWM_TypeDef * PWMx, uint32_t chn, uint16_t hduty, uint16_t hduty2) +{ + if(chn == PWM_CH_A) + { + PWMx->CMPA = hduty; + PWMx->CMPA2 = hduty2; + } + else + { + PWMx->CMPB = hduty; + PWMx->CMPB2 = hduty2; + } +} + +/****************************************************************************************************************************************** +* : PWM_GetHDuty2() +* ˵: ȡߵƽʱڷǶԳĶģʽ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1 +* uint32_t chn ָҪõPWMͨЧֵPWM_CH_APWM_CH_B +* : uint16_t *hduty ȡǰڸߵƽʱ +* uint16_t *hduty2 ȡĺڸߵƽʱ +* ע: +******************************************************************************************************************************************/ +void PWM_GetHDuty2(PWM_TypeDef * PWMx, uint32_t chn, uint16_t *hduty, uint16_t *hduty2) +{ + if(chn == PWM_CH_A) + { + *hduty = PWMx->CMPA; + *hduty2 = PWMx->CMPA2; + } + else + { + *hduty = PWMx->CMPB; + *hduty2 = PWMx->CMPB2; + } +} + +/****************************************************************************************************************************************** +* : PWM_SetDeadzone() +* ˵: ʱ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1 +* uint32_t chn ָҪõPWMͨЧֵPWM_CH_APWM_CH_B +* uint16_t deadzone Ҫ趨ʱȡֵΧ0--1023 +* : +* ע: +******************************************************************************************************************************************/ +void PWM_SetDeadzone(PWM_TypeDef * PWMx, uint32_t chn, uint16_t deadzone) +{ + if(chn == PWM_CH_A) + PWMx->DZA = deadzone; + else + PWMx->DZB = deadzone; +} + +/****************************************************************************************************************************************** +* : PWM_GetDeadzone() +* ˵: ȡʱ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1 +* uint32_t chn ָҪõPWMͨЧֵPWM_CH_APWM_CH_B +* : uint16_t ȡʱ +* ע: +******************************************************************************************************************************************/ +uint16_t PWM_GetDeadzone(PWM_TypeDef * PWMx, uint32_t chn) +{ + if(chn == PWM_CH_A) + return PWMx->DZA; + else + return PWMx->DZB; +} + + +/****************************************************************************************************************************************** +* : PWM_IntEn() +* ˵: жʹ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1 +* uint32_t it interrupt typeЧֵPWM_IT_OVF_UPPWM_IT_OVF_DOWNPWM_IT_CMPA_UPPWM_IT_CMPB_UP +* PWM_IT_CMPA_DOWNPWM_IT_CMPB_DOWN 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void PWM_IntEn(PWM_TypeDef * PWMx, uint32_t it) +{ + PWMx->IE |= it; +} + +/****************************************************************************************************************************************** +* : PWM_IntDis() +* ˵: жϽ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1 +* uint32_t it interrupt typeЧֵPWM_IT_OVF_UPPWM_IT_OVF_DOWNPWM_IT_CMPA_UPPWM_IT_CMPB_UP +* PWM_IT_CMPA_DOWNPWM_IT_CMPB_DOWN 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void PWM_IntDis(PWM_TypeDef * PWMx, uint32_t it) +{ + PWMx->IE &= ~it; +} + +/****************************************************************************************************************************************** +* : PWM_IntClr() +* ˵:жϱ־ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1 +* uint32_t it interrupt typeЧֵPWM_IT_OVF_UPPWM_IT_OVF_DOWNPWM_IT_CMPA_UPPWM_IT_CMPB_UP +* PWM_IT_CMPA_DOWNPWM_IT_CMPB_DOWN 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void PWM_IntClr(PWM_TypeDef * PWMx, uint32_t it) +{ + PWMx->IF = it; +} + +/****************************************************************************************************************************************** +* : PWM_IntStat() +* ˵: жϱ־ѯ +* : PWM_TypeDef * PWMx ָҪõPWMЧֵPWM0PWM1 +* uint32_t it interrupt typeЧֵPWM_IT_OVF_UPPWM_IT_OVF_DOWNPWM_IT_CMPA_UPPWM_IT_CMPB_UP +* PWM_IT_CMPA_DOWNPWM_IT_CMPB_DOWN 䡰 +* : uint32_t 0 жϱ־δ 0 жϱ־ +* ע: +******************************************************************************************************************************************/ +uint32_t PWM_IntStat(PWM_TypeDef * PWMx, uint32_t it) +{ + return (PWMx->IF & it); +} + +/****************************************************************************************************************************************** +* : PWM_BrkIntEn() +* ˵: ɲжʹ +* : uint32_t brkit brake interrupt typeЧֵ PWM_BRKIT_BRK0PWM_BRKIT_BRK1PWM_BRKIT_BRK2 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void PWM_BrkIntEn(uint32_t brkit) +{ + PWMG->BRKIE |= brkit; +} + +/****************************************************************************************************************************************** +* : PWM_BrkIntDis() +* ˵: ɲжϽ +* : uint32_t brkit brake interrupt typeЧֵ PWM_BRKIT_BRK0PWM_BRKIT_BRK1PWM_BRKIT_BRK2 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void PWM_BrkIntDis(uint32_t brkit) +{ + PWMG->BRKIE &= ~brkit; +} + +/****************************************************************************************************************************************** +* : PWM_BrkIntClr() +* ˵:жϱ־ +* : uint32_t brkit brake interrupt typeЧֵ PWM_BRKIT_BRK0PWM_BRKIT_BRK1PWM_BRKIT_BRK2 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void PWM_BrkIntClr(uint32_t brkit) +{ + PWMG->BRKIF = brkit; +} + +/****************************************************************************************************************************************** +* : PWM_BrkIntStat() +* ˵: ɲжϱ־ѯ +* : uint32_t brkit brake interrupt typeЧֵ PWM_BRKIT_BRK0PWM_BRKIT_BRK1PWM_BRKIT_BRK2 䡰 +* : uint32_t 0 жϱ־δ 0 жϱ־ +* ע: +******************************************************************************************************************************************/ +uint32_t PWM_BrkIntStat(uint32_t brkit) +{ + return (PWMG->BRKIF & brkit); +} diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_pwm.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_pwm.h new file mode 100644 index 0000000..d68cb3b --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_pwm.h @@ -0,0 +1,122 @@ +#ifndef __SWM221_PWM_H__ +#define __SWM221_PWM_H__ + + +typedef struct { + uint8_t Mode; //PWM_EDGE_ALIGNEDPWM_CENTER_ALIGNEDPWM_ASYM_CENTER_ALIGNED + + uint16_t Clkdiv; //1--1024 + + uint16_t Period; // + + uint16_t HdutyA; //ռձȣߵƽʱPWM_ASYM_CENTER_ALIGNED ģʽ趨ǰڵĸߵƽʱ + uint16_t HdutyA2; //ֻ PWM_ASYM_CENTER_ALIGNED ģʽʹã趨ڵĸߵƽʱ + uint16_t DeadzoneA; //ʱȡֵ0--1023 + uint8_t IdleLevelA; //ֹͣ״̬PWMxAƽ + uint8_t IdleLevelAN; //ֹͣ״̬PWMxANƽ + uint8_t OutputInvA; //PWMxAȡ + uint8_t OutputInvAN; //PWMxANȡ + + uint16_t HdutyB; + uint16_t HdutyB2; + uint16_t DeadzoneB; + uint8_t IdleLevelB; + uint8_t IdleLevelBN; + uint8_t OutputInvB; + uint8_t OutputInvBN; + + uint8_t UpOvfIE; //ؼжʹܣPWM_EDGE_ALIGNED ģʽϼֻ + uint8_t DownOvfIE; //½ؼжʹܣģʽϼ¼ǰڡ½Ǻ + uint8_t UpCmpAIE; //رȽAƥжʹ + uint8_t DownCmpAIE; //½رȽAƥжʹ + uint8_t UpCmpBIE; //رȽBƥжʹ + uint8_t DownCmpBIE; //½رȽBƥжʹ +} PWM_InitStructure; + + +#define PWM_EDGE_ALIGNED 0 +#define PWM_CENTER_ALIGNED 1 +#define PWM_ASYM_CENTER_ALIGNED 2 // ǶԳĶģʽغ½ؾвͬķתȽֵ + + +#define PWM_CH_A 0 +#define PWM_CH_B 1 + +#define PWM0_MSK (1 << 0) +#define PWM1_MSK (1 << 1) + +#define PWM_BRK0 (1 << 0) +#define PWM_BRK1 (1 << 1) +#define PWM_BRK2 (1 << 2) + +#define PWM_DIR_UP 0 +#define PWM_DIR_DOWN 1 + +#define PWM_TRG_0 0 //ֵָʱ PWM ź +#define PWM_TRG_1 1 +#define PWM_TRG_2 2 +#define PWM_TRG_3 3 +#define PWM_TRG_4 4 +#define PWM_TRG_5 5 +#define PWM_TRG_6 6 +#define PWM_TRG_7 7 + +#define PWM_EVT_DIS 0 //ⲿ¼źΪʱ PWM ֹͣͣ +#define PWM_EVT_0 1 +#define PWM_EVT_1 2 +#define PWM_EVT_2 3 +#define PWM_EVT_3 4 +#define PWM_EVT_4 5 +#define PWM_EVT_TIMR0 6 +#define PWM_EVT_TIMR1 7 + +/* Interrupt Type */ +#define PWM_IT_OVF_UP (1 << 0) //ϼʱPWM_EDGE_ALIGNED ģʽϼֻ +#define PWM_IT_OVF_DOWN (1 << 1) //¼ʱģʽϼ¼ǰڡ½Ǻ +#define PWM_IT_CMPA_UP (1 << 2) //ϼʱֵCMPA +#define PWM_IT_CMPB_UP (1 << 3) //ϼʱֵCMPB +#define PWM_IT_CMPA_DOWN (1 << 4) //¼ʱֵCMPA +#define PWM_IT_CMPB_DOWN (1 << 5) //¼ʱֵCMPB + +#define PWM_BRKIT_BRK0 (1 << 0) //PWM_BRK0ϳɲź +#define PWM_BRKIT_BRK1 (1 << 1) +#define PWM_BRKIT_BRK2 (1 << 2) + + + +void PWM_Init(PWM_TypeDef * PWMx, PWM_InitStructure * initStruct); //PWMʼ +void PWM_Start(uint32_t pwm); //PWMʼPWM +void PWM_Stop(uint32_t pwm); //رPWMֹͣPWM +void PWM_Restart(uint32_t pwm); + +void PWM_ReloadEn(uint32_t pwm); +void PWM_ReloadDis(uint32_t pwm); + +void PWM_BrkInPolarity(uint32_t brk, uint32_t level); +void PWM_BrkConfig(PWM_TypeDef * PWMx, uint32_t chn, uint32_t brk, uint32_t out, uint32_t outN, uint32_t outHold, uint32_t stpCount); + +void PWM_OvfTrigger(PWM_TypeDef * PWMx, uint32_t en_up, uint32_t en_down, uint32_t trig_chn); +void PWM_CmpTrigger(PWM_TypeDef * PWMx, uint16_t match, uint32_t dir, uint32_t width, uint32_t trig_chn, uint32_t trig_interval); + +void PWM_OutMask(PWM_TypeDef * PWMx, uint32_t chn, uint32_t evt, uint32_t out, uint32_t evt_n, uint32_t out_n); + +void PWM_SetPeriod(PWM_TypeDef * PWMx, uint16_t period); // +uint16_t PWM_GetPeriod(PWM_TypeDef * PWMx); //ȡ +void PWM_SetHDuty(PWM_TypeDef * PWMx, uint32_t chn, uint16_t hduty); //øߵƽʱ +uint16_t PWM_GetHDuty(PWM_TypeDef * PWMx, uint32_t chn); //ȡߵƽʱ +void PWM_SetHDuty2(PWM_TypeDef * PWMx, uint32_t chn, uint16_t hduty, uint16_t hduty2); //øߵƽʱڷǶԳĶģʽ +void PWM_GetHDuty2(PWM_TypeDef * PWMx, uint32_t chn, uint16_t *hduty, uint16_t *hduty2); //ȡߵƽʱڷǶԳĶģʽ +void PWM_SetDeadzone(PWM_TypeDef * PWMx, uint32_t chn, uint16_t deadzone); //ʱ +uint16_t PWM_GetDeadzone(PWM_TypeDef * PWMx, uint32_t chn); //ȡʱ + +void PWM_IntEn(PWM_TypeDef * PWMx, uint32_t it); //жʹ +void PWM_IntDis(PWM_TypeDef * PWMx, uint32_t it); //жϽ +void PWM_IntClr(PWM_TypeDef * PWMx, uint32_t it); //жϱ־ +uint32_t PWM_IntStat(PWM_TypeDef * PWMx, uint32_t it); //жϱ־ѯ +void PWM_BrkIntEn(uint32_t brkit); //ɲжʹ +void PWM_BrkIntDis(uint32_t brkit); //ɲжϽ +void PWM_BrkIntClr(uint32_t brkit); //ɲжϱ־ +uint32_t PWM_BrkIntStat(uint32_t brkit); //ɲжϱ־ѯ + + +#endif //__SWM221_PWM_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_qei.c b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_qei.c new file mode 100644 index 0000000..241621d --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_qei.c @@ -0,0 +1,146 @@ +/****************************************************************************************************************************************** +* ļ: SWM221_qei.c +* ˵: SWM221ƬӿQEI +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.0.0 20130630 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM221.h" +#include "SWM221_qei.h" + + +/****************************************************************************************************************************************** +* : QEI_Init() +* ˵: ӿQEIʼ +* : QEI_TypeDef * QEIx ָҪõӿڣЧֵQEI +* QEI_InitStructure * initStruct ӿ趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void QEI_Init(QEI_TypeDef * QEIx,QEI_InitStructure * initStruct) +{ + switch((uint32_t)QEIx) + { + case ((uint32_t)QEI): + SYS->CLKEN0 |= (1 << SYS_CLKEN0_QEI_Pos); + break; + } + + QEI_Stop(QEIx); //ǰرQEIģ + + QEIx->CR = (initStruct->swapAB << QEI_CR_ABSWAP_Pos) | + (initStruct->mode << QEI_CR_X2X4_Pos) | + (1 << QEI_CR_RSTSRC_Pos) | + (1 << QEI_CR_MODE_Pos); + + QEIx->POSCNT = 0; + QEIx->MAXCNT = initStruct->maxcnt; + + QEIx->IC = 0x0F; + QEIx->IE = 0x0F; + QEIx->IM = (initStruct->intINDEXEn << QEI_IM_INDEX_Pos) | + (initStruct->intMATCHEn << QEI_IM_MATCH_Pos) | + (initStruct->intCNTOVEn << QEI_IM_CNTOV_Pos) | + (initStruct->intERROREn << QEI_IM_ERROR_Pos); + + if(initStruct->intINDEXEn | initStruct->intMATCHEn | initStruct->intCNTOVEn | initStruct->intERROREn) + { + NVIC_EnableIRQ(GPIOB4_GPIOB10_QEI_IRQn); + } +} + +/****************************************************************************************************************************************** +* : QEI_Start() +* ˵: ָQEI +* : QEI_TypeDef * QEIx ָҪõӿڣЧֵQEI +* : +* ע: +******************************************************************************************************************************************/ +void QEI_Start(QEI_TypeDef * QEIx) +{ + QEIx->CR |= (1 << QEI_CR_ENA_Pos); +} + +/****************************************************************************************************************************************** +* : QEI_Stop() +* ˵: رָQEI +* : QEI_TypeDef * QEIx ָҪõӿڣЧֵQEI +* : +* ע: +******************************************************************************************************************************************/ +void QEI_Stop(QEI_TypeDef * QEIx) +{ + QEIx->CR &= ~(1 << QEI_CR_ENA_Pos); +} + +/****************************************************************************************************************************************** +* : QEI_IntEn() +* ˵: QEIжʹ +* : QEI_TypeDef * QEIx ָҪõӿڣЧֵQEI +* uint32_t it interrupt typeȡֵQEI_IT_INDEXQEI_IT_MATCHQEI_IT_CNTOVQEI_IT_ERROR +* : +* ע: +******************************************************************************************************************************************/ +void QEI_IntEn(QEI_TypeDef * QEIx, uint32_t it) +{ + QEIx->IM |= it; + + switch((uint32_t)QEIx) + { + case ((uint32_t)QEI): + NVIC_EnableIRQ(GPIOB4_GPIOB10_QEI_IRQn); + break; + } +} + +/****************************************************************************************************************************************** +* : QEI_IntDis() +* ˵: QEIжϹر +* : QEI_TypeDef * QEIx ָҪõӿڣЧֵQEI +* uint32_t it interrupt typeȡֵQEI_IT_INDEXQEI_IT_MATCHQEI_IT_CNTOVQEI_IT_ERROR +* : +* ע: +******************************************************************************************************************************************/ +void QEI_IntDis(QEI_TypeDef * QEIx, uint32_t it) +{ + QEIx->IM &= ~it; +} + +/****************************************************************************************************************************************** +* : QEI_IntClr() +* ˵: QEIжϱ־ +* : QEI_TypeDef * QEIx ָҪõӿڣЧֵQEI +* uint32_t it interrupt typeȡֵQEI_IT_INDEXQEI_IT_MATCHQEI_IT_CNTOVQEI_IT_ERROR +* : +* ע: +******************************************************************************************************************************************/ +void QEI_IntClr(QEI_TypeDef * QEIx, uint32_t it) +{ + QEIx->IC = it; +} + +/****************************************************************************************************************************************** +* : QEI_IntStat() +* ˵: QEIж״̬ѯ +* : QEI_TypeDef * QEIx ָҪõӿڣЧֵQEI +* uint32_t it interrupt typeȡֵQEI_IT_INDEXQEI_IT_MATCHQEI_IT_CNTOVQEI_IT_ERROR +* : uint32_t 0 ûжϷ 0ֵ жϷ +* ע: +******************************************************************************************************************************************/ +uint32_t QEI_IntStat(QEI_TypeDef * QEIx, uint32_t it) +{ + return (QEIx->IF & it); +} diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_qei.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_qei.h new file mode 100644 index 0000000..d25534f --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_qei.h @@ -0,0 +1,37 @@ +#ifndef __SWM221_QEI_H__ +#define __SWM221_QEI_H__ + +typedef struct { + uint8_t mode; //QEI_MODE_X2QEI_MODE_X4 + uint16_t maxcnt; //ֵ + uint8_t swapAB; //1 AB + uint8_t intINDEXEn; //⵽Indexжʹ + uint8_t intMATCHEn; //POSCNTMAXCNTȣPOSCNTMAXCNTݼ0жʹ + uint8_t intCNTOVEn; //Counter Overrunжʹ + uint8_t intERROREn; //жʹ +} QEI_InitStructure; + + +#define QEI_MODE_X2 0 +#define QEI_MODE_X4 1 + +#define QEI_IT_INDEX (1 << 0) +#define QEI_IT_MATCH (1 << 1) +#define QEI_IT_CNTOV (1 << 2) +#define QEI_IT_ERROR (1 << 3) + + +void QEI_Init(QEI_TypeDef * QEIx, QEI_InitStructure * initStruct); //QEIʼ +void QEI_Start(QEI_TypeDef * QEIx); //QEI +void QEI_Stop(QEI_TypeDef * QEIx); //رQEI + +uint32_t QEI_IndexLvl(QEI_TypeDef * QEIx); //QEI Indexŵƽ +uint32_t QEI_CountDir(QEI_TypeDef * QEIx); //QEI0 1 + +void QEI_IntEn(QEI_TypeDef * QEIx, uint32_t it); //QEIжʹ +void QEI_IntDis(QEI_TypeDef * QEIx, uint32_t it); //QEIжϹر +void QEI_IntClr(QEI_TypeDef * QEIx, uint32_t it); //QEIжϱ־ +uint32_t QEI_IntStat(QEI_TypeDef * QEIx, uint32_t it); //QEIж״̬ѯ + + +#endif //__SWM221_QEI_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_qspi.c b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_qspi.c new file mode 100644 index 0000000..2bdee0c --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_qspi.c @@ -0,0 +1,734 @@ +/****************************************************************************************************************************************** +* ļ: SWM342_qspi.c +* ˵: SWM342ƬQSPIģ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.1.0 20171025 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM221.h" +#include "SWM221_qspi.h" + + +static uint8_t AddressSize; + + +/****************************************************************************************************************************************** +* : QSPI_Init() +* ˵: QSPI ʼ +* : QSPI_TypeDef * QSPIx ָҪõQSPIӿڣЧֵQSPI0 +* QSPI_InitStructure * initStruct QSPIӿ趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void QSPI_Init(QSPI_TypeDef * QSPIx, QSPI_InitStructure * initStruct) +{ + switch((uint32_t)QSPIx) + { + case ((uint32_t)QSPI0): + SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_QSPI0_Pos); + break; + } + + QSPI_Close(QSPIx); + + QSPIx->CR = (0 << QSPI_CR_SSHIFT_Pos) | + (7 << QSPI_CR_FFTHR_Pos) | + (initStruct->IntEn << QSPI_CR_ERRIE_Pos) | + ((initStruct->ClkDiv-1) << QSPI_CR_CLKDIV_Pos); + + QSPIx->DCR = (initStruct->ClkMode << QSPI_DCR_CLKMOD_Pos) | + (3 << QSPI_DCR_CSHIGH_Pos) | + (initStruct->Size << QSPI_DCR_FLSIZE_Pos); + + AddressSize = initStruct->Size / 8; + + QSPIx->SSHIFT = ((initStruct->SampleShift & 0x0F) << QSPI_SSHIFT_CYCLE_Pos) | + (2 << QSPI_SSHIFT_SPACE_Pos); + + QSPIx->FCR = 0x1B; + if(initStruct->IntEn) + { + switch((uint32_t)QSPIx) + { + case ((uint32_t)QSPI0): NVIC_EnableIRQ(QSPI0_IRQn); break; + } + } +} + + +/****************************************************************************************************************************************** +* : QSPI_Open() +* ˵: QSPIӿڴ +* : QSPI_TypeDef * QSPIx ָҪõQSPIӿڣЧֵQSPI0 +* : +* ע: +******************************************************************************************************************************************/ +void QSPI_Open(QSPI_TypeDef * QSPIx) +{ + QSPIx->CR |= QSPI_CR_EN_Msk; +} + + +/****************************************************************************************************************************************** +* : QSPI_Close() +* ˵: QSPIӿڹر +* : QSPI_TypeDef * QSPIx ָҪõQSPIӿڣЧֵQSPI0 +* : +* ע: +******************************************************************************************************************************************/ +void QSPI_Close(QSPI_TypeDef * QSPIx) +{ + QSPIx->CR &= ~QSPI_CR_EN_Msk; +} + + +void QSPI_CmdStructClear(QSPI_CmdStructure * cmdStruct) +{ + cmdStruct->Instruction = 0; + cmdStruct->InstructionMode = 0; + cmdStruct->Address = 0; + cmdStruct->AddressMode = 0; + cmdStruct->AddressSize = 0; + cmdStruct->AlternateBytes = 0; + cmdStruct->AlternateBytesMode = 0; + cmdStruct->AlternateBytesSize = 0; + cmdStruct->DummyCycles = 0; + cmdStruct->DataMode = 0; + cmdStruct->DataCount = 0; + cmdStruct->SendInstOnlyOnce = 0; +} + + +/****************************************************************************************************************************************** +* : QSPI_Command() +* ˵: QSPIִ +* : QSPI_TypeDef * QSPIx ָҪõQSPIӿڣЧֵQSPI0 +* QSPI_CmdStructure * cmdStruct Ҫִ +* : +* ע: +******************************************************************************************************************************************/ +void QSPI_Command(QSPI_TypeDef * QSPIx, uint8_t cmdMode, QSPI_CmdStructure * cmdStruct) +{ + if(cmdStruct->AlternateBytesMode != QSPI_PhaseMode_None) + QSPIx->ABR = cmdStruct->AlternateBytes; + + if(cmdStruct->DataMode != QSPI_PhaseMode_None) + QSPIx->DLR = cmdStruct->DataCount - 1; + + QSPIx->CCR = (cmdStruct->Instruction << QSPI_CCR_CODE_Pos) | + (cmdStruct->InstructionMode << QSPI_CCR_IMODE_Pos) | + (cmdStruct->AddressMode << QSPI_CCR_AMODE_Pos) | + (cmdStruct->AddressSize << QSPI_CCR_ASIZE_Pos) | + (cmdStruct->AlternateBytesMode << QSPI_CCR_ABMODE_Pos) | + (cmdStruct->AlternateBytesSize << QSPI_CCR_ABSIZE_Pos) | + (cmdStruct->DummyCycles << QSPI_CCR_DUMMY_Pos) | + (cmdStruct->DataMode << QSPI_CCR_DMODE_Pos) | + (cmdMode << QSPI_CCR_MODE_Pos) | + (cmdStruct->SendInstOnlyOnce << QSPI_CCR_SIOO_Pos); + + if(cmdStruct->AddressMode != QSPI_PhaseMode_None) + QSPIx->AR = cmdStruct->Address; + + for(int i = 0; i < 3; i++) __NOP(); +} + + +/****************************************************************************************************************************************** +* : QSPI_Erase_() +* ˵: QSPI Flash +* : QSPI_TypeDef * QSPIx ָҪõQSPIӿڣЧֵQSPI0 +* uint32_t addr Ҫ SPI Flash ַ +* uint16_t block_size ҪĿСλΪ kbytesЧֵ 464 +* uint8_t wait Ƿȴ SPI Flash ɲ1 ȴ 0 +* : +* ע: wait == 0 أҪ QSPI_FlashBusy() SPI Flash ɲִжд +******************************************************************************************************************************************/ +void QSPI_Erase_(QSPI_TypeDef * QSPIx, uint32_t addr, uint16_t block_size, uint8_t wait) +{ + QSPI_CmdStructure cmdStruct; + QSPI_CmdStructClear(&cmdStruct); + + uint8_t instruction; + switch(block_size) + { + case 4: + instruction = (AddressSize == QSPI_PhaseSize_32bit) ? QSPI_C4B_ERASE_SECTOR : QSPI_CMD_ERASE_SECTOR; + break; + + case 64: + instruction = (AddressSize == QSPI_PhaseSize_32bit) ? QSPI_C4B_ERASE_BLOCK64KB : QSPI_CMD_ERASE_BLOCK64KB; + break; + } + + cmdStruct.InstructionMode = QSPI_PhaseMode_1bit; + cmdStruct.Instruction = instruction; + cmdStruct.AddressMode = QSPI_PhaseMode_1bit; + cmdStruct.AddressSize = AddressSize; + cmdStruct.Address = addr; + cmdStruct.AlternateBytesMode = QSPI_PhaseMode_None; + cmdStruct.DummyCycles = 0; + cmdStruct.DataMode = QSPI_PhaseMode_None; + + QSPI_WriteEnable(QSPIx); + + QSPI_Command(QSPIx, QSPI_Mode_IndirectWrite, &cmdStruct); + + while(QSPI_Busy(QSPIx)) __NOP(); + + if(wait) + while(QSPI_FlashBusy(QSPIx)) __NOP(); +} + + +/****************************************************************************************************************************************** +* : QSPI_Write_() +* ˵: QSPI Flash д +* : QSPI_TypeDef * QSPIx ָҪõQSPIӿڣЧֵQSPI0 +* uint32_t addr Ҫд뵽 SPI Flash ַ +* uint8_t buff[] Ҫд SPI Flash +* uint32_t count Ҫд SPI Flash ݸ 256дݲܿҳ +* uint8_t data_width дʹõ߸Чֵ 14 +* uint8_t data_phase Ƿڴ˺ִݽ׶Σ񣬿ںͨ DMA ʵָЧд +* : +* ע: +******************************************************************************************************************************************/ +void QSPI_Write_(QSPI_TypeDef * QSPIx, uint32_t addr, uint8_t buff[], uint32_t count, uint8_t data_width, uint8_t data_phase) +{ + QSPI_CmdStructure cmdStruct; + QSPI_CmdStructClear(&cmdStruct); + + uint8_t instruction, dataMode; + switch(data_width) + { + case 1: + instruction = (AddressSize == QSPI_PhaseSize_32bit) ? QSPI_C4B_PAGE_PROGRAM : QSPI_CMD_PAGE_PROGRAM; + dataMode = QSPI_PhaseMode_1bit; + break; + + case 4: + instruction = (AddressSize == QSPI_PhaseSize_32bit) ? QSPI_C4B_PAGE_PROGRAM_4bit : QSPI_CMD_PAGE_PROGRAM_4bit; + dataMode = QSPI_PhaseMode_4bit; + break; + } + + cmdStruct.InstructionMode = QSPI_PhaseMode_1bit; + cmdStruct.Instruction = instruction; + cmdStruct.AddressMode = QSPI_PhaseMode_1bit; + cmdStruct.AddressSize = AddressSize; + cmdStruct.Address = addr; + cmdStruct.AlternateBytesMode = QSPI_PhaseMode_None; + cmdStruct.DummyCycles = 0; + cmdStruct.DataMode = dataMode; + cmdStruct.DataCount = count; + + QSPI_WriteEnable(QSPIx); + + QSPI_Command(QSPIx, QSPI_Mode_IndirectWrite, &cmdStruct); + + if(data_phase == 0) + return; + + if((uint32_t)buff % 4 == 0) // word aligned + { + uint32_t n_word = count / 4; + + for(int i = 0; i < n_word; i++) + { + uint32_t * p_word = (uint32_t *)buff; + + while(QSPI_FIFOSpace(QSPIx) < 4) __NOP(); + + QSPIx->DRW = p_word[i]; + } + + if((count % 4) / 2) + { + uint16_t * p_half = (uint16_t *)&buff[n_word * 4]; + + while(QSPI_FIFOSpace(QSPIx) < 2) __NOP(); + + QSPIx->DRH = p_half[0]; + } + + if(count % 2) + { + while(QSPI_FIFOSpace(QSPIx) < 1) __NOP(); + + QSPIx->DRB = buff[count - 1]; + } + } + else + { + for(int i = 0; i < count; i++) + { + while(QSPI_FIFOSpace(QSPIx) < 1) __NOP(); + + QSPIx->DRB = buff[i]; + } + } + + while(QSPI_Busy(QSPIx)) __NOP(); + + while(QSPI_FlashBusy(QSPIx)) __NOP(); +} + + +/****************************************************************************************************************************************** +* : QSPI_Read_() +* ˵: QSPI Flash ȡ +* : QSPI_TypeDef * QSPIx ָҪõQSPIӿڣЧֵQSPI0 +* uint32_t addr ҪȡԵ SPI Flash ַ +* uint8_t buff[] ȡд +* uint32_t count Ҫȡݵĸ +* uint8_t addr_width ȡʹõĵַ߸Чֵ 124 +* uint8_t data_width ȡʹõ߸Чֵ 124 +* uint8_t data_phase Ƿڴ˺ִݽ׶Σ񣬿ںͨ DMA ʵָЧĶȡ +* : +* ע: +******************************************************************************************************************************************/ +void QSPI_Read_(QSPI_TypeDef * QSPIx, uint32_t addr, uint8_t buff[], uint32_t count, uint8_t addr_width, uint8_t data_width, uint8_t data_phase) +{ + QSPI_CmdStructure cmdStruct; + QSPI_CmdStructClear(&cmdStruct); + + uint8_t instruction, addressMode, dataMode, dummyCycles; + uint8_t alternateBytesMode, alternateBytesSize, alternateBytes; + switch((addr_width << 4) | data_width) + { + case 0x11: + instruction = (AddressSize == QSPI_PhaseSize_32bit) ? QSPI_C4B_FAST_READ : QSPI_CMD_FAST_READ; + addressMode = QSPI_PhaseMode_1bit; + alternateBytesMode = QSPI_PhaseMode_None; + alternateBytesSize = 0; + dummyCycles = 8; + dataMode = QSPI_PhaseMode_1bit; + break; + + case 0x12: + instruction = (AddressSize == QSPI_PhaseSize_32bit) ? QSPI_C4B_FAST_READ_2bit : QSPI_CMD_FAST_READ_2bit; + addressMode = QSPI_PhaseMode_1bit; + alternateBytesMode = QSPI_PhaseMode_None; + alternateBytesSize = 0; + dummyCycles = 8; + dataMode = QSPI_PhaseMode_2bit; + break; + + case 0x22: + instruction = (AddressSize == QSPI_PhaseSize_32bit) ? QSPI_C4B_FAST_READ_IO2bit : QSPI_CMD_FAST_READ_IO2bit; + addressMode = QSPI_PhaseMode_2bit; + alternateBytesMode = QSPI_PhaseMode_2bit; + alternateBytesSize = QSPI_PhaseSize_8bit; + alternateBytes = 0xFF; + dummyCycles = 0; + dataMode = QSPI_PhaseMode_2bit; + break; + + case 0x14: + instruction = (AddressSize == QSPI_PhaseSize_32bit) ? QSPI_C4B_FAST_READ_4bit : QSPI_CMD_FAST_READ_4bit; + addressMode = QSPI_PhaseMode_1bit; + alternateBytesMode = QSPI_PhaseMode_None; + alternateBytesSize = 0; + dummyCycles = 8; + dataMode = QSPI_PhaseMode_4bit; + break; + + case 0x44: + instruction = (AddressSize == QSPI_PhaseSize_32bit) ? QSPI_C4B_FAST_READ_IO4bit : QSPI_CMD_FAST_READ_IO4bit; + addressMode = QSPI_PhaseMode_4bit; + alternateBytesMode = QSPI_PhaseMode_4bit; + alternateBytesSize = QSPI_PhaseSize_8bit; + alternateBytes = 0xFF; + dummyCycles = 4; + dataMode = QSPI_PhaseMode_4bit; + break; + } + + cmdStruct.InstructionMode = QSPI_PhaseMode_1bit; + cmdStruct.Instruction = instruction; + cmdStruct.AddressMode = addressMode; + cmdStruct.AddressSize = AddressSize; + cmdStruct.Address = addr; + cmdStruct.AlternateBytesMode = alternateBytesMode; + cmdStruct.AlternateBytesSize = alternateBytesSize; + cmdStruct.AlternateBytes = alternateBytes; + cmdStruct.DummyCycles = dummyCycles; + cmdStruct.DataMode = dataMode; + cmdStruct.DataCount = count; + + QSPI_Command(QSPIx, QSPI_Mode_IndirectRead, &cmdStruct); + + if(data_phase == 0) + return; + + if((uint32_t)buff % 4 == 0) // word aligned + { + uint32_t n_word = count / 4; + + for(int i = 0; i < n_word; i++) + { + uint32_t * p_word = (uint32_t *)buff; + + while(QSPI_FIFOCount(QSPIx) < 4) __NOP(); + + p_word[i] = QSPIx->DRW; + } + + if((count % 4) / 2) + { + uint16_t * p_half = (uint16_t *)&buff[n_word * 4]; + + while(QSPI_FIFOCount(QSPIx) < 2) __NOP(); + + p_half[0] = QSPIx->DRH; + } + + if(count % 2) + { + while(QSPI_FIFOCount(QSPIx) < 1) __NOP(); + + buff[count - 1] = QSPIx->DRB; + } + } + else + { + for(int i = 0; i < count; i++) + { + while(QSPI_FIFOCount(QSPIx) < 1) __NOP(); + + buff[i] = QSPIx->DRB; + } + } + + QSPI_Abort(QSPIx); +} + + +/****************************************************************************************************************************************** +* : QSPI_FlashBusy() +* ˵: QSPI Flash æѯ +* : QSPI_TypeDef * QSPIx ָҪõQSPIӿڣЧֵQSPI0 +* : bool SPI Flash Ƿִڲд +* ע: +******************************************************************************************************************************************/ +bool QSPI_FlashBusy(QSPI_TypeDef * QSPIx) +{ + uint16_t reg = QSPI_ReadReg(QSPIx, QSPI_CMD_READ_STATUS_REG1, 1); + + bool busy = (reg & (1 << QSPI_STATUS_REG1_BUSY_Pos)); + + return busy; +} + + +/****************************************************************************************************************************************** +* : QSPI_QuadState() +* ˵: QSPI Flash QE ѯ +* : QSPI_TypeDef * QSPIx ָҪõQSPIӿڣЧֵQSPI0 +* : uint8_t 1 QE ʹ 0 QE ֹ +* ע: ͬƷ SPI Flash УQE Status Register еλÿܲͬ +******************************************************************************************************************************************/ +uint8_t QSPI_QuadState(QSPI_TypeDef * QSPIx) +{ + uint8_t reg = QSPI_ReadReg(QSPIx, QSPI_CMD_READ_STATUS_REG2, 1); + + return (reg & (1 << QSPI_STATUS_REG2_QUAD_Pos)) ? 1 : 0; +} + + +/****************************************************************************************************************************************** +* : QSPI_QuadSwitch() +* ˵: QSPI Flash QE +* : QSPI_TypeDef * QSPIx ָҪõQSPIӿڣЧֵQSPI0 +* uint8_t on 1 QE ʹ 0 QE ֹ +* : +* ע: ͬƷ SPI Flash УQE Status Register еλÿܲͬ +******************************************************************************************************************************************/ +void QSPI_QuadSwitch(QSPI_TypeDef * QSPIx, uint8_t on) +{ + uint8_t reg = QSPI_ReadReg(QSPIx, QSPI_CMD_READ_STATUS_REG2, 1); + + if(on) + reg |= (1 << QSPI_STATUS_REG2_QUAD_Pos); + else + reg &= ~(1 << QSPI_STATUS_REG2_QUAD_Pos); + + QSPI_WriteEnable(QSPIx); + + QSPI_WriteReg(QSPIx, QSPI_CMD_WRITE_STATUS_REG2, reg, 1); + + while(QSPI_FlashBusy(QSPIx)) __NOP(); +} + + +/****************************************************************************************************************************************** +* : QSPI_ReadReg() +* ˵: QSPI Flash Ĵȡֻݽ׶Σݲ4ֽڵ +* : QSPI_TypeDef * QSPIx ָҪõQSPIӿڣЧֵQSPI0 +* uint8_t cmd Ĵȡ +* uint8_t n_bytes Ҫȡֽȡֵ 1234 +* : uint32_t ȡݣMSB +* ע: +******************************************************************************************************************************************/ +uint32_t QSPI_ReadReg(QSPI_TypeDef * QSPIx, uint8_t cmd, uint8_t n_bytes) +{ + QSPI_CmdStructure cmdStruct; + QSPI_CmdStructClear(&cmdStruct); + + cmdStruct.InstructionMode = QSPI_PhaseMode_1bit; + cmdStruct.Instruction = cmd; + cmdStruct.AddressMode = QSPI_PhaseMode_None; + cmdStruct.AlternateBytesMode = QSPI_PhaseMode_None; + cmdStruct.DummyCycles = 0; + cmdStruct.DataMode = QSPI_PhaseMode_1bit; + cmdStruct.DataCount = n_bytes; + + QSPI_Command(QSPIx, QSPI_Mode_IndirectRead, &cmdStruct); + + while(QSPI_FIFOCount(QSPIx) < n_bytes) __NOP(); + + uint32_t data = 0; + for(int i = n_bytes; i > 0; i--) + ((uint8_t *)&data)[i-1] = QSPIx->DRB; + + return data; +} + + +/****************************************************************************************************************************************** +* : QSPI_WriteReg() +* ˵: QSPI Flash Ĵд룬ֻݽ׶Σݲ4ֽڵ +* : QSPI_TypeDef * QSPIx ָҪõQSPIӿڣЧֵQSPI0 +* uint8_t cmd Ĵд +* uint32_t data ҪдĴݣMSB +* uint8_t n_bytes ҪдĴֽȡֵ 12340ݽ׶ +* : +* ע: +******************************************************************************************************************************************/ +void QSPI_WriteReg(QSPI_TypeDef * QSPIx, uint8_t cmd, uint32_t data, uint8_t n_bytes) +{ + QSPI_CmdStructure cmdStruct; + QSPI_CmdStructClear(&cmdStruct); + + cmdStruct.InstructionMode = QSPI_PhaseMode_1bit; + cmdStruct.Instruction = cmd; + cmdStruct.AddressMode = QSPI_PhaseMode_None; + cmdStruct.AlternateBytesMode = QSPI_PhaseMode_None; + cmdStruct.DummyCycles = 0; + cmdStruct.DataMode = n_bytes ? QSPI_PhaseMode_1bit : QSPI_PhaseMode_None; + cmdStruct.DataCount = n_bytes; + + QSPI_Command(QSPIx, QSPI_Mode_IndirectWrite, &cmdStruct); + + for(int i = n_bytes; i > 0; i--) + QSPIx->DRB = ((uint8_t *)&data)[i-1]; + + while(QSPI_Busy(QSPIx)) __NOP(); +} + + +/****************************************************************************************************************************************** +* : QSPI_INTEn() +* ˵: жʹ +* : QSPI_TypeDef * QSPIx ָҪõQSPIӿڣЧֵQSPI0 +* uint32_t it interrupt typeȡֵ QSPI_IT_ERRQSPI_IT_DONEQSPI_IT_FFTHRQSPI_IT_PSMATQSPI_IT_TO 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void QSPI_INTEn(QSPI_TypeDef * QSPIx, uint32_t it) +{ + QSPIx->CR |= (it << 16); +} + +/****************************************************************************************************************************************** +* : QSPI_INTDis() +* ˵: жϽֹ +* : QSPI_TypeDef * QSPIx ָҪõQSPIӿڣЧֵQSPI0 +* uint32_t it interrupt typeȡֵ QSPI_IT_ERRQSPI_IT_DONEQSPI_IT_FFTHRQSPI_IT_PSMATQSPI_IT_TO 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void QSPI_INTDis(QSPI_TypeDef * QSPIx, uint32_t it) +{ + QSPIx->CR &= ~(it << 16); +} + +/****************************************************************************************************************************************** +* : QSPI_INTClr() +* ˵: жϱ־ +* : QSPI_TypeDef * QSPIx ָҪõQSPIӿڣЧֵQSPI0 +* uint32_t it interrupt typeȡֵ QSPI_IT_ERRQSPI_IT_DONEQSPI_IT_PSMATQSPI_IT_TO 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void QSPI_INTClr(QSPI_TypeDef * QSPIx, uint32_t it) +{ + QSPIx->FCR = it; +} + +/****************************************************************************************************************************************** +* : QSPI_INTStat() +* ˵: ж״̬ѯ +* : QSPI_TypeDef * QSPIx ָҪõQSPIӿڣЧֵQSPI0 +* uint32_t it interrupt typeȡֵ QSPI_IT_ERRQSPI_IT_DONEQSPI_IT_FFTHRQSPI_IT_PSMATQSPI_IT_TO 䡰 +* : uint32_t 0 жδ 0 жѷ +* ע: +******************************************************************************************************************************************/ +uint32_t QSPI_INTStat(QSPI_TypeDef * QSPIx, uint32_t it) +{ + return QSPIx->SR & it; +} + + +/****************************************************************************************************************************************** +* : QSPI_SPI_Write_() +* ˵: QSPI ͨ SPI д +* : QSPI_TypeDef * QSPIx ָҪõQSPIӿڣЧֵQSPI0 +* uint8_t buff[] Ҫд +* uint32_t count Ҫдݸ +* uint8_t data_width дʹõ߸Чֵ 124 +* uint8_t data_phase Ƿڴ˺ִݽ׶Σ񣬿ںͨ DMA ʵָЧд +* : +* ע: +******************************************************************************************************************************************/ +void QSPI_SPI_Write_(QSPI_TypeDef * QSPIx, uint8_t buff[], uint32_t count, uint8_t data_width, uint8_t data_phase) +{ + QSPI_CmdStructure cmdStruct; + QSPI_CmdStructClear(&cmdStruct); + + cmdStruct.InstructionMode = QSPI_PhaseMode_None; + cmdStruct.AddressMode = QSPI_PhaseMode_None; + cmdStruct.AlternateBytesMode = QSPI_PhaseMode_None; + cmdStruct.DummyCycles = 0; + cmdStruct.DataMode = (data_width == 1) ? QSPI_PhaseMode_1bit : ((data_width == 2) ? QSPI_PhaseMode_2bit : QSPI_PhaseMode_4bit); + cmdStruct.DataCount = count; + + QSPI_Command(QSPIx, QSPI_Mode_IndirectWrite, &cmdStruct); + + if(data_phase == 0) + return; + + if((uint32_t)buff % 4 == 0) // word aligned + { + uint32_t n_word = count / 4; + + for(int i = 0; i < n_word; i++) + { + uint32_t * p_word = (uint32_t *)buff; + + while(QSPI_FIFOSpace(QSPIx) < 4) __NOP(); + + QSPIx->DRW = p_word[i]; + } + + if((count % 4) / 2) + { + uint16_t * p_half = (uint16_t *)&buff[n_word * 4]; + + while(QSPI_FIFOSpace(QSPIx) < 2) __NOP(); + + QSPIx->DRH = p_half[0]; + } + + if(count % 2) + { + while(QSPI_FIFOSpace(QSPIx) < 1) __NOP(); + + QSPIx->DRB = buff[count - 1]; + } + } + else + { + for(int i = 0; i < count; i++) + { + while(QSPI_FIFOSpace(QSPIx) < 1) __NOP(); + + QSPIx->DRB = buff[i]; + } + } + + while(QSPI_Busy(QSPIx)) __NOP(); +} + + +/****************************************************************************************************************************************** +* : QSPI_SPI_Read_() +* ˵: QSPI ͨ SPI +* : QSPI_TypeDef * QSPIx ָҪõQSPIӿڣЧֵQSPI0 +* uint8_t buff[] ȡд +* uint32_t count Ҫȡݵĸ +* uint8_t data_width ȡʹõ߸Чֵ 124 +* uint8_t data_phase Ƿڴ˺ִݽ׶Σ񣬿ںͨ DMA ʵָЧĶȡ +* : +* ע: +******************************************************************************************************************************************/ +void QSPI_SPI_Read_(QSPI_TypeDef * QSPIx, uint8_t buff[], uint32_t count, uint8_t data_width, uint8_t data_phase) +{ + QSPI_CmdStructure cmdStruct; + QSPI_CmdStructClear(&cmdStruct); + + cmdStruct.InstructionMode = QSPI_PhaseMode_None; + cmdStruct.AddressMode = QSPI_PhaseMode_None; + cmdStruct.AlternateBytesMode = QSPI_PhaseMode_None; + cmdStruct.DummyCycles = 0; + cmdStruct.DataMode = (data_width == 1) ? QSPI_PhaseMode_1bit : ((data_width == 2) ? QSPI_PhaseMode_2bit : QSPI_PhaseMode_4bit); + cmdStruct.DataCount = count; + + QSPI_Command(QSPIx, QSPI_Mode_IndirectRead, &cmdStruct); + + if(data_phase == 0) + return; + + if((uint32_t)buff % 4 == 0) // word aligned + { + uint32_t n_word = count / 4; + + for(int i = 0; i < n_word; i++) + { + uint32_t * p_word = (uint32_t *)buff; + + while(QSPI_FIFOCount(QSPIx) < 4) __NOP(); + + p_word[i] = QSPIx->DRW; + } + + if((count % 4) / 2) + { + uint16_t * p_half = (uint16_t *)&buff[n_word * 4]; + + while(QSPI_FIFOCount(QSPIx) < 2) __NOP(); + + p_half[0] = QSPIx->DRH; + } + + if(count % 2) + { + while(QSPI_FIFOCount(QSPIx) < 1) __NOP(); + + buff[count - 1] = QSPIx->DRB; + } + } + else + { + for(int i = 0; i < count; i++) + { + while(QSPI_FIFOCount(QSPIx) < 1) __NOP(); + + buff[i] = QSPIx->DRB; + } + } + + QSPI_Abort(QSPIx); +} diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_qspi.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_qspi.h new file mode 100644 index 0000000..a941d20 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_qspi.h @@ -0,0 +1,215 @@ +#ifndef __SWM221_QSPI_H__ +#define __SWM221_QSPI_H__ + + +typedef struct { + uint16_t Size; // Flash С + uint16_t ClkDiv; // ȡֵ 2--256 + uint8_t ClkMode; // ȡֵ QSPI_ClkMode_0QSPI_ClkMode_3 + uint8_t SampleShift; // ȡֵ QSPI_SampleShift_NoneQSPI_SampleShift_1_SYSCLK... + uint8_t IntEn; // ȡֵ QSPI_IT_ERRQSPI_IT_DONEQSPI_IT_FFTHRQSPI_IT_PSMATQSPI_IT_TO 䡰 +} QSPI_InitStructure; + +#define QSPI_Size_1MB 19 +#define QSPI_Size_2MB 20 +#define QSPI_Size_4MB 21 +#define QSPI_Size_8MB 22 +#define QSPI_Size_16MB 23 +#define QSPI_Size_32MB 24 +#define QSPI_Size_64MB 25 +#define QSPI_Size_128MB 26 +#define QSPI_Size_256MB 27 +#define QSPI_Size_512MB 28 + +#define QSPI_ClkMode_0 0 +#define QSPI_ClkMode_3 1 + +#define QSPI_SampleShift_NONE 0 +#define QSPI_SampleShift_1_SYSCLK 1 +#define QSPI_SampleShift_2_SYSCLK 2 +#define QSPI_SampleShift_3_SYSCLK 3 +#define QSPI_SampleShift_4_SYSCLK 4 +#define QSPI_SampleShift_5_SYSCLK 5 +#define QSPI_SampleShift_6_SYSCLK 6 +#define QSPI_SampleShift_7_SYSCLK 7 + + +typedef struct { + uint8_t Instruction; // ָ + uint8_t InstructionMode; // ȡֵQSPI_PhaseMode_NoneQSPI_PhaseMode_1bitQSPI_PhaseMode_2bitQSPI_PhaseMode_4bit + uint32_t Address; + uint8_t AddressMode; // ȡֵQSPI_PhaseMode_NoneQSPI_PhaseMode_1bitQSPI_PhaseMode_2bitQSPI_PhaseMode_4bit + uint8_t AddressSize; // ȡֵQSPI_PhaseSize_8bitQSPI_PhaseSize_16bitQSPI_PhaseSize_24bitQSPI_PhaseSize_32bit + uint32_t AlternateBytes; + uint8_t AlternateBytesMode; // ȡֵQSPI_PhaseMode_NoneQSPI_PhaseMode_1bitQSPI_PhaseMode_2bitQSPI_PhaseMode_4bit + uint8_t AlternateBytesSize; // ȡֵQSPI_PhaseSize_8bitQSPI_PhaseSize_16bitQSPI_PhaseSize_24bitQSPI_PhaseSize_32bit + uint8_t DummyCycles; // ȡֵ0--31 + uint8_t DataMode; // ȡֵQSPI_PhaseMode_NoneQSPI_PhaseMode_1bitQSPI_PhaseMode_2bitQSPI_PhaseMode_4bit + uint32_t DataCount; // Ҫдݵֽڸ0 ʾһֱдֱ洢ĩβ + uint8_t SendInstOnlyOnce; +} QSPI_CmdStructure; + +#define QSPI_PhaseMode_None 0 // there is no this phase +#define QSPI_PhaseMode_1bit 1 // ߴ +#define QSPI_PhaseMode_2bit 2 // ˫ߴ +#define QSPI_PhaseMode_4bit 3 // ߴ + +#define QSPI_PhaseSize_8bit 0 +#define QSPI_PhaseSize_16bit 1 +#define QSPI_PhaseSize_24bit 2 +#define QSPI_PhaseSize_32bit 3 + + +#define QSPI_Mode_IndirectWrite 0 +#define QSPI_Mode_IndirectRead 1 +#define QSPI_Mode_AutoPolling 2 + + +#define QSPI_CMD_READ_JEDEC 0x9F +#define QSPI_CMD_FAST_READ 0x0B +#define QSPI_CMD_FAST_READ_2bit 0x3B +#define QSPI_CMD_FAST_READ_IO2bit 0xBB +#define QSPI_CMD_FAST_READ_4bit 0x6B +#define QSPI_CMD_FAST_READ_IO4bit 0xEB +#define QSPI_CMD_WRITE_ENABLE 0x06 +#define QSPI_CMD_WRITE_DISABLE 0x04 +#define QSPI_CMD_PAGE_PROGRAM 0x02 +#define QSPI_CMD_PAGE_PROGRAM_4bit 0x32 +#define QSPI_CMD_ERASE_CHIP 0x60 +#define QSPI_CMD_ERASE_SECTOR 0x20 +#define QSPI_CMD_ERASE_BLOCK32KB 0x52 +#define QSPI_CMD_ERASE_BLOCK64KB 0xD8 +#define QSPI_CMD_READ_STATUS_REG1 0x05 +#define QSPI_CMD_READ_STATUS_REG2 0x35 +#define QSPI_CMD_READ_STATUS_REG3 0x15 +#define QSPI_CMD_WRITE_STATUS_REG1 0x01 +#define QSPI_CMD_WRITE_STATUS_REG2 0x31 +#define QSPI_CMD_WRITE_STATUS_REG3 0x11 +#define QSPI_CMD_WRITE_EXT_ADDR 0xC5 // Write Extended Address Register +#define QSPI_CMD_READ_EXT_ADDR 0xC8 +#define QSPI_CMD_4BYTE_ADDR_ENTER 0xB7 +#define QSPI_CMD_4BYTE_ADDR_EXIT 0xE9 + +/* Command with 4-byte address */ +#define QSPI_C4B_FAST_READ 0x0C +#define QSPI_C4B_FAST_READ_2bit 0x3C +#define QSPI_C4B_FAST_READ_IO2bit 0xBC +#define QSPI_C4B_FAST_READ_4bit 0x6C +#define QSPI_C4B_FAST_READ_IO4bit 0xEC +#define QSPI_C4B_PAGE_PROGRAM 0x12 +#define QSPI_C4B_PAGE_PROGRAM_4bit 0x34 +#define QSPI_C4B_ERASE_SECTOR 0x21 +#define QSPI_C4B_ERASE_BLOCK64KB 0xDC + + +#define QSPI_STATUS_REG1_BUSY_Pos 0 +#define QSPI_STATUS_REG2_QUAD_Pos 1 +#define QSPI_STATUS_REG3_ADS_Pos 0 // Current Address Mode, Status Only +#define QSPI_STATUS_REG3_ADP_Pos 1 // PowerUp Address Mode, Non-Volatile Writable + + +/* Interrupt Type */ +#define QSPI_IT_ERR (1 << QSPI_CR_ERR_Pos) +#define QSPI_IT_DONE (1 << QSPI_CR_DONE_Pos) +#define QSPI_IT_FFTHR (1 << QSPI_CR_FFTHR_Pos) +#define QSPI_IT_PSMAT (1 << QSPI_CR_PSMAT_Pos) +#define QSPI_IT_TO (1 << QSPI_CR_TOIE_Pos) + + + +void QSPI_Init(QSPI_TypeDef * QSPIx, QSPI_InitStructure * initStruct); +void QSPI_Open(QSPI_TypeDef * QSPIx); +void QSPI_Close(QSPI_TypeDef * QSPIx); + +void QSPI_CmdStructClear(QSPI_CmdStructure * cmdStruct); +void QSPI_Command(QSPI_TypeDef * QSPIx, uint8_t cmdMode, QSPI_CmdStructure * cmdStruct); + +void QSPI_Erase_(QSPI_TypeDef * QSPIx, uint32_t addr, uint16_t block_size, uint8_t wait); +#define QSPI_Erase(QSPIx, addr, wait) QSPI_Erase_(QSPIx, (addr), 4, (wait)); +#define QSPI_Erase_Block64KB(QSPIx, addr, wait) QSPI_Erase_(QSPIx, (addr), 64, (wait)); + +void QSPI_Write_(QSPI_TypeDef * QSPIx, uint32_t addr, uint8_t buff[], uint32_t count, uint8_t data_width, uint8_t data_phase); +#define QSPI_Write(QSPIx, addr, buff, count) QSPI_Write_(QSPIx, (addr), (buff), (count), 1, 1) +#define QSPI_Write_4bit(QSPIx, addr, buff, count) QSPI_Write_(QSPIx, (addr), (buff), (count), 4, 1) + +void QSPI_Read_(QSPI_TypeDef * QSPIx, uint32_t addr, uint8_t buff[], uint32_t count, uint8_t addr_width, uint8_t data_width, uint8_t data_phase); +#define QSPI_Read(QSPIx, addr, buff, count) QSPI_Read_(QSPIx, (addr), (buff), (count), 1, 1, 1) +#define QSPI_Read_2bit(QSPIx, addr, buff, count) QSPI_Read_(QSPIx, (addr), (buff), (count), 1, 2, 1) +#define QSPI_Read_4bit(QSPIx, addr, buff, count) QSPI_Read_(QSPIx, (addr), (buff), (count), 1, 4, 1) +#define QSPI_Read_IO2bit(QSPIx, addr, buff, count) QSPI_Read_(QSPIx, (addr), (buff), (count), 2, 2, 1) +#define QSPI_Read_IO4bit(QSPIx, addr, buff, count) QSPI_Read_(QSPIx, (addr), (buff), (count), 4, 4, 1) + + +bool QSPI_FlashBusy(QSPI_TypeDef * QSPIx); +uint8_t QSPI_QuadState(QSPI_TypeDef * QSPIx); +void QSPI_QuadSwitch(QSPI_TypeDef * QSPIx, uint8_t on); + +uint32_t QSPI_ReadReg(QSPI_TypeDef * QSPIx, uint8_t cmd, uint8_t n_bytes); +void QSPI_WriteReg(QSPI_TypeDef * QSPIx, uint8_t cmd, uint32_t data, uint8_t n_bytes); + +#define QSPI_ReadJEDEC(QSPIx) QSPI_ReadReg(QSPIx, QSPI_CMD_READ_JEDEC, 3) +#define QSPI_WriteEnable(QSPIx) QSPI_WriteReg(QSPIx, QSPI_CMD_WRITE_ENABLE, 0, 0) +#define QSPI_WriteDisable(QSPIx) QSPI_WriteReg(QSPIx, QSPI_CMD_WRITE_DISABLE, 0, 0) +#define QSPI_4ByteAddrEnable(QSPIx) QSPI_WriteReg(QSPIx, QSPI_CMD_4BYTE_ADDR_ENTER, 0, 0) +#define QSPI_4ByteAddrDisable(QSPIx) QSPI_WriteReg(QSPIx, QSPI_CMD_4BYTE_ADDR_EXIT, 0, 0) + + +static inline bool QSPI_Busy(QSPI_TypeDef * QSPIx) +{ + return QSPIx->SR & QSPI_SR_BUSY_Msk; +} + +static inline void QSPI_Abort(QSPI_TypeDef * QSPIx) +{ + QSPIx->CR |= QSPI_CR_ABORT_Msk; +} + +static inline uint32_t QSPI_FIFOCount(QSPI_TypeDef * QSPIx) +{ + return (QSPIx->SR & QSPI_SR_FFLVL_Msk) >> QSPI_SR_FFLVL_Pos; +} + +static inline uint32_t QSPI_FIFOSpace(QSPI_TypeDef * QSPIx) +{ + return 16 - QSPI_FIFOCount(QSPIx); +} + +static inline bool QSPI_FIFOEmpty(QSPI_TypeDef * QSPIx) +{ + return QSPI_FIFOCount(QSPIx) == 0; +} + +static inline void QSPI_DMAEnable(QSPI_TypeDef * QSPIx, uint32_t mode) +{ + /* ȷĶдģʽȻλ QSPI->CR.DMAEN CCR.MODE ʱд CCR.CODE */ + *((uint8_t *)((uint32_t)&QSPIx->CCR + 3)) = (mode << (QSPI_CCR_MODE_Pos - 24)); + + QSPIx->CR |= QSPI_CR_DMAEN_Msk; +} + +static inline void QSPI_DMADisable(QSPI_TypeDef * QSPIx) +{ + QSPIx->CR &= ~QSPI_CR_DMAEN_Msk; +} + +void QSPI_INTEn(QSPI_TypeDef * QSPIx, uint32_t it); +void QSPI_INTDis(QSPI_TypeDef * QSPIx, uint32_t it); +void QSPI_INTClr(QSPI_TypeDef * QSPIx, uint32_t it); +uint32_t QSPI_INTStat(QSPI_TypeDef * QSPIx, uint32_t it); + + + +/******** QSPI use as normal SPI (half-duplex) ********/ + +void QSPI_SPI_Write_(QSPI_TypeDef * QSPIx, uint8_t buff[], uint32_t count, uint8_t data_width, uint8_t data_phase); +#define QSPI_SPI_Write(QSPIx, buff, count) QSPI_SPI_Write_(QSPIx, (buff), (count), 1, 1) +#define QSPI_SPI_Write_2bit(QSPIx, buff, count) QSPI_SPI_Write_(QSPIx, (buff), (count), 2, 1) +#define QSPI_SPI_Write_4bit(QSPIx, buff, count) QSPI_SPI_Write_(QSPIx, (buff), (count), 4, 1) + +void QSPI_SPI_Read_(QSPI_TypeDef * QSPIx, uint8_t buff[], uint32_t count, uint8_t data_width, uint8_t data_phase); +#define QSPI_SPI_Read(QSPIx, buff, count) QSPI_SPI_Read_(QSPIx, (buff), (count), 1, 1) +#define QSPI_SPI_Read_2bit(QSPIx, buff, count) QSPI_SPI_Read_(QSPIx, (buff), (count), 2, 1) +#define QSPI_SPI_Read_4bit(QSPIx, buff, count) QSPI_SPI_Read_(QSPIx, (buff), (count), 4, 1) + + +#endif //__SWM221_QSPI_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_spi.c b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_spi.c new file mode 100644 index 0000000..1a956d6 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_spi.c @@ -0,0 +1,267 @@ +/****************************************************************************************************************************************** +* ļ: SWM221_spi.c +* ˵: SWM221ƬSPI +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.0.0 2016130 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM221.h" +#include "SWM221_spi.h" + + +/****************************************************************************************************************************************** +* : SPI_Init() +* ˵: SPIͬнӿڳʼ֡趨ʱ趨ٶ趨ж趨FIFO趨 +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0 +* SPI_InitStructure * initStruct SPI趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void SPI_Init(SPI_TypeDef * SPIx, SPI_InitStructure * initStruct) +{ + uint32_t fast = 0, no_sync = 0; + + switch((uint32_t)SPIx) + { + case ((uint32_t)SPI0): + SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_SPI0_Pos); + break; + } + + SPI_Close(SPIx); //һЩؼĴֻSPIرʱ + + if(initStruct->clkDiv == SPI_CLKDIV_2) + { + fast = 1; + no_sync = 1; + } + else if(initStruct->clkDiv == SPI_CLKDIV_4) + { + no_sync = 1; + } + + SPIx->CTRL &= ~(SPI_CTRL_FFS_Msk | SPI_CTRL_CPHA_Msk | SPI_CTRL_CPOL_Msk | SPI_CTRL_SIZE_Msk | SPI_CTRL_MSTR_Msk | + SPI_CTRL_CLKDIV_Msk | SPI_CTRL_SSN_H_Msk | SPI_CTRL_RFTHR_Msk | SPI_CTRL_TFTHR_Msk); + SPIx->CTRL |= (initStruct->FrameFormat << SPI_CTRL_FFS_Pos) | + (initStruct->SampleEdge << SPI_CTRL_CPHA_Pos) | + (initStruct->IdleLevel << SPI_CTRL_CPOL_Pos) | + ((initStruct->WordSize-1) << SPI_CTRL_SIZE_Pos) | + (initStruct->Master << SPI_CTRL_MSTR_Pos) | + (fast << SPI_CTRL_FAST_Pos) | + (no_sync << SPI_CTRL_NSYNC_Pos) | + ((initStruct->clkDiv & 7) << SPI_CTRL_CLKDIV_Pos) | + (0 << SPI_CTRL_SSN_H_Pos) | + ((initStruct->RXThreshold > 0 ? initStruct->RXThreshold-1 : 0) << SPI_CTRL_RFTHR_Pos) | + (initStruct->TXThreshold << SPI_CTRL_TFTHR_Pos) | + (1 << SPI_CTRL_RFCLR_Pos) | + (1 << SPI_CTRL_TFCLR_Pos); + SPIx->CTRL &= ~(SPI_CTRL_RFCLR_Msk | SPI_CTRL_TFCLR_Msk); + + SPIx->IF = 0x37F; //жϱ־ + SPIx->IE = 0x000; + SPIx->IE |= (initStruct->RXThresholdIEn << SPI_IE_RFTHR_Pos) | + (initStruct->TXThresholdIEn << SPI_IE_TFTHR_Pos) | + (initStruct->TXCompleteIEn << SPI_IE_FTC_Pos); + + switch((uint32_t)SPIx) + { + case ((uint32_t)SPI0): + if(initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TXCompleteIEn) + { + NVIC_EnableIRQ(GPIOB3_GPIOA11_SPI0_IRQn); + } + else + { + NVIC_DisableIRQ(GPIOB3_GPIOA11_SPI0_IRQn); + } + break; + } +} + +/****************************************************************************************************************************************** +* : SPI_Open() +* ˵: SPI򿪣շ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_Open(SPI_TypeDef * SPIx) +{ + SPIx->CTRL |= (0x01 << SPI_CTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* : SPI_Close() +* ˵: SPIرգֹշ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_Close(SPI_TypeDef * SPIx) +{ + SPIx->CTRL &= ~SPI_CTRL_EN_Msk; +} + +/****************************************************************************************************************************************** +* : SPI_Read() +* ˵: ȡһ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0 +* : uint32_t ȡ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_Read(SPI_TypeDef * SPIx) +{ + return SPIx->DATA; +} + +/****************************************************************************************************************************************** +* : SPI_Write() +* ˵: дһ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0 +* uint32_t Ҫд +* : +* ע: +******************************************************************************************************************************************/ +void SPI_Write(SPI_TypeDef * SPIx, uint32_t data) +{ + SPIx->DATA = data; +} + +/****************************************************************************************************************************************** +* : SPI_WriteWithWait() +* ˵: дһݲȴȫͳȥ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0 +* uint32_t Ҫд +* : +* ע: +******************************************************************************************************************************************/ +void SPI_WriteWithWait(SPI_TypeDef * SPIx, uint32_t data) +{ + SPIx->STAT |= (1 << SPI_STAT_WTC_Pos); + + SPIx->DATA = data; + + while((SPIx->STAT & SPI_STAT_WTC_Msk) == 0); +} + +/****************************************************************************************************************************************** +* : SPI_ReadWrite() +* ˵: һݣط͹нյ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0 +* uint32_t data Ҫ͵ +* : uint32_t յ +* ע: ͬһSPIģ飬˺ӦSPI_Write()ãΪSPI_Write()SPI_STAT_RFNE״̬ +******************************************************************************************************************************************/ +uint32_t SPI_ReadWrite(SPI_TypeDef * SPIx, uint32_t data) +{ + SPIx->DATA = data; + while(!(SPIx->STAT & SPI_STAT_RFNE_Msk)); + + return SPIx->DATA; +} + +/****************************************************************************************************************************************** +* : SPI_IsRXEmpty() +* ˵: FIFOǷգԼSPI_Read() +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0 +* : uint32_t 1 FIFO 0 FIFOǿ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_IsRXEmpty(SPI_TypeDef * SPIx) +{ + return (SPIx->STAT & SPI_STAT_RFNE_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* : SPI_IsTXFull() +* ˵: FIFOǷԼSPI_Write() +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0 +* : uint32_t 1 FIFO 0 FIFO +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_IsTXFull(SPI_TypeDef * SPIx) +{ + return (SPIx->STAT & SPI_STAT_TFNF_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* : SPI_IsTXEmpty() +* ˵: FIFOǷ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0 +* : uint32_t 1 FIFO 0 FIFOǿ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_IsTXEmpty(SPI_TypeDef * SPIx) +{ + return (SPIx->STAT & SPI_STAT_TFE_Msk) ? 1 : 0; +} + + +/****************************************************************************************************************************************** +* : SPI_INTEn() +* ˵: жʹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0 +* uint32_t it interrupt typeЧֵSPI_IT_RX_OVFSPI_IT_RX_FULLSPI_IT_RX_HFULLSPI_IT_TX_EMPTYSPI_IT_TX_HFULL +* SPI_IT_RX_THRESSPI_IT_TX_THRESSPI_IT_TX_DONESPI_IT_CS_FALLSPI_IT_CS_RISE 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTEn(SPI_TypeDef * SPIx, uint32_t it) +{ + SPIx->IE |= it; +} + +/****************************************************************************************************************************************** +* : SPI_INTDis() +* ˵: жϽֹ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0 +* uint32_t it interrupt typeЧֵSPI_IT_RX_OVFSPI_IT_RX_FULLSPI_IT_RX_HFULLSPI_IT_TX_EMPTYSPI_IT_TX_HFULL +* SPI_IT_RX_THRESSPI_IT_TX_THRESSPI_IT_TX_DONESPI_IT_CS_FALLSPI_IT_CS_RISE 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTDis(SPI_TypeDef * SPIx, uint32_t it) +{ + SPIx->IE &= ~it; +} + +/****************************************************************************************************************************************** +* : SPI_INTClr() +* ˵: жϱ־ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0 +* uint32_t it interrupt typeЧֵSPI_IT_RX_OVFSPI_IT_RX_FULLSPI_IT_RX_HFULLSPI_IT_TX_EMPTYSPI_IT_TX_HFULL +* SPI_IT_RX_THRESSPI_IT_TX_THRESSPI_IT_TX_DONESPI_IT_CS_FALLSPI_IT_CS_RISE 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void SPI_INTClr(SPI_TypeDef * SPIx, uint32_t it) +{ + SPIx->IF = it; +} + +/****************************************************************************************************************************************** +* : SPI_INTStat() +* ˵: ж״̬ѯ +* : SPI_TypeDef * SPIx ָҪõSPIЧֵSPI0 +* uint32_t it interrupt typeЧֵSPI_IT_RX_OVFSPI_IT_RX_FULLSPI_IT_RX_HFULLSPI_IT_TX_EMPTYSPI_IT_TX_HFULL +* SPI_IT_RX_THRESSPI_IT_TX_THRESSPI_IT_TX_DONESPI_IT_CS_FALLSPI_IT_CS_RISE 䡰 +* : uint32_t 1 жϷ 0 жδ +* ע: +******************************************************************************************************************************************/ +uint32_t SPI_INTStat(SPI_TypeDef * SPIx, uint32_t it) +{ + return (SPIx->IF & it) ? 1 : 0; +} diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_spi.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_spi.h new file mode 100644 index 0000000..384cd97 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_spi.h @@ -0,0 +1,112 @@ +#ifndef __SWM221_SPI_H__ +#define __SWM221_SPI_H__ + +typedef struct { + uint8_t FrameFormat; //֡ʽSPI_FORMAT_SPISPI_FORMAT_TI_SSI + uint8_t SampleEdge; //SPI֡ʽ£ѡݲأSPI_FIRST_EDGESPI_SECOND_EDGE + uint8_t IdleLevel; //SPI֡ʽ£ѡʱݴʱʱߵĵƽSPI_LOW_LEVELSPI_HIGH_LEVEL + uint8_t WordSize; //ֳ, Чֵ4-16 + uint8_t Master; //1 ģʽ 0 ӻģʽ + uint8_t clkDiv; //SPI_CLK = SYS_CLK / clkDivЧֵSPI_CLKDIV_2SPI_CLKDIV_4... ... SPI_CLKDIV_512 + + uint8_t RXThreshold; //ȡֵ1--8 + uint8_t RXThresholdIEn;//RX FIFOݸ >= RXThresholdʱж + + uint8_t TXThreshold; //ȡֵ0--7 + uint8_t TXThresholdIEn;//TX FIFOݸ <= TXThresholdʱж + + uint8_t TXCompleteIEn; //FIFOҷλĴжʹ +} SPI_InitStructure; + +#define SPI_FORMAT_SPI 0 //Motorola SPI ʽ +#define SPI_FORMAT_TI_SSI 1 //TI SSI ʽ + +#define SPI_FIRST_EDGE 0 //һʱؿʼ +#define SPI_SECOND_EDGE 1 //ڶʱؿʼ + +#define SPI_LOW_LEVEL 0 //ʱʱֵ߱͵ƽ +#define SPI_HIGH_LEVEL 1 //ʱʱָ߱ߵƽ + +#define SPI_CLKDIV_2 8 +#define SPI_CLKDIV_4 0 +#define SPI_CLKDIV_8 1 +#define SPI_CLKDIV_16 2 +#define SPI_CLKDIV_32 3 +#define SPI_CLKDIV_64 4 +#define SPI_CLKDIV_128 5 +#define SPI_CLKDIV_256 6 +#define SPI_CLKDIV_512 7 + + +/* Interrupt Type */ +#define SPI_IT_RX_OVF (1 << 0) //RX FIFO Overflow +#define SPI_IT_RX_FULL (1 << 1) //RX FIFO Full +#define SPI_IT_RX_HFULL (1 << 2) //RX FIFO Half Full +#define SPI_IT_TX_EMPTY (1 << 3) //TX FIFO Empty +#define SPI_IT_TX_HFULL (1 << 4) //TX FIFO Half Full +#define SPI_IT_RX_THRES (1 << 5) //RX FIFO ThresholdFIFOݸCTRL.RFTHR趨ֵ +#define SPI_IT_TX_THRES (1 << 6) //TX FIFO ThresholdFIFOݸСCTRL.TFTHR趨ֵ +#define SPI_IT_TX_DONE (1 << 9) //TX DoneFIFOҷλĴգ +#define SPI_IT_CS_FALL (1 << 10) //ӻģʽ£CS½ж +#define SPI_IT_CS_RISE (1 << 11) //ӻģʽ£CSж + + +void SPI_Init(SPI_TypeDef * SPIx, SPI_InitStructure * initStruct); //SPIʼ +void SPI_Open(SPI_TypeDef * SPIx); //SPI򿪣շ +void SPI_Close(SPI_TypeDef * SPIx); //SPIرգֹշ + +uint32_t SPI_Read(SPI_TypeDef * SPIx); +void SPI_Write(SPI_TypeDef * SPIx, uint32_t data); +void SPI_WriteWithWait(SPI_TypeDef * SPIx, uint32_t data); +uint32_t SPI_ReadWrite(SPI_TypeDef * SPIx, uint32_t data); + +uint32_t SPI_IsRXEmpty(SPI_TypeDef * SPIx); //FIFOǷգԼSPI_Read() +uint32_t SPI_IsTXFull(SPI_TypeDef * SPIx); //FIFOǷԼSPI_Write() +uint32_t SPI_IsTXEmpty(SPI_TypeDef * SPIx); //FIFOǷ + + +void SPI_INTEn(SPI_TypeDef * SPIx, uint32_t it); //жʹ +void SPI_INTDis(SPI_TypeDef * SPIx, uint32_t it); //жϽֹ +void SPI_INTClr(SPI_TypeDef * SPIx, uint32_t it); //жϱ־ +uint32_t SPI_INTStat(SPI_TypeDef * SPIx, uint32_t it); //ж״̬ѯ + + + +typedef struct { + uint8_t Mode; //I2S_MASTER_TXI2S_MASTER_RXI2S_MASTER_TX_RXI2S_SLAVE_TXI2S_SLAVE_RXI2S_SLAVE_TX_RX + uint8_t FrameFormat; //I2S_I2S_PHILIPSI2S_MSB_JUSTIFIEDI2S_PCM_SHORTI2S_PCM_LONG0I2S_PCM_LONG1 + uint8_t DataLen; //I2S_DATALEN_8I2S_DATALEN_16I2S_DATALEN_24I2S_DATALEN_32 + uint32_t ClkFreq; //I2S_SCLK Frequency + + uint8_t RXThreshold; //ȡֵ1--8 + uint8_t RXThresholdIEn;//RX FIFOݸ >= RXThresholdʱж + + uint8_t TXThreshold; //ȡֵ0--7 + uint8_t TXThresholdIEn;//TX FIFOݸ <= TXThresholdʱж + + uint8_t TXCompleteIEn; //FIFOҷλĴжʹ +} I2S_InitStructure; + +#define I2S_MASTER_RX 5 +#define I2S_MASTER_TX 6 +#define I2S_SLAVE_RX 1 +#define I2S_SLAVE_TX 2 + +#define I2S_I2S_PHILIPS 0 +#define I2S_MSB_JUSTIFIED 1 +#define I2S_PCM_SHORT 2 +#define I2S_PCM_LONG0 3 //PCM Long Mode Sync Width 1 SCLK period +#define I2S_PCM_LONG1 4 //PCM Long Mode Sync Width 1 Data Length + +#define I2S_DATALEN_8 0 +#define I2S_DATALEN_16 1 +#define I2S_DATALEN_24 2 +#define I2S_DATALEN_32 3 + +void I2S_Init(SPI_TypeDef * SPIx, I2S_InitStructure * initStruct); //I2Sʼ +void I2S_Open(SPI_TypeDef * SPIx); //I2S򿪣շ +void I2S_Close(SPI_TypeDef * SPIx); //I2Sرգֹշ +void I2S_MCLKConfig(SPI_TypeDef * SPIx, uint32_t output_enable, uint32_t mclk_freq); + + +#endif //__SWM221_SPI_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_timr.c b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_timr.c new file mode 100644 index 0000000..ef20f93 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_timr.c @@ -0,0 +1,564 @@ +/****************************************************************************************************************************************** +* ļ: SWM221_timr.c +* ˵: SWM221Ƭļ/ʱ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.0.0 2016130 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM221.h" +#include "SWM221_timr.h" + + +/****************************************************************************************************************************************** +* : TIMR_Init() +* ˵: TIMRʱ/ʼ +* : TIMR_TypeDef * TIMRx ָҪõĶʱЧֵTIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3 +* uint32_t mode TIMR0~3: TIMR_MODE_TIMERTIMR_MODE_COUNTERTIMR_MODE_OCTIMR_MODE_IC +* BTIMR0~3: TIMR_MODE_TIMERTIMR_MODE_OC +* uint32_t prediv ԤƵȡֵ1-256 +* uint32_t period ʱ/ڣȡֵ1-16777216 +* uint32_t int_en жʹ +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_Init(TIMR_TypeDef * TIMRx, uint32_t mode, uint32_t prediv, uint32_t period, uint32_t int_en) +{ + if((TIMRx == TIMR0) || (TIMRx == TIMR1) || (TIMRx == TIMR2)) + { + SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_TIMR_Pos); + } + else if((TIMRx == BTIMR0) || (TIMRx == BTIMR1) || (TIMRx == BTIMR2) || (TIMRx == BTIMR3)) + { + SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_BTIMR_Pos); + } + + TIMR_Stop(TIMRx); //һЩؼĴֻڶʱֹͣʱ + + TIMRx->CR &= ~(TIMR_CR_MODE_Msk | TIMR_CR_CLKSRC_Msk); + TIMRx->CR |= (mode << TIMR_CR_CLKSRC_Pos); + + TIMRx->PREDIV = prediv - 1; + + TIMRx->LOAD = period - 1; + + TIMRx->IF = (1 << TIMR_IF_TO_Pos); //жϱ־ + if(int_en) TIMRx->IE |= (1 << TIMR_IE_TO_Pos); + else TIMRx->IE &= ~(1 << TIMR_IE_TO_Pos); + + switch((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + if(int_en) NVIC_EnableIRQ(TIMR0_IRQn); + break; + + case ((uint32_t)TIMR1): + if(int_en) NVIC_EnableIRQ(TIMR1_IRQn); + break; + + case ((uint32_t)TIMR2): + if(int_en) NVIC_EnableIRQ(GPIOB0_GPIOA8_TIMR2_IRQn); + break; + + case ((uint32_t)BTIMR0): + if(int_en) NVIC_EnableIRQ(BTIMR0_IRQn); + break; + + case ((uint32_t)BTIMR1): + if(int_en) NVIC_EnableIRQ(BTIMR1_IRQn); + break; + + case ((uint32_t)BTIMR2): + if(int_en) NVIC_EnableIRQ(BTIMR2_IRQn); + break; + + case ((uint32_t)BTIMR3): + if(int_en) NVIC_EnableIRQ(BTIMR3_IRQn); + break; + } +} + +/****************************************************************************************************************************************** +* : TIMR_Start() +* ˵: ʱӳʼֵʼʱ/ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_Start(TIMR_TypeDef * TIMRx) +{ + switch((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + TIMRG->EN |= (1 << TIMRG_EN_TIMR0_Pos); + break; + + case ((uint32_t)TIMR1): + TIMRG->EN |= (1 << TIMRG_EN_TIMR1_Pos); + break; + + case ((uint32_t)TIMR2): + TIMRG->EN |= (1 << TIMRG_EN_TIMR2_Pos); + break; + + case ((uint32_t)BTIMR0): + BTIMRG->EN |= (1 << TIMRG_EN_TIMR0_Pos); + break; + + case ((uint32_t)BTIMR1): + BTIMRG->EN |= (1 << TIMRG_EN_TIMR1_Pos); + break; + + case ((uint32_t)BTIMR2): + BTIMRG->EN |= (1 << TIMRG_EN_TIMR2_Pos); + break; + + case ((uint32_t)BTIMR3): + BTIMRG->EN |= (1 << TIMRG_EN_TIMR3_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* : TIMR_Stop() +* ˵: ֹͣʱ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_Stop(TIMR_TypeDef * TIMRx) +{ + switch((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + TIMRG->EN &= ~(1 << TIMRG_EN_TIMR0_Pos); + break; + + case ((uint32_t)TIMR1): + TIMRG->EN &= ~(1 << TIMRG_EN_TIMR1_Pos); + break; + + case ((uint32_t)TIMR2): + TIMRG->EN &= ~(1 << TIMRG_EN_TIMR2_Pos); + break; + + case ((uint32_t)BTIMR0): + BTIMRG->EN &= ~(1 << TIMRG_EN_TIMR0_Pos); + break; + + case ((uint32_t)BTIMR1): + BTIMRG->EN &= ~(1 << TIMRG_EN_TIMR1_Pos); + break; + + case ((uint32_t)BTIMR2): + BTIMRG->EN &= ~(1 << TIMRG_EN_TIMR2_Pos); + break; + + case ((uint32_t)BTIMR3): + BTIMRG->EN &= ~(1 << TIMRG_EN_TIMR3_Pos); + break; + } +} + +/****************************************************************************************************************************************** +* : TIMR_Halt() +* ˵: ͣʱֲֵ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_Halt(TIMR_TypeDef * TIMRx) +{ + TIMRx->HALT = 1; +} + +/****************************************************************************************************************************************** +* : TIMR_Resume() +* ˵: ָʱͣ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_Resume(TIMR_TypeDef * TIMRx) +{ + TIMRx->HALT = 0; +} + +/****************************************************************************************************************************************** +* : TIMR_GetCurValue() +* ˵: ȡǰֵ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3 +* : uint32_t ǰֵ +* ע: +******************************************************************************************************************************************/ +uint32_t TIMR_GetCurValue(TIMR_TypeDef * TIMRx) +{ + return TIMRx->VALUE; +} + +/****************************************************************************************************************************************** +* : TIMR_INTEn() +* ˵: ʹж +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_INTEn(TIMR_TypeDef * TIMRx) +{ + TIMRx->IE |= (1 << TIMR_IE_TO_Pos); +} + +/****************************************************************************************************************************************** +* : TIMR_INTDis() +* ˵: ж +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_INTDis(TIMR_TypeDef * TIMRx) +{ + TIMRx->IE &= ~(1 << TIMR_IE_TO_Pos); +} + +/****************************************************************************************************************************************** +* : TIMR_INTClr() +* ˵: жϱ־ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_INTClr(TIMR_TypeDef * TIMRx) +{ + TIMRx->IF = (1 << TIMR_IF_TO_Pos); +} + +/****************************************************************************************************************************************** +* : TIMR_INTStat() +* ˵: ȡж״̬ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3 +* : uint32_t 0 TIMRxδж 1 TIMRxж +* ע: +******************************************************************************************************************************************/ +uint32_t TIMR_INTStat(TIMR_TypeDef * TIMRx) +{ + return (TIMRx->IF & TIMR_IF_TO_Msk) ? 1 : 0; +} + + +/****************************************************************************************************************************************** +* : TIMR_OC_Init() +* ˵: ȽϹܳʼ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3 +* uint32_t match ֵݼmatchʱƽת +* uint32_t match_int_en ֵݼmatchʱǷж +* uint32_t init_lvl ʼƽTimerֹͣʱģʽǡȽϡʱƽ +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_OC_Init(TIMR_TypeDef * TIMRx, uint32_t match, uint32_t match_int_en, uint32_t init_lvl) +{ + TIMRx->OCMAT = match; + if(init_lvl) TIMRx->OCCR |= (1 << TIMR_OCCR_INITLVL_Pos); + else TIMRx->OCCR &= ~(1 << TIMR_OCCR_INITLVL_Pos); + + TIMRx->IF = (1 << TIMR_IF_OC0_Pos); //жϱ־ + if(match_int_en) TIMRx->IE |= (1 << TIMR_IE_OC0_Pos); + else TIMRx->IE &= ~(1 << TIMR_IE_OC0_Pos); + + switch((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + if(match_int_en) NVIC_EnableIRQ(TIMR0_IRQn); + break; + + case ((uint32_t)TIMR1): + if(match_int_en) NVIC_EnableIRQ(TIMR1_IRQn); + break; + + case ((uint32_t)TIMR2): + if(match_int_en) NVIC_EnableIRQ(GPIOB0_GPIOA8_TIMR2_IRQn); + break; + + case ((uint32_t)BTIMR0): + if(match_int_en) NVIC_EnableIRQ(BTIMR0_IRQn); + break; + + case ((uint32_t)BTIMR1): + if(match_int_en) NVIC_EnableIRQ(BTIMR1_IRQn); + break; + + case ((uint32_t)BTIMR2): + if(match_int_en) NVIC_EnableIRQ(BTIMR2_IRQn); + break; + + case ((uint32_t)BTIMR3): + if(match_int_en) NVIC_EnableIRQ(BTIMR3_IRQn); + break; + } +} + +/****************************************************************************************************************************************** +* : TIMR_OC_OutputEn() +* ˵: ʹȽϹܵIJ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_OC_OutputEn(TIMR_TypeDef * TIMRx) +{ + TIMRx->OCCR &= ~(TIMR_OCCR_FORCEEN_Pos); +} + +/****************************************************************************************************************************************** +* : TIMR_OC_OutputDis() +* ˵: ֹȽϹܵIJȽϹűlevelƽ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3 +* uint32_t level ֹκϱֵĵƽ +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_OC_OutputDis(TIMR_TypeDef * TIMRx, uint32_t level) +{ + if(level) TIMRx->OCCR |= (1 << TIMR_OCCR_FORCELVL_Pos); + else TIMRx->OCCR &= ~(1 << TIMR_OCCR_FORCELVL_Pos); + + TIMRx->OCCR |= (TIMR_OCCR_FORCEEN_Pos); +} + +/****************************************************************************************************************************************** +* : TIMR_OC_SetMatch() +* ˵: ȽϹܵıȽֵ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3 +* uint32_t match ȽϹܵıȽֵ +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_OC_SetMatch(TIMR_TypeDef * TIMRx, uint32_t match) +{ + TIMRx->OCMAT = match; +} + +/****************************************************************************************************************************************** +* : TIMR_OC_GetMatch() +* ˵: ȡȽϹܵıȽֵ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3 +* : uint32_t ȽϹܵıȽֵ +* ע: +******************************************************************************************************************************************/ +uint32_t TIMR_OC_GetMatch(TIMR_TypeDef * TIMRx) +{ + return TIMRx->OCMAT; +} + +/****************************************************************************************************************************************** +* : TIMR_OC_INTEn() +* ˵: ʹȽж +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_OC_INTEn(TIMR_TypeDef * TIMRx) +{ + TIMRx->IE |= (1 << TIMR_IE_OC0_Pos); +} + +/****************************************************************************************************************************************** +* : TIMR_OC_INTDis() +* ˵: Ƚж +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_OC_INTDis(TIMR_TypeDef * TIMRx) +{ + TIMRx->IE &= ~(1 << TIMR_IE_OC0_Pos); +} + +/****************************************************************************************************************************************** +* : TIMR_OC_INTClr() +* ˵: Ƚжϱ־ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_OC_INTClr(TIMR_TypeDef * TIMRx) +{ + TIMRx->IF = (1 << TIMR_IF_OC0_Pos); +} + +/****************************************************************************************************************************************** +* : TIMR_OC_INTStat() +* ˵: ȡȽж״̬ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2BTIMR0BTIMR1BTIMR2BTIMR3 +* : uint32_t 0 Ƚmatchδ 1 Ƚmatch +* ע: +******************************************************************************************************************************************/ +uint32_t TIMR_OC_INTStat(TIMR_TypeDef * TIMRx) +{ + return (TIMRx->IF & TIMR_IF_OC0_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : TIMR_IC_Init() +* ˵: 벶ܳʼ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2 +* uint32_t captureH_int_en ߵƽжʹ +* uint32_t captureL_int_en ͵ƽжʹ +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_IC_Init(TIMR_TypeDef * TIMRx, uint32_t captureH_int_en, uint32_t captureL_int_en) +{ + TIMRx->IF = (TIMR_IF_ICR_Msk | TIMR_IF_ICF_Msk); + if(captureH_int_en) TIMRx->IE |= (1 << TIMR_IE_ICF_Pos); + else TIMRx->IE &= ~(1 << TIMR_IE_ICF_Pos); + if(captureL_int_en) TIMRx->IE |= (1 << TIMR_IE_ICR_Pos); + else TIMRx->IE &= ~(1 << TIMR_IE_ICR_Pos); + + switch((uint32_t)TIMRx) + { + case ((uint32_t)TIMR0): + if(captureH_int_en | captureL_int_en) NVIC_EnableIRQ(TIMR0_IRQn); + break; + + case ((uint32_t)TIMR1): + if(captureH_int_en | captureL_int_en) NVIC_EnableIRQ(TIMR1_IRQn); + break; + + case ((uint32_t)TIMR2): + if(captureH_int_en | captureL_int_en) NVIC_EnableIRQ(GPIOB0_GPIOA8_TIMR2_IRQn); + break; + } +} + +/****************************************************************************************************************************************** +* : TIMR_IC_GetCaptureH() +* ˵: ȡߵƽȲ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2 +* : uint32_t ߵƽȲ +* ע: +******************************************************************************************************************************************/ +uint32_t TIMR_IC_GetCaptureH(TIMR_TypeDef * TIMRx) +{ + return TIMRx->ICHIGH; +} + +/****************************************************************************************************************************************** +* : TIMR_IC_GetCaptureL() +* ˵: ȡ͵ƽȲ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2 +* : uint32_t ͵ƽȲ +* ע: +******************************************************************************************************************************************/ +uint32_t TIMR_IC_GetCaptureL(TIMR_TypeDef * TIMRx) +{ + return TIMRx->ICLOW; +} + +/****************************************************************************************************************************************** +* : TIMR_IC_CaptureH_INTEn() +* ˵: ʹ벶ߵƽȲж +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_IC_CaptureH_INTEn(TIMR_TypeDef * TIMRx) +{ + TIMRx->IE |= (1 << TIMR_IE_ICF_Pos); +} + +/****************************************************************************************************************************************** +* : TIMR_IC_CaptureH_INTDis() +* ˵: 벶ߵƽȲж +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_IC_CaptureH_INTDis(TIMR_TypeDef * TIMRx) +{ + TIMRx->IE &= ~(1 << TIMR_IE_ICF_Pos); +} + +/****************************************************************************************************************************************** +* : TIMR_IC_CaptureH_INTClr() +* ˵: 벶ߵƽȲжϱ־ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_IC_CaptureH_INTClr(TIMR_TypeDef * TIMRx) +{ + TIMRx->IF = (1 << TIMR_IF_ICF_Pos); +} + +/****************************************************************************************************************************************** +* : TIMR_IC_CaptureH_INTStat() +* ˵: ȡ벶ߵƽȲж״̬ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2 +* : uint32_t 0 ߵƽȲδ 1 ߵƽȲ +* ע: +******************************************************************************************************************************************/ +uint32_t TIMR_IC_CaptureH_INTStat(TIMR_TypeDef * TIMRx) +{ + return (TIMRx->IF & TIMR_IF_ICF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : TIMR_IC_CaptureL_INTEn() +* ˵: ʹ벶͵ƽȲж +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_IC_CaptureL_INTEn(TIMR_TypeDef * TIMRx) +{ + TIMRx->IE |= (1 << TIMR_IE_ICR_Pos); +} + +/****************************************************************************************************************************************** +* : TIMR_IC_CaptureL_INTDis() +* ˵: 벶͵ƽȲж +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_IC_CaptureL_INTDis(TIMR_TypeDef * TIMRx) +{ + TIMRx->IE &= ~(1 << TIMR_IE_ICR_Pos); +} + +/****************************************************************************************************************************************** +* : TIMR_IC_CaptureL_INTClr() +* ˵: 벶͵ƽȲжϱ־ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2 +* : +* ע: +******************************************************************************************************************************************/ +void TIMR_IC_CaptureL_INTClr(TIMR_TypeDef * TIMRx) +{ + TIMRx->IF = (1 << TIMR_IF_ICR_Pos); +} + +/****************************************************************************************************************************************** +* : TIMR_IC_CaptureL_INTStat() +* ˵: ȡ벶͵ƽȲж״̬ +* : TIMR_TypeDef * TIMRx ָҪõĶʱȡֵTIMR0TIMR1TIMR2 +* : uint32_t 0 ͵ƽȲδ 1 ͵ƽȲ +* ע: +******************************************************************************************************************************************/ +uint32_t TIMR_IC_CaptureL_INTStat(TIMR_TypeDef * TIMRx) +{ + return (TIMRx->IF & TIMR_IF_ICR_Msk) ? 1 : 0; +} diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_timr.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_timr.h new file mode 100644 index 0000000..92afdad --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_timr.h @@ -0,0 +1,63 @@ +#ifndef __SWM221_TIMR_H__ +#define __SWM221_TIMR_H__ + +#define TIMR_MODE_TIMER ((0 << 2) | 0) +#define TIMR_MODE_IC ((1 << 2) | 0) //벶 +#define TIMR_MODE_OC ((2 << 2) | 0) //Ƚ +#define TIMR_MODE_COUNTER ((0 << 2) | 2) // + + +void TIMR_Init(TIMR_TypeDef * TIMRx, uint32_t mode, uint32_t prediv, uint32_t period, uint32_t int_en); //ʱ/ʼ +void TIMR_Start(TIMR_TypeDef * TIMRx); //ʱӳʼֵʼʱ/ +void TIMR_Stop(TIMR_TypeDef * TIMRx); //ֹͣʱ +void TIMR_Halt(TIMR_TypeDef * TIMRx); //ͣʱֲֵ +void TIMR_Resume(TIMR_TypeDef * TIMRx); //ָʱͣ + +uint32_t TIMR_SetPrediv(TIMR_TypeDef * TIMRx, uint32_t prediv); //ԤƵ +void TIMR_SetPeriod(TIMR_TypeDef * TIMRx, uint32_t period); //öʱ/ +uint32_t TIMR_GetPeriod(TIMR_TypeDef * TIMRx); //ȡʱ/ +uint32_t TIMR_GetCurValue(TIMR_TypeDef * TIMRx); //ȡǰֵ + +void TIMR_INTEn(TIMR_TypeDef * TIMRx); //ʹж +void TIMR_INTDis(TIMR_TypeDef * TIMRx); //ж +void TIMR_INTClr(TIMR_TypeDef * TIMRx); //жϱ־ +uint32_t TIMR_INTStat(TIMR_TypeDef * TIMRx); //ȡж״̬ + + +void TIMR_OC_Init(TIMR_TypeDef * TIMRx, uint32_t match, uint32_t match_int_en, uint32_t init_lvl); + +void TIMR_OC_OutputEn(TIMR_TypeDef * TIMRx); +void TIMR_OC_OutputDis(TIMR_TypeDef * TIMRx, uint32_t level); + +void TIMR_OC_SetMatch(TIMR_TypeDef * TIMRx, uint32_t match); +uint32_t TIMR_OC_GetMatch(TIMR_TypeDef * TIMRx); + +void TIMR_OC_INTEn(TIMR_TypeDef * TIMRx); +void TIMR_OC_INTDis(TIMR_TypeDef * TIMRx); +void TIMR_OC_INTClr(TIMR_TypeDef * TIMRx); +uint32_t TIMR_OC_INTStat(TIMR_TypeDef * TIMRx); + + +void TIMR_IC_Init(TIMR_TypeDef * TIMRx, uint32_t captureH_int_en, uint32_t captureL_int_en); +void TIMR_IC_Start(TIMR_TypeDef * TIMRx); +void TIMR_IC_Start_Multi(uint32_t timr0, uint32_t timr1, uint32_t timr2, uint32_t timr3); +void TIMR_IC_Stop(TIMR_TypeDef * TIMRx); + +uint32_t TIMR_IC_GetCaptureH(TIMR_TypeDef * TIMRx); +uint32_t TIMR_IC_GetCaptureL(TIMR_TypeDef * TIMRx); + +void TIMR_IC_CaptureH_INTEn(TIMR_TypeDef * TIMRx); +void TIMR_IC_CaptureH_INTDis(TIMR_TypeDef * TIMRx); +void TIMR_IC_CaptureH_INTClr(TIMR_TypeDef * TIMRx); +uint32_t TIMR_IC_CaptureH_INTStat(TIMR_TypeDef * TIMRx); +void TIMR_IC_CaptureL_INTEn(TIMR_TypeDef * TIMRx); +void TIMR_IC_CaptureL_INTDis(TIMR_TypeDef * TIMRx); +void TIMR_IC_CaptureL_INTClr(TIMR_TypeDef * TIMRx); +uint32_t TIMR_IC_CaptureL_INTStat(TIMR_TypeDef * TIMRx); +void TIMR_IC_CaptureOV_INTEn(TIMR_TypeDef * TIMRx); +void TIMR_IC_CaptureOV_INTDis(TIMR_TypeDef * TIMRx); +void TIMR_IC_CaptureOV_INTClr(TIMR_TypeDef * TIMRx); +uint32_t TIMR_IC_CaptureOV_INTStat(TIMR_TypeDef * TIMRx); + + +#endif //__SWM221_TIMR_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_uart.c b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_uart.c new file mode 100644 index 0000000..4acacd2 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_uart.c @@ -0,0 +1,498 @@ +/****************************************************************************************************************************************** +* ļ: SWM221_uart.c +* ˵: SWM221ƬUARTڹ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.0.0 2016130 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM221.h" +#include "SWM221_uart.h" + + +/****************************************************************************************************************************************** +* : UART_Init() +* ˵: UARTڳʼ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1 +* UART_InitStructure * initStruct UART趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void UART_Init(UART_TypeDef * UARTx, UART_InitStructure * initStruct) +{ + switch((uint32_t)UARTx) + { + case ((uint32_t)UART0): + SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_UART0_Pos); + break; + + case ((uint32_t)UART1): + SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_UART1_Pos); + break; + } + + UART_Close(UARTx); //һЩؼĴֻڴڹرʱ + + UARTx->BAUD &= ~(UART_BAUD_BAUD_Msk | UART_BAUD_FRAC_Msk); + UARTx->BAUD |= (((SystemCoreClock/initStruct->Baudrate - 1) / 16) << UART_BAUD_BAUD_Pos) | + (((SystemCoreClock/initStruct->Baudrate - 1) % 16) << UART_BAUD_FRAC_Pos); + + UARTx->CTRL &= ~(UART_CTRL_DATA9b_Msk | UART_CTRL_PARITY_Msk | UART_CTRL_STOP2b_Msk); + UARTx->CTRL |= (initStruct->DataBits << UART_CTRL_DATA9b_Pos) | + (initStruct->Parity << UART_CTRL_PARITY_Pos) | + (initStruct->StopBits << UART_CTRL_STOP2b_Pos); + + UARTx->FIFO &= ~(UART_FIFO_RXTHR_Msk | UART_FIFO_TXTHR_Msk); + UARTx->FIFO |= (initStruct->RXThreshold << UART_FIFO_RXTHR_Pos) | + (initStruct->TXThreshold << UART_FIFO_TXTHR_Pos); + + UARTx->TOCR &= ~UART_TOCR_TIME_Msk; + UARTx->TOCR |= (1 << UART_TOCR_MODE_Pos) | + (initStruct->TimeoutTime << UART_TOCR_TIME_Pos); + + UARTx->CTRL &= ~(UART_CTRL_RXIE_Msk | UART_CTRL_TXIE_Msk | UART_CTRL_TOIE_Msk); + UARTx->CTRL |= (initStruct->RXThresholdIEn << UART_CTRL_RXIE_Pos) | + (initStruct->TXThresholdIEn << UART_CTRL_TXIE_Pos) | + (initStruct->TimeoutIEn << UART_CTRL_TOIE_Pos); + + switch((uint32_t)UARTx) + { + case ((uint32_t)UART0): + if(initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TimeoutIEn) + { + NVIC_EnableIRQ(UART0_IRQn); + } + else + { + NVIC_DisableIRQ(UART0_IRQn); + } + break; + + case ((uint32_t)UART1): + if(initStruct->RXThresholdIEn | initStruct->TXThresholdIEn | initStruct->TimeoutIEn) + { + NVIC_EnableIRQ(UART1_IRQn); + } + else + { + NVIC_DisableIRQ(UART1_IRQn); + } + break; + } +} + +/****************************************************************************************************************************************** +* : UART_Open() +* ˵: UARTڴ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1 +* : +* ע: +******************************************************************************************************************************************/ +void UART_Open(UART_TypeDef * UARTx) +{ + UARTx->CTRL |= (0x01 << UART_CTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* : UART_Close() +* ˵: UARTڹر +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1 +* : +* ע: +******************************************************************************************************************************************/ +void UART_Close(UART_TypeDef * UARTx) +{ + UARTx->CTRL &= ~(0x01 << UART_CTRL_EN_Pos); +} + +/****************************************************************************************************************************************** +* : UART_WriteByte() +* ˵: һֽ +* : UART_TypeDef * UARTx ָҪõUARTڣȡֵUART0UART1UART4 +* uint8_t data Ҫ͵ֽ +* : +* ע: +******************************************************************************************************************************************/ +void UART_WriteByte(UART_TypeDef * UARTx, uint8_t data) +{ + UARTx->DATA = data; +} + +/****************************************************************************************************************************************** +* : UART_ReadByte() +* ˵: ȡһֽݣָǷValid +* : UART_TypeDef * UARTx ָҪõUARTڣȡֵUART0UART1UART4 +* uint32_t * data յ +* : uint32_t 0 ޴ UART_ERR_PARITY żУ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_ReadByte(UART_TypeDef * UARTx, uint32_t * data) +{ + uint32_t reg = UARTx->DATA; + + *data = (reg & UART_DATA_DATA_Msk); + + if(reg & UART_DATA_PAERR_Msk) return UART_ERR_PARITY; + + return 0; +} + +/****************************************************************************************************************************************** +* : UART_IsTXBusy() +* ˵: UARTǷڷ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1 +* : uint32_t 1 UARTڷ 0 ѷ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_IsTXBusy(UART_TypeDef * UARTx) +{ + return (UARTx->CTRL & UART_CTRL_TXIDLE_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* : UART_IsRXFIFOEmpty() +* ˵: FIFOǷΪգ˵ݿԶȡ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1 +* : uint32_t 1 FIFO 0 FIFOǿ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_IsRXFIFOEmpty(UART_TypeDef * UARTx) +{ + return (UARTx->CTRL & UART_CTRL_RXNE_Msk) ? 0 : 1; +} + +/****************************************************************************************************************************************** +* : UART_IsTXFIFOFull() +* ˵: FIFOǷΪԼд +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1 +* : uint32_t 1 FIFO 0 FIFO +* ע: +******************************************************************************************************************************************/ +uint32_t UART_IsTXFIFOFull(UART_TypeDef * UARTx) +{ + return (UARTx->CTRL & UART_CTRL_TXFF_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : UART_SetBaudrate() +* ˵: ò +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1 +* uint32_t baudrate ҪõIJ +* : +* ע: ҪڴڹʱIJʣʹô˺ǰȵUART_Close()رմ +******************************************************************************************************************************************/ +void UART_SetBaudrate(UART_TypeDef * UARTx, uint32_t baudrate) +{ + UARTx->BAUD &= ~(UART_BAUD_BAUD_Msk | UART_BAUD_FRAC_Msk); + UARTx->BAUD |= (((SystemCoreClock/baudrate - 1) / 16) << UART_BAUD_BAUD_Pos) | + (((SystemCoreClock/baudrate - 1) % 16) << UART_BAUD_FRAC_Pos); +} + +/****************************************************************************************************************************************** +* : UART_GetBaudrate() +* ˵: ѯ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1 +* : uint32_t ǰ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_GetBaudrate(UART_TypeDef * UARTx) +{ + return SystemCoreClock/(((UARTx->BAUD & UART_BAUD_BAUD_Msk) >> UART_BAUD_BAUD_Pos) * 16 + + ((UARTx->BAUD & UART_BAUD_FRAC_Msk) >> UART_BAUD_FRAC_Pos) + 1); +} + +/****************************************************************************************************************************************** +* : UART_CTSConfig() +* ˵: UART CTS +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1 +* uint32_t enable 1 ʹCTS 0 ֹCTS +* uint32_t polarity 0 CTSΪͱʾԷ 1 CTSΪ߱ʾԷ +* : +* ע: +******************************************************************************************************************************************/ +void UART_CTSConfig(UART_TypeDef * UARTx, uint32_t enable, uint32_t polarity) +{ + UARTx->CTSCR &= ~(UART_CTSCR_EN_Msk | UART_CTSCR_POL_Msk); + UARTx->CTSCR |= (enable << UART_CTSCR_EN_Pos) | + (polarity << UART_CTSCR_POL_Pos); +} + +/****************************************************************************************************************************************** +* : UART_CTSLineState() +* ˵: UART CTSߵǰ״̬ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1 +* : uint32_t 0 CTSߵǰΪ͵ƽ 1 CTSߵǰΪߵƽ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_CTSLineState(UART_TypeDef * UARTx) +{ + return (UARTx->CTSCR & UART_CTSCR_STAT_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : UART_RTSConfig() +* ˵: UART RTS +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1 +* uint32_t enable 1 ʹRTS 0 ֹRTS +* uint32_t polarity 0 RTSͱʾԽ 1 RTS߱ʾԽ +* uint32_t threshold RTSصĴֵȡֵUART_RTS_1BYTEUART_RTS_2BYTEUART_RTS_4BYTEUART_RTS_6BYTE +* : +* ע: +******************************************************************************************************************************************/ +void UART_RTSConfig(UART_TypeDef * UARTx, uint32_t enable, uint32_t polarity, uint32_t threshold) +{ + UARTx->RTSCR &= ~(UART_RTSCR_EN_Msk | UART_RTSCR_POL_Msk | UART_RTSCR_THR_Msk); + UARTx->RTSCR |= (enable << UART_RTSCR_EN_Pos) | + (polarity << UART_RTSCR_POL_Pos) | + (threshold << UART_RTSCR_THR_Pos); +} + +/****************************************************************************************************************************************** +* : UART_RTSLineState() +* ˵: UART RTSߵǰ״̬ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1 +* : uint32_t 0 RTSߵǰΪ͵ƽ 1 RTSߵǰΪߵƽ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_RTSLineState(UART_TypeDef * UARTx) +{ + return (UARTx->RTSCR & UART_RTSCR_STAT_Msk) ? 1 : 0; +} + +/****************************************************************************************************************************************** +* : UART_LINConfig() +* ˵: UART LIN +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1 +* uint32_t detectedLen ⵽BreakҪĵ͵ƽȣλȡֵ1--16 +* uint32_t detectedIEn ⵽Breakжʹ +* uint32_t generatedLen Break͵͵ƽȣȡֵ1--15 +* uint32_t generatedIEn Breakжʹ +* : +* ע: +******************************************************************************************************************************************/ +void UART_LINConfig(UART_TypeDef * UARTx, uint32_t detectedLen, uint32_t detectedIEn, uint32_t generatedLen, uint32_t generatedIEn) +{ + UARTx->CFG &= ~(UART_CFG_BRKTXLEN_Msk | UART_CFG_BRKRXLEN_Msk); + UARTx->CFG |= ((detectedLen-1) << UART_CFG_BRKRXLEN_Pos) | + (generatedLen << UART_CFG_BRKTXLEN_Pos); + UARTx->LINCR &= ~(UART_LINCR_BRKDETIE_Msk | UART_LINCR_GENBRKIE_Msk); + UARTx->LINCR |= (detectedIEn << UART_LINCR_BRKDETIE_Pos) | + (generatedIEn << UART_LINCR_GENBRKIE_Pos); +} + +/****************************************************************************************************************************************** +* : UART_LINGenerate() +* ˵: UART LIN/Break +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1 +* : +* ע: +******************************************************************************************************************************************/ +void UART_LINGenerate(UART_TypeDef * UARTx) +{ + UARTx->LINCR |= (1 << UART_LINCR_GENBRK_Pos); +} + +/****************************************************************************************************************************************** +* : UART_LININTEn() +* ˵: LIN жʹ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1 +* uint32_t it interrupt typeЧֵ UART_IT_LIN_DETUART_IT_LIN_GEN 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void UART_LININTEn(UART_TypeDef * UARTx, uint32_t it) +{ + UARTx->LINCR |= it; +} + +/****************************************************************************************************************************************** +* : UART_LININTDis() +* ˵: LIN жϽֹ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1 +* uint32_t it interrupt typeЧֵ UART_IT_LIN_DETUART_IT_LIN_GEN 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void UART_LININTDis(UART_TypeDef * UARTx, uint32_t it) +{ + UARTx->LINCR &= ~it; +} + +/****************************************************************************************************************************************** +* : UART_LININTClr() +* ˵: LIN жϱ־ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1 +* uint32_t it interrupt typeЧֵ UART_IT_LIN_DETUART_IT_LIN_GEN 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void UART_LININTClr(UART_TypeDef * UARTx, uint32_t it) +{ + UARTx->LINCR |= (it << 1); +} + +/****************************************************************************************************************************************** +* : UART_LININTStat() +* ˵: LIN ж״̬ѯ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1 +* uint32_t it interrupt typeЧֵ UART_IT_LIN_DETUART_IT_LIN_GEN 䡰 +* : uint32_t 0 жѷ 0 жδ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_LININTStat(UART_TypeDef * UARTx, uint32_t it) +{ + return (UARTx->LINCR & (it << 1)); +} + +uint8_t UART_LIN_IDParity(uint8_t lin_id) +{ + struct { + uint8_t b0 : 1; + uint8_t b1 : 1; + uint8_t b2 : 1; + uint8_t b3 : 1; + uint8_t b4 : 1; + uint8_t b5 : 1; + uint8_t b6 : 1; + uint8_t b7 : 1; + } * bits = (void *)&lin_id; + + uint8_t id_P0 = (bits->b0 ^ bits->b1 ^ bits->b2 ^ bits->b4); + uint8_t id_P1 = ~(bits->b1 ^ bits->b3 ^ bits->b4 ^ bits->b5); + + return (lin_id & 0x3F) | (id_P0 << 6) | (id_P1 << 7); +} + +uint8_t UART_LIN_Checksum(uint8_t lin_id, uint8_t data[], uint32_t count, bool enhanced_checksum) +{ + uint16_t checksum; + + if(enhanced_checksum && ((lin_id & 0x3F) != 60) && ((lin_id & 0x3F) != 61)) + checksum = lin_id; + else + checksum = 0x00; + + for(int i = 0; i < count; i++) + { + checksum += data[i]; + checksum = (checksum & 0xFF) + (checksum >> 8); + } + + return ~checksum; +} + +/****************************************************************************************************************************************** +* : UART_ABRStart() +* ˵: UART Զʼ⿪ʼ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1 +* uint32_t detectChar Զ⡢㲨ʵļַ +* 8λʱȡֵ0xFF0xFE0xF80x80ֱʾͷ뷢0xFF0xFE0xF80x80 +* 9λʱȡֵ0x1FF0x1FE0x1F80x180ֱʾͷ뷢0x1FF0x1FE0x1F80x180 +* : +* ע: ԶʼʱܿżУ +******************************************************************************************************************************************/ +void UART_ABRStart(UART_TypeDef * UARTx, uint32_t detectChar) +{ + uint32_t bits; + + if((detectChar == 0xFF) || (detectChar == 0x1FF)) bits = 0; + else if((detectChar == 0xFE) || (detectChar == 0x1FE)) bits = 1; + else if((detectChar == 0xF8) || (detectChar == 0x1F8)) bits = 2; + else if((detectChar == 0x80) || (detectChar == 0x180)) bits = 3; + else while(1); + + UARTx->BAUD &= ~(UART_BAUD_ABREN_Msk | UART_BAUD_ABRBIT_Msk); + UARTx->BAUD |= (1 << UART_BAUD_ABREN_Pos) | + (bits << UART_BAUD_ABRBIT_Pos); +} + +/****************************************************************************************************************************************** +* : UART_ABRIsDone() +* ˵: UART ԶǷ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1 +* : uint32_t 0 δ UART_ABR_RES_OK ɣҳɹ UART_ABR_RES_ERR ɣʧܡ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_ABRIsDone(UART_TypeDef * UARTx) +{ + if(UARTx->BAUD & UART_BAUD_ABREN_Msk) + { + return 0; + } + else if(UARTx->BAUD & UART_BAUD_ABRERR_Msk) + { + return UART_ABR_RES_ERR; + } + else + { + return UART_ABR_RES_OK; + } +} + +/****************************************************************************************************************************************** +* : UART_INTEn() +* ˵: жʹ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* uint32_t it interrupt typeЧֵ UART_IT_RX_THRUART_IT_RX_TOUTUART_IT_TX_THRUART_IT_TX_DONE 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void UART_INTEn(UART_TypeDef * UARTx, uint32_t it) +{ + UARTx->CTRL |= it; +} + +/****************************************************************************************************************************************** +* : UART_INTDis() +* ˵: жϽֹ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* uint32_t it interrupt typeЧֵ UART_IT_RX_THRUART_IT_RX_TOUTUART_IT_TX_THRUART_IT_TX_DONE 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void UART_INTDis(UART_TypeDef * UARTx, uint32_t it) +{ + UARTx->CTRL &= ~it; +} + +/****************************************************************************************************************************************** +* : UART_INTClr() +* ˵: жϱ־ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* uint32_t it interrupt typeЧֵ UART_IT_RX_TOUT +* : +* ע: +******************************************************************************************************************************************/ +void UART_INTClr(UART_TypeDef * UARTx, uint32_t it) +{ + if(it & UART_IT_RX_TOUT) + UARTx->TOCR |= UART_TOCR_IFCLR_Msk; +} + +/****************************************************************************************************************************************** +* : UART_INTStat() +* ˵: ж״̬ѯ +* : UART_TypeDef * UARTx ָҪõUARTڣЧֵUART0UART1UART2UART3 +* uint32_t it interrupt typeЧֵ UART_IT_RX_THRUART_IT_RX_TOUTUART_IT_TX_THRUART_IT_TX_DONE 䡰 +* : uint32_t 1 жѷ 0 жδ +* ע: +******************************************************************************************************************************************/ +uint32_t UART_INTStat(UART_TypeDef * UARTx, uint32_t it) +{ + return (((it & UART_IT_RX_THR) && (UARTx->BAUD & UART_BAUD_RXIF_Msk)) || + ((it & UART_IT_RX_TOUT) && (UARTx->BAUD & UART_BAUD_TOIF_Msk)) || + ((it & UART_IT_TX_THR) && (UARTx->BAUD & UART_BAUD_TXIF_Msk)) || + ((it & UART_IT_TX_DONE) && (UARTx->BAUD & UART_BAUD_TXDOIF_Msk))); +} diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_uart.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_uart.h new file mode 100644 index 0000000..d70fe2d --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_uart.h @@ -0,0 +1,100 @@ +#ifndef __SWM221_UART_H__ +#define __SWM221_UART_H__ + +typedef struct { + uint32_t Baudrate; + + uint8_t DataBits; //λλȡֵUART_DATA_8BITUART_DATA_9BIT + + uint8_t Parity; //żУλȡֵUART_PARITY_NONEUART_PARITY_ODDUART_PARITY_EVENUART_PARITY_ONEUART_PARITY_ZERO + + uint8_t StopBits; //ֹͣλλȡֵUART_STOP_1BITUART_STOP_2BIT + + uint8_t RXThreshold; //ȡֵ0--7 + uint8_t RXThresholdIEn; //RX FIFOݸ > RXThresholdʱж + + uint8_t TXThreshold; //ȡֵ0--7 + uint8_t TXThresholdIEn; //TX FIFOݸ <= TXThresholdʱж + + uint8_t TimeoutTime; //ʱʱ = TimeoutTime/(Baudrate/10) + uint8_t TimeoutIEn; //ʱжϣRX FIFOǿգҳ TimeoutTime/(Baudrate/10) ûRXϽյʱж +} UART_InitStructure; + + +#define UART_DATA_8BIT 0 +#define UART_DATA_9BIT 1 + +#define UART_PARITY_NONE 0 +#define UART_PARITY_ODD 1 +#define UART_PARITY_EVEN 3 +#define UART_PARITY_ONE 5 +#define UART_PARITY_ZERO 7 + +#define UART_STOP_1BIT 0 +#define UART_STOP_2BIT 1 + +#define UART_RTS_1BYTE 0 +#define UART_RTS_2BYTE 1 +#define UART_RTS_4BYTE 2 +#define UART_RTS_6BYTE 3 + +#define UART_ABR_RES_OK 1 +#define UART_ABR_RES_ERR 2 + +#define UART_ERR_FRAME 1 +#define UART_ERR_PARITY 2 +#define UART_ERR_NOISE 3 + + +/* Interrupt Type */ +#define UART_IT_RX_THR (1 << UART_CTRL_RXIE_Pos) //RX FIFO Threshold, RX FIFOݸ > RXThreshold +#define UART_IT_RX_TOUT (1 << UART_CTRL_TOIE_Pos) //RX Timeout, TimeoutTime/(Baudrate/10) ûRXϽյ +#define UART_IT_TX_THR (1 << UART_CTRL_TXIE_Pos) //TX FIFO Threshold, TX FIFOݸ <= TXThreshold +#define UART_IT_TX_DONE (1 << UART_CTRL_TXDOIE_Pos) //TX Done, FIFOҷͷλĴѽһλͳȥ + +#define UART_IT_LIN_DET (1 << UART_LINCR_BRKDETIE_Pos) +#define UART_IT_LIN_GEN (1 << UART_LINCR_GENBRKIE_Pos) + + +void UART_Init(UART_TypeDef * UARTx, UART_InitStructure * initStruct); //UARTڳʼ +void UART_Open(UART_TypeDef * UARTx); +void UART_Close(UART_TypeDef * UARTx); + +void UART_WriteByte(UART_TypeDef * UARTx, uint8_t data); //һֽ +uint32_t UART_ReadByte(UART_TypeDef * UARTx, uint32_t * data); //ȡһֽݣָǷValid + +uint32_t UART_IsTXBusy(UART_TypeDef * UARTx); +uint32_t UART_IsRXFIFOEmpty(UART_TypeDef * UARTx); //FIFOǷգԼUART_ReadByte() +uint32_t UART_IsTXFIFOFull(UART_TypeDef * UARTx); //FIFOǷԼUART_WriteByte() + + +void UART_SetBaudrate(UART_TypeDef * UARTx, uint32_t baudrate); //ò +uint32_t UART_GetBaudrate(UART_TypeDef * UARTx); //ȡǰʹõIJ + +void UART_CTSConfig(UART_TypeDef * UARTx, uint32_t enable, uint32_t polarity); +uint32_t UART_CTSLineState(UART_TypeDef * UARTx); + +void UART_RTSConfig(UART_TypeDef * UARTx, uint32_t enable, uint32_t polarity, uint32_t threshold); +uint32_t UART_RTSLineState(UART_TypeDef * UARTx); + +void UART_LINConfig(UART_TypeDef * UARTx, uint32_t detectedLen, uint32_t detectedIEn, uint32_t generatedLen, uint32_t generatedIEn); +void UART_LINGenerate(UART_TypeDef * UARTx); + +void UART_LININTEn(UART_TypeDef * UARTx, uint32_t it); +void UART_LININTDis(UART_TypeDef * UARTx, uint32_t it); +void UART_LININTClr(UART_TypeDef * UARTx, uint32_t it); +uint32_t UART_LININTStat(UART_TypeDef * UARTx, uint32_t it); + +uint8_t UART_LIN_IDParity(uint8_t lin_id); +uint8_t UART_LIN_Checksum(uint8_t lin_id, uint8_t data[], uint32_t count, bool enhanced_checksum); + +void UART_ABRStart(UART_TypeDef * UARTx, uint32_t detectChar); +uint32_t UART_ABRIsDone(UART_TypeDef * UARTx); + + +void UART_INTEn(UART_TypeDef * UARTx, uint32_t it); +void UART_INTDis(UART_TypeDef * UARTx, uint32_t it); +void UART_INTClr(UART_TypeDef * UARTx, uint32_t it); +uint32_t UART_INTStat(UART_TypeDef * UARTx, uint32_t it); + +#endif //__SWM221_UART_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_usart.c b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_usart.c new file mode 100644 index 0000000..2c1a65b --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_usart.c @@ -0,0 +1,195 @@ +/****************************************************************************************************************************************** +* ļ: SWM221_usart.c +* ˵: SWM221ƬUSARTڹ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.0.0 2016130 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM221.h" +#include "SWM221_usart.h" + + +/****************************************************************************************************************************************** +* : USART_Init() +* ˵: USARTڳʼ +* : USART_TypeDef * USARTx ָҪõUARTڣЧֵUSART0 +* USART_InitStructure * initStruct USART趨ֵĽṹ +* : +* ע: +******************************************************************************************************************************************/ +void USART_Init(USART_TypeDef * USARTx, USART_InitStructure * initStruct) +{ + switch((uint32_t)USARTx) + { + case ((uint32_t)USART0): + SYS->CLKEN0 |= (0x01 << SYS_CLKEN0_USART0_Pos); + break; + } + + USART_Close(USARTx); //һЩؼĴֻڴڹرʱ + + USARTx->MR = (0 << USART_MR_MODE_Pos) | + (0 << USART_MR_CLKS_Pos) | + (1 << USART_MR_OVER8_Pos) | + (initStruct->DataBits << USART_MR_NBDATA_Pos) | + (initStruct->Parity << USART_MR_PARITY_Pos) | + (initStruct->StopBits << USART_MR_NBSTOP_Pos); + + USARTx->BAUD = ((SystemCoreClock/initStruct->Baudrate / 8) << USART_BAUD_IDIV_Pos) | + ((SystemCoreClock/initStruct->Baudrate % 8) << USART_BAUD_FDIV_Pos); + + USARTx->RXTO = initStruct->TimeoutTime; + + USARTx->IER = (initStruct->RXReadyIEn << USART_IER_RXRDY_Pos) | + (initStruct->TXReadyIEn << USART_IER_TXRDY_Pos) | + (initStruct->TimeoutIEn << USART_IER_RXTO_Pos); + + if(initStruct->RXReadyIEn | initStruct->TXReadyIEn | initStruct->TimeoutIEn) + { + switch((uint32_t)USARTx) + { + case ((uint32_t)USART0): NVIC_EnableIRQ(USART0_IRQn); break; + } + } +} + + +/****************************************************************************************************************************************** +* : USART_Open() +* ˵: USARTڴ +* : USART_TypeDef * USARTx ָҪõUSARTڣЧֵUSART0 +* : +* ע: +******************************************************************************************************************************************/ +void USART_Open(USART_TypeDef * USARTx) +{ + USARTx->CR = USART_CR_RXEN_Msk | + USART_CR_TXEN_Msk; +} + + +/****************************************************************************************************************************************** +* : USART_Close() +* ˵: USARTڹر +* : USART_TypeDef * USARTx ָҪõUSARTڣЧֵUSART0 +* : +* ע: +******************************************************************************************************************************************/ +void USART_Close(USART_TypeDef * USARTx) +{ + USARTx->CR = USART_CR_RXDIS_Msk | + USART_CR_TXDIS_Msk | + USART_CR_RSTRX_Msk | + USART_CR_RSTTX_Msk | + USART_CR_RSTSTA_Msk; +} + + +/****************************************************************************************************************************************** +* : USART_SetBaudrate() +* ˵: ò +* : USART_TypeDef * USARTx ָҪõUSARTڣЧֵUSART0 +* uint32_t baudrate ҪõIJ +* : +* ע: ҪڴڹʱIJʣʹô˺ǰȵUSART_Close()رմ +******************************************************************************************************************************************/ +void USART_SetBaudrate(USART_TypeDef * USARTx, uint32_t baudrate) +{ + USARTx->BAUD = ((SystemCoreClock/baudrate / 8) << USART_BAUD_IDIV_Pos) | + ((SystemCoreClock/baudrate % 8) << USART_BAUD_FDIV_Pos); +} + + +/****************************************************************************************************************************************** +* : USART_GetBaudrate() +* ˵: ѯ +* : USART_TypeDef * USARTx ָҪõUSARTڣЧֵUSART0 +* : uint32_t ǰ +* ע: +******************************************************************************************************************************************/ +uint32_t USART_GetBaudrate(USART_TypeDef * USARTx) +{ + return SystemCoreClock/(((USARTx->BAUD & USART_BAUD_IDIV_Msk) >> USART_BAUD_IDIV_Pos) * 8 + + ((USARTx->BAUD & USART_BAUD_FDIV_Msk) >> USART_BAUD_FDIV_Pos)); +} + + +/****************************************************************************************************************************************** +* : USART_LINConfig() +* ˵: USART LIN ģʽ +* : USART_TypeDef * USARTx ָҪõUSARTڣЧֵUSART0 +* uint32_t mode LIN ģʽѡ񣬿ȡֵ USART_LIN_MASTERUSART_LIN_SLAVE +* uint32_t checksum Уͣȡֵ USART_CHECKSUM_LIN13USART_CHECKSUM_LIN20 +* uint32_t it interrupt typeЧֵ USART_IT_LIN_IDUSART_IT_LIN_DONE 䡰 +* : +* ע: +******************************************************************************************************************************************/ +void USART_LINConfig(USART_TypeDef * USARTx, uint32_t mode, uint32_t checksum, uint32_t it) +{ + USARTx->MR &= ~USART_MR_MODE_Msk; + USARTx->MR |= (mode << USART_MR_MODE_Pos); + + USARTx->LINMR = (USART_LIN_IGNORE << USART_LINMR_NACT_Pos) | + (0 << USART_LINMR_PARDIS_Pos) | + (0 << USART_LINMR_CHKDIS_Pos) | + (checksum << USART_LINMR_CHKTYP_Pos) | + (0 << USART_LINMR_RDLMOD_Pos) | + (0 << USART_LINMR_FSMDIS_Pos) | + (0 << USART_LINMR_SYNCDIS_Pos); + + USART_INTEn(USARTx, it); +} + + +/****************************************************************************************************************************************** +* : USART_LINStart() +* ˵: USART LIN Master +* : USART_TypeDef * USARTx ָҪõUSARTڣЧֵUSART0 +* uint32_t slave_id ӻ ID +* uint32_t action Ӧ׶εȡֵ USART_LIN_PUBLISHUSART_LIN_SUBSCRIBEUSART_LIN_IGNORE +* uint32_t count Ӧ׶ݸ +* uint32_t checksum Уͣȡֵ USART_CHECKSUM_LIN13USART_CHECKSUM_LIN20 +* : +* ע: +******************************************************************************************************************************************/ +void USART_LINStart(USART_TypeDef * USARTx, uint32_t slave_id, uint32_t action, uint32_t count, uint32_t checksum) +{ + USARTx->LINMR &= ~(USART_LINMR_NACT_Msk | USART_LINMR_DLC_Msk | USART_LINMR_CHKTYP_Msk); + USARTx->LINMR |= (action << USART_LINMR_NACT_Pos) | + ((count - 1) << USART_LINMR_DLC_Pos) | + (checksum << USART_LINMR_CHKTYP_Pos); + + USARTx->LINID = slave_id; +} + + +/****************************************************************************************************************************************** +* : USART_LINResponse() +* ˵: USART LIN Slave Ӧ +* : USART_TypeDef * USARTx ָҪõUSARTڣЧֵUSART0 +* uint32_t action Ӧ׶εĴӻȡֵ USART_LIN_PUBLISHUSART_LIN_SUBSCRIBEUSART_LIN_IGNORE +* uint32_t count Ӧ׶ݸ +* uint32_t checksum Уͣȡֵ USART_CHECKSUM_LIN13USART_CHECKSUM_LIN20 +* : +* ע: +******************************************************************************************************************************************/ +void USART_LINResponse(USART_TypeDef * USARTx, uint32_t action, uint32_t count, uint32_t checksum) +{ + USARTx->LINMR &= ~(USART_LINMR_NACT_Msk | USART_LINMR_DLC_Msk | USART_LINMR_CHKTYP_Msk); + USARTx->LINMR |= (action << USART_LINMR_NACT_Pos) | + ((count - 1) << USART_LINMR_DLC_Pos) | + (checksum << USART_LINMR_CHKTYP_Pos); +} diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_usart.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_usart.h new file mode 100644 index 0000000..5d7526d --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_usart.h @@ -0,0 +1,134 @@ +#ifndef __SWM221_USART_H__ +#define __SWM221_USART_H__ + + +typedef struct { + uint32_t Baudrate; + + uint8_t DataBits; //λλȡֵUSART_DATA_5BITUSART_DATA_6BITUSART_DATA_7BITUSART_DATA_8BITUSART_DATA_9BIT + + uint8_t Parity; //żУλȡֵUSART_PARITY_NONEUSART_PARITY_EVENUSART_PARITY_ODDUSART_PARITY_ZEROUSART_PARITY_ONE + + uint8_t StopBits; //ֹͣλλȡֵUSART_STOP_1BITUSART_STOP_1BIT_5USART_STOP_2BIT + + uint8_t RXReadyIEn; //RHR ǿգԶȡ + uint8_t TXReadyIEn; //THR գд + uint8_t TimeoutIEn; //ʱжϣ TimeoutTime/Baudrate ûRXϽյʱж + uint16_t TimeoutTime; //ʱʱ = TimeoutTime/Baudrate +} USART_InitStructure; + + +#define USART_DATA_5BIT 0 +#define USART_DATA_6BIT 1 +#define USART_DATA_7BIT 2 +#define USART_DATA_8BIT 3 +#define USART_DATA_9BIT (1 << 11) + +#define USART_PARITY_NONE 4 +#define USART_PARITY_EVEN 0 +#define USART_PARITY_ODD 1 +#define USART_PARITY_ZERO 2 +#define USART_PARITY_ONE 3 + +#define USART_STOP_1BIT 0 +#define USART_STOP_1BIT_5 1 //1.5bit +#define USART_STOP_2BIT 2 + +#define USART_LIN_MASTER 10 +#define USART_LIN_SLAVE 11 + +#define USART_LIN_PUBLISH 0 +#define USART_LIN_SUBSCRIBE 1 +#define USART_LIN_IGNORE 2 + +#define USART_CHECKSUM_LIN13 1 +#define USART_CHECKSUM_LIN20 0 + + +/* Interrupt Type */ +#define USART_IT_RX_RDY USART_IER_RXRDY_Msk //RHR ǿգԶȡ +#define USART_IT_TX_RDY USART_IER_TXRDY_Msk //THR գд +#define USART_IT_RX_TO USART_IER_RXTO_Msk //ճʱ +#define USART_IT_TX_EMPTY USART_IER_TXEMPTY_Msk //THR λĴԿ +#define USART_IT_ERR_OVR USART_IER_OVRERR_Msk //Ƴ +#define USART_IT_ERR_FRAME USART_IER_FRAMERR_Msk //֡ʽ +#define USART_IT_ERR_PARITY USART_IER_PARITYERR_Msk //У +#define USART_IT_LIN_BRK USART_IER_BRK_Msk //LIN Break Sent or Received +#define USART_IT_LIN_ID USART_IER_ID_Msk //LIN Identifier Sent or Received +#define USART_IT_LIN_DONE USART_IER_DONE_Msk +#define USART_IT_LIN_BITERR USART_ISR_BITERR_Msk +#define USART_IT_LIN_SYNCERR USART_ISR_SYNCERR_Msk +#define USART_IT_LIN_IDERR USART_ISR_IDERR_Msk +#define USART_IT_LIN_CHKERR USART_ISR_CHKERR_Msk +#define USART_IT_LIN_NAKERR USART_ISR_NAKERR_Msk +#define USART_IT_LIN_HDRTO USART_ISR_HDRTO_Msk + + +void USART_Init(USART_TypeDef * UARTx, USART_InitStructure * initStruct); //UARTڳʼ +void USART_Open(USART_TypeDef * UARTx); +void USART_Close(USART_TypeDef * UARTx); + +void USART_SetBaudrate(USART_TypeDef * UARTx, uint32_t baudrate); //ò +uint32_t USART_GetBaudrate(USART_TypeDef * UARTx); //ȡǰʹõIJ + +void USART_LINConfig(USART_TypeDef * USARTx, uint32_t mode, uint32_t checksum, uint32_t it); +void USART_LINStart(USART_TypeDef * USARTx, uint32_t slave_id, uint32_t action, uint32_t count, uint32_t checksum); +void USART_LINResponse(USART_TypeDef * USARTx, uint32_t action, uint32_t count, uint32_t checksum); + + +static inline void USART_Write(USART_TypeDef * USARTx, uint32_t data) +{ + USARTx->THR = data; +} + + +static inline uint32_t USART_Read(USART_TypeDef * USARTx) +{ + return USARTx->RHR & USART_RHR_DATA_Msk; +} + + +static inline void USART_INTEn(USART_TypeDef * USARTx, uint32_t it) +{ + USARTx->IER = it; +} + + +static inline void USART_INTDis(USART_TypeDef * USARTx, uint32_t it) +{ + USARTx->IDR = it; +} + + +static inline void USART_INTClr(USART_TypeDef * USARTx, uint32_t it) +{ + if(it & USART_IT_RX_TO) + { + USARTx->CR = USART_CR_STTTO_Msk; + } + + if(it & (USART_IT_ERR_OVR | + USART_IT_ERR_FRAME | + USART_IT_ERR_PARITY | + USART_IT_LIN_BRK | + USART_IT_LIN_ID | + USART_IT_LIN_DONE | + USART_IT_LIN_BITERR | + USART_IT_LIN_SYNCERR | + USART_IT_LIN_IDERR | + USART_IT_LIN_CHKERR | + USART_IT_LIN_NAKERR | + USART_IT_LIN_HDRTO)) + { + USARTx->CR = USART_CR_RSTSTA_Msk; + } +} + + +static inline uint32_t USART_INTStat(USART_TypeDef * USARTx, uint32_t it) +{ + return USARTx->ISR & it; +} + + +#endif //__SWM221_USART_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_wdt.c b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_wdt.c new file mode 100644 index 0000000..cb169c6 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_wdt.c @@ -0,0 +1,153 @@ +/****************************************************************************************************************************************** +* ļ: SWM221_wdt.c +* ˵: SWM221ƬWDTŹ +* ֧: http://www.synwit.com.cn/e/tool/gbook/?bid=1 +* ע: +* 汾: V1.0.0 2016130 +* ¼: +* +* +******************************************************************************************************************************************* +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION +* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE +* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN- +* -ECTION WITH THEIR PRODUCTS. +* +* COPYRIGHT 2012 Synwit Technology +*******************************************************************************************************************************************/ +#include "SWM221.h" +#include "SWM221_wdt.h" + + +/****************************************************************************************************************************************** +* : WDT_Init() +* ˵: WDTŹʼ +* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT +* uint32_t int_period жڣȡֵ1--65534λ1/1000룬ȡֵ0ʾرWDTжϹ +* uint32_t rst_period λڣȡֵ1--65534λ1/1000룬ȡֵ0ʾرWDTλ +* : +* ע: ˺ֻоƬϵһΣҪ WDT WDT_ReInit() +******************************************************************************************************************************************/ +void WDT_Init(WDT_TypeDef * WDTx, uint32_t int_period, uint32_t rst_period) +{ + SYS->CLKEN0 |= (1 << SYS_CLKEN0_WDT_Pos); + + WDTx->CR &= ~WDT_CR_CLKDIV_Msk; + WDTx->CR |= (4 << WDT_CR_CLKDIV_Pos); //ʱ32Ƶ + + if(int_period == 0) + { + WDTx->CR &= ~(1 << WDT_CR_INTEN_Pos); + + NVIC_DisableIRQ(WDT_IRQn); + } + else + { + WDTx->CR |= (1 << WDT_CR_INTEN_Pos); + + WDTx->INTVAL = int_period; + + WDTx->IF = 1; + NVIC_EnableIRQ(WDT_IRQn); + } + + if(rst_period == 0) + { + WDTx->CR &= ~(1 << WDT_CR_RSTEN_Pos); + + WDTx->RSTVAL = int_period + 1; + } + else + { + WDTx->CR |= (1 << WDT_CR_RSTEN_Pos); + + WDTx->RSTVAL = rst_period; + } +} + +/****************************************************************************************************************************************** +* : WDT_ReInit() +* ˵: WDTŹ³ʼ +* : ͬ WDT_Init() +* : +* ע: ִ WDT_ReInit() ǰ벻Ҫִ WDT_Stop()Ϊ WDT ֹͣ״̬޷ڲ +******************************************************************************************************************************************/ +void WDT_ReInit(WDT_TypeDef * WDTx, uint32_t int_period, uint32_t rst_period) +{ + int i; + + /* WDT ѾУõ rst_period ȵǰֵСWDT Ҫ 2^16 0 ܴжϺ͸λ + ִһι֤¼ */ + WDT_Feed(WDTx); + + /* ȴ WDT ڲι */ + for(i = 0; i < CyclesPerUs * 300 / 4; i++) __NOP(); + + WDT_Stop(WDTx); + + WDT_Init(WDTx, int_period, rst_period); +} + +/****************************************************************************************************************************************** +* : WDT_Start() +* ˵: ָWDTʼʱ +* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT +* : +* ע: +******************************************************************************************************************************************/ +void WDT_Start(WDT_TypeDef * WDTx) +{ + WDTx->CR |= (1 << WDT_CR_EN_Pos); +} + +/****************************************************************************************************************************************** +* : WDT_Stop() +* ˵: رָWDTֹͣʱ +* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT +* : +* ע: +******************************************************************************************************************************************/ +void WDT_Stop(WDT_TypeDef * WDTx) +{ + WDTx->CR &= ~(1 << WDT_CR_EN_Pos); +} + +/****************************************************************************************************************************************** +* : WDT_Feed() +* ˵: ι´װֵʼʱ +* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT +* : +* ע: +******************************************************************************************************************************************/ +void WDT_Feed(WDT_TypeDef * WDTx) +{ + if(WDTx->CR & WDT_CR_EN_Msk) // WDT ֹͣ״̬£ִι + WDTx->FEED = 0x55; +} + +/****************************************************************************************************************************************** +* : WDT_INTClr() +* ˵: жϱ־ +* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT +* : +* ע: +******************************************************************************************************************************************/ +void WDT_INTClr(WDT_TypeDef * WDTx) +{ + WDTx->IF = 1; +} + +/****************************************************************************************************************************************** +* : WDT_INTStat() +* ˵: ж״̬ѯ +* : WDT_TypeDef * WDTx ָҪõĿŹЧֵWDT +* : int32_t 1 ж 0 δж +* ע: +******************************************************************************************************************************************/ +uint32_t WDT_INTStat(WDT_TypeDef * WDTx) +{ + return WDTx->IF; +} diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_wdt.h b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_wdt.h new file mode 100644 index 0000000..994d28f --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/SWM221_StdPeriph_Driver/SWM221_wdt.h @@ -0,0 +1,16 @@ +#ifndef __SWM221_WDT_H__ +#define __SWM221_WDT_H__ + +void WDT_Init(WDT_TypeDef * WDTx, uint32_t int_period, uint32_t rst_period); +void WDT_ReInit(WDT_TypeDef * WDTx, uint32_t int_period, uint32_t rst_period); +void WDT_Start(WDT_TypeDef * WDTx); //ָWDTʼʱ +void WDT_Stop(WDT_TypeDef * WDTx); //رָWDTֹͣʱ + +void WDT_Feed(WDT_TypeDef * WDTx); //ι´װֵʼʱ + + +void WDT_INTClr(WDT_TypeDef * WDTx); //жϱ־ +uint32_t WDT_INTStat(WDT_TypeDef * WDTx); //ж״̬ѯ + + +#endif //__SWM221_WDT_H__ diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/version-250318 b/SWM221_Lib/SWM221_StdPeriph_Driver/CSL/version-250318 new file mode 100644 index 0000000..e69de29 diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/SWM221_StdPeriph_Driver.ewp b/SWM221_Lib/SWM221_StdPeriph_Driver/SWM221_StdPeriph_Driver.ewp new file mode 100644 index 0000000..220cd5d --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/SWM221_StdPeriph_Driver.ewp @@ -0,0 +1,1141 @@ + + + 3 + + SWM221 + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 36 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 23 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + APP + + $PROJ_DIR$\APP\main.c + + + + CSL\CMSIS + + $PROJ_DIR$\CSL\CMSIS\DeviceSupport\startup\iar\startup_SWM221.s + + + $PROJ_DIR$\CSL\CMSIS\DeviceSupport\system_SWM221.c + + + + CSL\StdPD + + $PROJ_DIR$\CSL\SWM221_StdPeriph_Driver\SWM221_adc.c + + + $PROJ_DIR$\CSL\SWM221_StdPeriph_Driver\SWM221_can.c + + + $PROJ_DIR$\CSL\SWM221_StdPeriph_Driver\SWM221_crc.c + + + $PROJ_DIR$\CSL\SWM221_StdPeriph_Driver\SWM221_div.c + + + $PROJ_DIR$\CSL\SWM221_StdPeriph_Driver\SWM221_dma.c + + + $PROJ_DIR$\CSL\SWM221_StdPeriph_Driver\SWM221_exti.c + + + $PROJ_DIR$\CSL\SWM221_StdPeriph_Driver\SWM221_flash.c + + + $PROJ_DIR$\CSL\SWM221_StdPeriph_Driver\SWM221_gpio.c + + + $PROJ_DIR$\CSL\SWM221_StdPeriph_Driver\SWM221_i2c.c + + + $PROJ_DIR$\CSL\SWM221_StdPeriph_Driver\SWM221_iofilt.c + + + $PROJ_DIR$\CSL\SWM221_StdPeriph_Driver\SWM221_mpu.c + + + $PROJ_DIR$\CSL\SWM221_StdPeriph_Driver\SWM221_port.c + + + $PROJ_DIR$\CSL\SWM221_StdPeriph_Driver\SWM221_pwm.c + + + $PROJ_DIR$\CSL\SWM221_StdPeriph_Driver\SWM221_qei.c + + + $PROJ_DIR$\CSL\SWM221_StdPeriph_Driver\SWM221_qspi.c + + + $PROJ_DIR$\CSL\SWM221_StdPeriph_Driver\SWM221_spi.c + + + $PROJ_DIR$\CSL\SWM221_StdPeriph_Driver\SWM221_timr.c + + + $PROJ_DIR$\CSL\SWM221_StdPeriph_Driver\SWM221_uart.c + + + $PROJ_DIR$\CSL\SWM221_StdPeriph_Driver\SWM221_usart.c + + + $PROJ_DIR$\CSL\SWM221_StdPeriph_Driver\SWM221_wdt.c + + + diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/SWM221_StdPeriph_Driver.eww b/SWM221_Lib/SWM221_StdPeriph_Driver/SWM221_StdPeriph_Driver.eww new file mode 100644 index 0000000..0240d8e --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/SWM221_StdPeriph_Driver.eww @@ -0,0 +1,8 @@ + + + + + $WS_DIR$\SWM221_StdPeriph_Driver.ewp + + + diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/SWM221_StdPeriph_Driver.uvoptx b/SWM221_Lib/SWM221_StdPeriph_Driver/SWM221_StdPeriph_Driver.uvoptx new file mode 100644 index 0000000..3c885aa --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/SWM221_StdPeriph_Driver.uvoptx @@ -0,0 +1,538 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + SWM221 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\out\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + 0 + JL2CM3 + -U59400009 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0SWM221x8.FLM -FS00 -FL020000 -FP0($$Device:SWM221xB$Flash\SWM221xB.FLM) + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + + + + 0 + 1 + SystemCoreClock,0x0A + + + 1 + 1 + ((SYS_TypeDef *) (0x40000000 + 0x00000)) + + + 2 + 1 + ((PWM_TypeDef *) (0x40040000 + 0x6000)) + + + 3 + 1 + ((PORT_TypeDef *) (0x400A0000 + 0x0000)) + + + 4 + 1 + ((SYS_TypeDef *) (0x40000000 + 0x00000)) + + + 5 + 1 + ((PORT_TypeDef *) (0x400A0000 + 0x0010)) + + + + + 1 + 1 + 0x400AA000 + 0 + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + System Viewer\GPIOA + 35905 + + + + + + + APP + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\app\main.c + main.c + 0 + 0 + + + + + CSL\StdPD + 1 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + .\CSL\SWM221_StdPeriph_Driver\SWM221_port.c + SWM221_port.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + .\CSL\SWM221_StdPeriph_Driver\SWM221_gpio.c + SWM221_gpio.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + .\CSL\SWM221_StdPeriph_Driver\SWM221_exti.c + SWM221_exti.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + .\CSL\SWM221_StdPeriph_Driver\SWM221_timr.c + SWM221_timr.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + .\CSL\SWM221_StdPeriph_Driver\SWM221_uart.c + SWM221_uart.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + .\CSL\SWM221_StdPeriph_Driver\SWM221_adc.c + SWM221_adc.c + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + .\CSL\SWM221_StdPeriph_Driver\SWM221_i2c.c + SWM221_i2c.c + 0 + 0 + + + 2 + 9 + 1 + 0 + 0 + 0 + .\CSL\SWM221_StdPeriph_Driver\SWM221_pwm.c + SWM221_pwm.c + 0 + 0 + + + 2 + 10 + 1 + 0 + 0 + 0 + .\CSL\SWM221_StdPeriph_Driver\SWM221_wdt.c + SWM221_wdt.c + 0 + 0 + + + 2 + 11 + 1 + 0 + 0 + 0 + .\CSL\SWM221_StdPeriph_Driver\SWM221_div.c + SWM221_div.c + 0 + 0 + + + 2 + 12 + 1 + 0 + 0 + 0 + .\CSL\SWM221_StdPeriph_Driver\SWM221_spi.c + SWM221_spi.c + 0 + 0 + + + 2 + 13 + 1 + 0 + 0 + 0 + .\CSL\SWM221_StdPeriph_Driver\SWM221_qei.c + SWM221_qei.c + 0 + 0 + + + 2 + 14 + 1 + 0 + 0 + 0 + .\CSL\SWM221_StdPeriph_Driver\SWM221_dma.c + SWM221_dma.c + 0 + 0 + + + 2 + 15 + 1 + 0 + 0 + 0 + .\CSL\SWM221_StdPeriph_Driver\SWM221_can.c + SWM221_can.c + 0 + 0 + + + 2 + 16 + 1 + 0 + 0 + 0 + .\CSL\SWM221_StdPeriph_Driver\SWM221_flash.c + SWM221_flash.c + 0 + 0 + + + 2 + 17 + 1 + 0 + 0 + 0 + .\CSL\SWM221_StdPeriph_Driver\SWM221_iofilt.c + SWM221_iofilt.c + 0 + 0 + + + 2 + 18 + 1 + 0 + 0 + 0 + .\CSL\SWM221_StdPeriph_Driver\SWM221_mpu.c + SWM221_mpu.c + 0 + 0 + + + 2 + 19 + 1 + 0 + 0 + 0 + .\CSL\SWM221_StdPeriph_Driver\SWM221_qspi.c + SWM221_qspi.c + 0 + 0 + + + 2 + 20 + 1 + 0 + 0 + 0 + .\CSL\SWM221_StdPeriph_Driver\SWM221_crc.c + SWM221_crc.c + 0 + 0 + + + 2 + 21 + 1 + 0 + 0 + 0 + .\CSL\SWM221_StdPeriph_Driver\SWM221_usart.c + SWM221_usart.c + 0 + 0 + + + + + CSL\CMSIS + 1 + 0 + 0 + 0 + + 3 + 22 + 1 + 0 + 0 + 0 + .\CSL\CMSIS\DeviceSupport\system_SWM221.c + system_SWM221.c + 0 + 0 + + + 3 + 23 + 2 + 0 + 0 + 0 + .\CSL\CMSIS\DeviceSupport\startup\arm\startup_SWM221.s + startup_SWM221.s + 0 + 0 + + + + diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/SWM221_StdPeriph_Driver.uvprojx b/SWM221_Lib/SWM221_StdPeriph_Driver/SWM221_StdPeriph_Driver.uvprojx new file mode 100644 index 0000000..63bf567 --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/SWM221_StdPeriph_Driver.uvprojx @@ -0,0 +1,532 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + SWM221 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + SWM221xB + Synwit + Synwit.SWM32_DFP.2.1.5 + http://www.synwit.com/pack + IRAM(0x20000000,0x2000) IROM(0x00000000,0x20000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0SWM221xB -FS00 -FL020000 -FP0($$Device:SWM221xB$Flash\SWM221xB.FLM)) + 0 + $$Device:SWM221xB$CSL\SWM221\CMSIS\DeviceSupport\SWM221.h + + + + + + + + + + $$Device:SWM221xB$SVD\SWM221.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\out\ + SWM221_stdperiph_lib + 1 + 0 + 0 + 1 + 1 + .\out\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 1 + fromelf --bin -o "$L@L.bin" "#L" + fromelf --text -a -c -o "$L@L.asm" "#L" + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 1 + 0x0 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x2000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 3 + 1 + 1 + 1 + 0 + 0 + 0 + + + CHIP_SWM221 + + .\CSL\CMSIS\CoreSupport;.\CSL\CMSIS\DeviceSupport;.\CSL\SWM221_StdPeriph_Driver + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + CHIP_SWM221 + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x00000000 + + + + + + + + + + + + + APP + + + main.c + 1 + .\app\main.c + + + + + CSL\StdPD + + + SWM221_port.c + 1 + .\CSL\SWM221_StdPeriph_Driver\SWM221_port.c + + + SWM221_gpio.c + 1 + .\CSL\SWM221_StdPeriph_Driver\SWM221_gpio.c + + + SWM221_exti.c + 1 + .\CSL\SWM221_StdPeriph_Driver\SWM221_exti.c + + + SWM221_timr.c + 1 + .\CSL\SWM221_StdPeriph_Driver\SWM221_timr.c + + + SWM221_uart.c + 1 + .\CSL\SWM221_StdPeriph_Driver\SWM221_uart.c + + + SWM221_adc.c + 1 + .\CSL\SWM221_StdPeriph_Driver\SWM221_adc.c + + + SWM221_i2c.c + 1 + .\CSL\SWM221_StdPeriph_Driver\SWM221_i2c.c + + + SWM221_pwm.c + 1 + .\CSL\SWM221_StdPeriph_Driver\SWM221_pwm.c + + + SWM221_wdt.c + 1 + .\CSL\SWM221_StdPeriph_Driver\SWM221_wdt.c + + + SWM221_div.c + 1 + .\CSL\SWM221_StdPeriph_Driver\SWM221_div.c + + + SWM221_spi.c + 1 + .\CSL\SWM221_StdPeriph_Driver\SWM221_spi.c + + + SWM221_qei.c + 1 + .\CSL\SWM221_StdPeriph_Driver\SWM221_qei.c + + + SWM221_dma.c + 1 + .\CSL\SWM221_StdPeriph_Driver\SWM221_dma.c + + + SWM221_can.c + 1 + .\CSL\SWM221_StdPeriph_Driver\SWM221_can.c + + + SWM221_flash.c + 1 + .\CSL\SWM221_StdPeriph_Driver\SWM221_flash.c + + + SWM221_iofilt.c + 1 + .\CSL\SWM221_StdPeriph_Driver\SWM221_iofilt.c + + + SWM221_mpu.c + 1 + .\CSL\SWM221_StdPeriph_Driver\SWM221_mpu.c + + + SWM221_qspi.c + 1 + .\CSL\SWM221_StdPeriph_Driver\SWM221_qspi.c + + + SWM221_crc.c + 1 + .\CSL\SWM221_StdPeriph_Driver\SWM221_crc.c + + + SWM221_usart.c + 1 + .\CSL\SWM221_StdPeriph_Driver\SWM221_usart.c + + + + + CSL\CMSIS + + + system_SWM221.c + 1 + .\CSL\CMSIS\DeviceSupport\system_SWM221.c + + + startup_SWM221.s + 2 + .\CSL\CMSIS\DeviceSupport\startup\arm\startup_SWM221.s + + + + + + + + + + + + + + + + + SWM221_StdPeriph_Driver + 1 + + + + + diff --git a/SWM221_Lib/SWM221_StdPeriph_Driver/功能说明.txt b/SWM221_Lib/SWM221_StdPeriph_Driver/功能说明.txt new file mode 100644 index 0000000..d5512fb --- /dev/null +++ b/SWM221_Lib/SWM221_StdPeriph_Driver/功能说明.txt @@ -0,0 +1,3 @@ +˵ +1ʹPA5ϵLED˸ +2ͨڴӡ"Hello World!" diff --git a/read_me.txt b/read_me.txt new file mode 100644 index 0000000..d768bdc --- /dev/null +++ b/read_me.txt @@ -0,0 +1,4 @@ +1.串口可收发数据 +2.CAN可收发数据 +3.协议已完成，扩展帧 +4.最新上传代码 V1.0 \ No newline at end of file